Commit Graph

7616 Commits

Author SHA1 Message Date
Duncan Sands d278d35b13 Fix a bunch of unused variable warnings when doing a release
build with gcc-4.6.

llvm-svn: 142350
2011-10-18 12:44:00 +00:00
David Meyer 49045ddb4c Remove NaClMode
llvm-svn: 142338
2011-10-18 05:29:23 +00:00
Craig Topper e20793a4f1 Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147.
llvm-svn: 142177
2011-10-17 05:33:10 +00:00
Craig Topper 96fa597828 Add X86 PEXTR and PDEP instructions.
llvm-svn: 142141
2011-10-16 16:50:08 +00:00
Benjamin Kramer 1930b003fe Add AsmToken::getEndLoc and use it to add ranges to x86 asm register parsing.
<stdin>:1:12: error: register %rax is only available in 64-bit mode
   incl    %rax
           ^~~~

llvm-svn: 142137
2011-10-16 12:10:27 +00:00
Benjamin Kramer d416bae5f2 X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and print ranges for invalid operands.
<stdin>:1:4: error: invalid instruction mnemonic 'abc'
   abc incl    %edi
   ^~~

llvm-svn: 142135
2011-10-16 11:28:29 +00:00
Craig Topper aea148c366 Add X86 BZHI instruction as well as BMI2 feature detection.
llvm-svn: 142122
2011-10-16 07:55:05 +00:00
Craig Topper 0ae8d4d738 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
llvm-svn: 142117
2011-10-16 07:05:40 +00:00
Chris Lattner a3a0681083 Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance
the X86 asmparser to produce ranges in the one case that was annoying me, for example:

test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
              ^~~~~~~

It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use 
ranges where appropriate if someone is interested.

llvm-svn: 142106
2011-10-16 04:47:35 +00:00
Craig Topper 25ea4e5ad3 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
llvm-svn: 142105
2011-10-16 03:51:13 +00:00
Craig Topper 6c8879e3ab Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7.
llvm-svn: 142089
2011-10-16 00:21:51 +00:00
Craig Topper 27ad12539d Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
llvm-svn: 142082
2011-10-15 20:46:47 +00:00
Benjamin Kramer 5fb5e3b384 SmallVector -> array
llvm-svn: 142073
2011-10-15 13:28:31 +00:00
Evan Cheng 06fdaeb5d9 A few 80-col violations.
llvm-svn: 141988
2011-10-14 20:36:23 +00:00
Craig Topper 965de2c197 Add X86 ANDN instruction. Including instruction selection.
llvm-svn: 141947
2011-10-14 07:06:56 +00:00
Craig Topper 3657fe4b17 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
llvm-svn: 141939
2011-10-14 03:21:46 +00:00
Jakob Stoklund Olesen d9444d455e Ban rematerializable instructions with side effects.
TableGen infers unmodeled side effects on instructions without a
pattern.  Fix some instruction definitions where that was overlooked.

Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.

llvm-svn: 141929
2011-10-14 01:00:49 +00:00
Jakob Stoklund Olesen eafa9d50c2 V_SET0 has no side effects.
TableGen will mark any pattern-less instruction as having unmodeled side
effects. This is extra bad for V_SET0 which gets rematerialized a lot.

This was part of the cause for PR11125, but the real bug was fixed
in r141923.

llvm-svn: 141924
2011-10-14 00:39:50 +00:00
Eli Friedman a5abd03a8d Simplify assertion, and avoid undefined shift. Based on patch by Ahmed Charles.
llvm-svn: 141912
2011-10-13 23:27:48 +00:00
Bill Wendling 25f6d3e321 More closely follow libgcc, which has code after the `ret' instruction to
release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.

llvm-svn: 141859
2011-10-13 08:24:19 +00:00
Bill Wendling 063f55ffdd Revert r141854 because it was causing failures:
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h

llvm-svn: 141857
2011-10-13 07:48:07 +00:00
Bill Wendling 22a690e3db Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I.
llvm-svn: 141856
2011-10-13 07:42:32 +00:00
Craig Topper 8cc9388073 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
llvm-svn: 141854
2011-10-13 07:09:14 +00:00
Craig Topper 2fdcb1f045 Add 'implicit EFLAGS' to patterns for popcnt and lzcnt
llvm-svn: 141853
2011-10-13 06:18:52 +00:00
Nick Lewycky 064c1c0e77 Fix indent in comment.
llvm-svn: 141749
2011-10-12 00:14:12 +00:00
Craig Topper 63bc541196 Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as modifying EFLAGS.
llvm-svn: 141656
2011-10-11 07:13:09 +00:00
Craig Topper 0fbca75c17 Make Ivy Bridge 16-bit floating point conversion instructions require AVX.
llvm-svn: 141654
2011-10-11 07:01:37 +00:00
Craig Topper 271064e873 Add X86 LZCNT instruction. Including instruction selection support.
llvm-svn: 141651
2011-10-11 06:44:02 +00:00
Craig Topper a697852386 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
llvm-svn: 141642
2011-10-11 04:34:23 +00:00
Lang Hames f22f46bf25 Fixed natural stack alignment for Linux x86-32. Thanks Eli.
llvm-svn: 141616
2011-10-11 00:51:36 +00:00
Lang Hames de7ab801cc Add a natural stack alignment field to TargetData, and prevent InstCombine from
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.

The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.

llvm-svn: 141599
2011-10-10 23:42:08 +00:00
Eli Friedman 8ec0897db6 Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102.
llvm-svn: 141585
2011-10-10 22:28:47 +00:00
Benjamin Kramer 874c519337 X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge.
llvm-svn: 141571
2011-10-10 19:35:07 +00:00
Nadav Rotem 814598563f Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the
instruction set has no 64-bit SRA support.

llvm-svn: 141570
2011-10-10 19:31:45 +00:00
Benjamin Kramer 42c0330a79 X86: Add patterns for the movbe instruction (mov + bswap, only available on atom)
llvm-svn: 141563
2011-10-10 18:34:56 +00:00
Craig Topper a14c5723eb Put a bunch of calls to ToggleFeature behind proper if statements.
llvm-svn: 141527
2011-10-10 05:34:02 +00:00
Craig Topper fe9179fa4f Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
llvm-svn: 141505
2011-10-09 07:31:39 +00:00
Jakob Stoklund Olesen 513d1213cc Prevent potential NOREX bug.
A GR8_NOREX virtual register is created when extrating a sub_8bit_hi
sub-register:

  %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1
  TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2

If such a live range is ever split, its register class must not be
inflated to GR8.  The sub-register copy can only target GR8_NOREX.

I dont have a test case for this theoretical bug.

llvm-svn: 141500
2011-10-08 20:20:03 +00:00
Jakob Stoklund Olesen 729abd360e Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

llvm-svn: 141499
2011-10-08 18:28:28 +00:00
Jakob Stoklund Olesen 464fcc0035 Constrain both operands on MOVZX32_NOREXrr8.
This instruction is explicitly encoded without an REX prefix, so both
operands but be *_NOREX.

Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX
constraints are not satisfied.

This fixes a miscompilation in 20040709-2 in the gcc test suite.

llvm-svn: 141410
2011-10-07 20:15:54 +00:00
Evan Cheng 74db300f37 High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336
llvm-svn: 141371
2011-10-07 17:21:44 +00:00
Craig Topper d9cfddc5cd Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
llvm-svn: 141358
2011-10-07 07:02:24 +00:00
Craig Topper bf136764ae Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
llvm-svn: 141354
2011-10-07 05:53:50 +00:00
Craig Topper 5aebebe18d Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
llvm-svn: 141353
2011-10-07 05:35:38 +00:00
Craig Topper 23eb468b1f Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
llvm-svn: 141274
2011-10-06 06:44:41 +00:00
Peter Collingbourne fb3d935649 Build system infrastructure for multiple tblgens.
llvm-svn: 141266
2011-10-06 01:51:51 +00:00
Jakob Stoklund Olesen ee9b576a2a Override TRI::getSubClassWithSubReg for X86.
There are fewer registers with sub_8bit sub-registers in 32-bit mode
than in 64-bit mode.  In 32-bit mode, sub_8bit behaves the same as
sub_8bit_hi.

llvm-svn: 141206
2011-10-05 20:26:33 +00:00
Craig Topper b58a9665bd Change C++ style comments to C style comments in X86 disassembler. Patch from Joe Abbey.
llvm-svn: 141162
2011-10-05 03:29:32 +00:00
Owen Anderson 0ca562ec4c Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
llvm-svn: 141135
2011-10-04 23:26:17 +00:00
Craig Topper f18c896337 Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
llvm-svn: 141065
2011-10-04 06:30:42 +00:00