29dd7f2090
[ASan] Fix lifetime intrinsics handling. Now for each intrinsic we check if it describes one of 'interesting' allocas. Assume that allocas can go through casts and phi-nodes before apperaring as llvm.lifetime arguments
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llvm-svn: 171153
2012-12-27 08:50:58 +00:00
9aa00f0363
DAGCombinerInformation: add a getter that exposes the dagcombine level.
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llvm-svn: 171152
2012-12-27 08:44:35 +00:00
75ceb5b56b
Fix new[]/delete mismatch in FullDependence spotted by AddressSanitizer
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llvm-svn: 171150
2012-12-27 08:40:37 +00:00
f85d3ee072
docs: Update the benchmark with updated perf numbers.
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llvm-svn: 171149
2012-12-27 08:32:44 +00:00
2a054b4475
On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
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register. In most cases we actually compare or select YMM-sized registers
and mixing the two types creates horrible code. This commit optimizes
some of the transition sequences.
PR14657.
llvm-svn: 171148
2012-12-27 08:15:45 +00:00
8e5d80eba3
AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook.
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The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization
and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps.
No new testcase because the original testcases still work.
llvm-svn: 171146
2012-12-27 07:45:10 +00:00
757f3fc394
Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT.
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llvm-svn: 171143
2012-12-27 07:16:08 +00:00
b1dd52450e
Refactor DAGCombinerInfo. Change the different booleans that indicate if we are before or after different runs of DAGCo, with the CombineLevel enum.
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Also, added a new API for checking if we are running before or after the LegalizeVectorOps phase.
llvm-svn: 171142
2012-12-27 06:47:41 +00:00
09ce4b9efe
Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again.
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llvm-svn: 171141
2012-12-27 06:34:54 +00:00
8f0b73942e
Update tablegen parser to allow defm names to start with #NAME.
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llvm-svn: 171140
2012-12-27 06:32:52 +00:00
396cb795bc
Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation.
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llvm-svn: 171137
2012-12-27 03:35:44 +00:00
c7910828e4
Mark the divide instructions as hasSideEffects=0.
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llvm-svn: 171136
2012-12-27 03:01:18 +00:00
3bf29fda91
For the dwarf5 split debug info code split out the string section
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per compile unit/skeleton compile unit. Update tests accordingly.
llvm-svn: 171133
2012-12-27 02:14:01 +00:00
c8a88ee691
FileCheck-ize.
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llvm-svn: 171132
2012-12-27 02:13:58 +00:00
d6152aabbb
FileCheck-ize.
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llvm-svn: 171131
2012-12-27 02:13:55 +00:00
5b807aaa38
Add hasSideEffects=0 to CMP*rr_REV.
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llvm-svn: 171130
2012-12-27 02:08:46 +00:00
b3f6751df5
whitespace
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llvm-svn: 171129
2012-12-27 02:04:12 +00:00
89e8607755
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them.
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llvm-svn: 171128
2012-12-27 02:01:33 +00:00
5a6acfa4c8
Right now all of the relocations are 32-bit dwarf, and the relocation
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information doesn't return an addend for Rel relocations. Go ahead
and use this information to fix relocation handling inside dwarfdump
for 32-bit ELF REL.
llvm-svn: 171126
2012-12-27 01:07:07 +00:00
5350cd314b
If all of the write objects are identified then we can vectorize the loop even if the read objects are unidentified.
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PR14719.
llvm-svn: 171124
2012-12-26 23:30:53 +00:00
c557343956
Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem.
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llvm-svn: 171123
2012-12-26 23:27:57 +00:00
d47a70de9f
Add hasSideEffects=0 to some atomic instructions.
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llvm-svn: 171122
2012-12-26 23:08:12 +00:00
af2372087b
Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects.
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llvm-svn: 171121
2012-12-26 22:19:23 +00:00
fca2acb618
80 columns. No functionality change.
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llvm-svn: 171120
2012-12-26 22:00:49 +00:00
90053a1214
Remove mid-optimizer warning. This situation should be handled differently,
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such as by a compiler warning, a check in clang -fsanitizer=undefined, being
optimized to unreachable, or a combination of the above. PR14722.
llvm-svn: 171119
2012-12-26 22:00:35 +00:00
1b8c0750ee
Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier.
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llvm-svn: 171118
2012-12-26 21:30:22 +00:00
18f2675e9b
Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns.
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llvm-svn: 171117
2012-12-26 21:04:30 +00:00
0bbf81e311
Update the docs with the new workload that was added.
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llvm-svn: 171115
2012-12-26 19:45:00 +00:00
3f7c4f36ba
LoopVectorizer: Optimize the vectorization of consecutive memory access when the iteration step is -1
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llvm-svn: 171114
2012-12-26 19:08:17 +00:00
8d5f8dc485
Fix comment typo
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llvm-svn: 171113
2012-12-26 18:15:42 +00:00
5eb5bf8b46
[msan] Raise alignment of origin stores/loads when possible.
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Origin alignment is as high as the alignment of the corresponding application
location, but never less than 4.
llvm-svn: 171110
2012-12-26 11:55:09 +00:00
d8be0c510c
[msan] Expand the file comment with track-origins info.
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llvm-svn: 171109
2012-12-26 10:59:00 +00:00
d14720dced
Fix quoting in configure. Patch by Krzysztof Parzyszek!
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llvm-svn: 171108
2012-12-26 10:48:49 +00:00
24f316e4db
Merge still more SSE/AVX instruction definitions.
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llvm-svn: 171103
2012-12-26 07:54:43 +00:00
af629e2700
Merge more SSE/AVX instruction definitions.
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llvm-svn: 171102
2012-12-26 07:20:35 +00:00
bf99a426cb
TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in fieldFromInstruction().
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Reported by Yang Yongyong, thanks!
llvm-svn: 171101
2012-12-26 06:43:14 +00:00
a1d2436b5f
revert an accidental commit.
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llvm-svn: 171098
2012-12-26 06:16:03 +00:00
65fe30450d
Fix 80 column violation.
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llvm-svn: 171097
2012-12-26 06:15:53 +00:00
f4d0fe8fcd
Fix class name in comment.
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llvm-svn: 171096
2012-12-26 06:15:09 +00:00
59747c4dbd
Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions.
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llvm-svn: 171095
2012-12-26 06:14:15 +00:00
7375d35711
Doc: add fmuladd to the list of vectorizeable functions. Thanks hfinkel.
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llvm-svn: 171094
2012-12-26 06:03:35 +00:00
8a48677586
Remove 'v' from mnemonic to fix asm matching failures.
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llvm-svn: 171093
2012-12-26 06:02:15 +00:00
b4ef0fa3a1
Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions.
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llvm-svn: 171092
2012-12-26 05:49:15 +00:00
5267bb71b8
Reformat the docs.
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llvm-svn: 171091
2012-12-26 04:59:20 +00:00
0e1d662d56
white space
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llvm-svn: 171090
2012-12-26 04:58:12 +00:00
a2594dd5f0
Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN
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llvm-svn: 171087
2012-12-26 04:36:03 +00:00
97730a0d6a
Merge an AVX/SSE 256-bit and 128-bit multiclass.
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llvm-svn: 171086
2012-12-26 03:56:47 +00:00
8b59746390
Mark VANDNPD/VANDNPDS as not commutable.
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llvm-svn: 171085
2012-12-26 03:48:10 +00:00
40aa3285f4
llvm/test/CodeGen/X86: FileCheck-ize two tests in r171083.
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llvm-svn: 171084
2012-12-26 03:19:30 +00:00
334f685328
llvm/test/CodeGen/X86: Disable avx in two tests corresponding to r171082.
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llvm-svn: 171083
2012-12-26 03:08:55 +00:00
Alexey Samsonov