9329e780cd
Fix PR1761 by not printing (rip) suffix when in -static mode.
...
Evan, please review this.
llvm-svn: 43680
2007-11-04 19:23:28 +00:00
296160d443
Fix PR1763 by allowing the 'q' constraint to work with 64-bit
...
regs on x86-64.
llvm-svn: 43669
2007-11-04 06:51:12 +00:00
2b93a20b09
Unbreak tailcall opt.
...
llvm-svn: 43646
2007-11-02 17:45:40 +00:00
389d430c49
add a note
...
llvm-svn: 43642
2007-11-02 17:04:20 +00:00
e453ff4913
Missing a getNumOperands check.
...
llvm-svn: 43630
2007-11-02 01:26:22 +00:00
b7cabbe295
Silence, accersed warning
...
llvm-svn: 43609
2007-11-01 08:51:44 +00:00
419b6d7ce4
Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold
...
and by restructuring the X86 version.
New I just have to move this to a common place :-)
llvm-svn: 43554
2007-10-31 14:39:58 +00:00
063f177300
Make ARM an X86 memcpy expansion more similar to each other.
...
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.
This should not change generated code.
llvm-svn: 43552
2007-10-31 11:52:06 +00:00
b066c1f216
Make i64=expand_vector_elt(v2i64) work in 32-bit mode.
...
llvm-svn: 43535
2007-10-31 00:32:36 +00:00
d50c8bcef6
Add missing SSE builtins: CVTPD2PI, CVTPS2PI,
...
CVTTPD2PI, CVTTPS2PI, CVTPI2PD, CVTPI2PS.
llvm-svn: 43523
2007-10-30 22:15:38 +00:00
b508c53c63
Fix for visibility warnings generated by gcc-4.2.
...
llvm-svn: 43500
2007-10-30 13:14:37 +00:00
6aa304e529
Add missing MMX PSUBQ.
...
llvm-svn: 43488
2007-10-30 01:18:38 +00:00
e106e2f142
Enable more fold (sext (load x)) -> (sext (truncate (sextload x)))
...
transformation. Previously, it's restricted by ensuring the number of load uses
is one. Now the restriction is loosened up by allowing setcc uses to be
"extended" (e.g. setcc x, c, eq -> setcc sext(x), sext(c), eq).
llvm-svn: 43465
2007-10-29 19:58:20 +00:00
7b3f7feaea
Avoid doing something dumb like rewriting using a 64-bit iv in 32-bit mode.
...
llvm-svn: 43446
2007-10-29 07:57:50 +00:00
909a54ccd4
add a note.
...
llvm-svn: 43444
2007-10-29 06:19:48 +00:00
5e99fd8c0d
Add support for the x86-64 'q' regigster modifier, and add support for the
...
b/h/w/k/q inline asm memory modifiers, which are just ignored. This fixes
PR1748 and CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll
llvm-svn: 43430
2007-10-29 03:09:07 +00:00
c826ac533b
New entry.
...
llvm-svn: 43420
2007-10-28 04:01:09 +00:00
d07d6a411c
Fix off-by-one stack offset computations (dwarf information) for callee-saved
...
registers in case, when FP pointer was eliminated. This should fixes misc. random
EH-related crahses, when stuff is compiled with -fomit-frame-pointer.
Thanks Duncan for nailing this bug!
llvm-svn: 43381
2007-10-26 09:13:24 +00:00
7f3d02471d
Loosen up iv reuse to allow reuse of the same stride but a larger type when truncating from the larger type to smaller type is free.
...
e.g.
Turns this loop:
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
movw %dx, %si
LBB1_2: # bb
movl L_X$non_lazy_ptr, %edi
movw %si, (%edi)
movl L_Y$non_lazy_ptr, %edi
movw %dx, (%edi)
addw $4, %dx
incw %si
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
into
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
LBB1_2: # bb
movl L_X$non_lazy_ptr, %esi
movw %cx, (%esi)
movl L_Y$non_lazy_ptr, %esi
movw %dx, (%esi)
addw $4, %dx
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
llvm-svn: 43375
2007-10-26 01:56:11 +00:00
bf474959a3
Fix the folding of multiplication into addresses on x86, which was broken
...
by the recent {U,S}MUL_LOHI changes.
llvm-svn: 43230
2007-10-22 20:22:24 +00:00
c92446af1f
Fix an unfolding bug.
...
llvm-svn: 43212
2007-10-22 03:03:20 +00:00
8ee70112ea
Allow for copysign having f80 second argument.
...
Fixes 5550319.
llvm-svn: 43205
2007-10-21 01:07:44 +00:00
45e096c77e
Resolve unfold tables ambiguity.
...
llvm-svn: 43194
2007-10-19 23:50:58 +00:00
35ff79370b
Local spiller optimization:
...
Turn a store folding instruction into a load folding instruction. e.g.
xorl %edi, %eax
movl %eax, -32(%ebp)
movl -36(%ebp), %eax
orl %eax, -32(%ebp)
=>
xorl %edi, %eax
orl -36(%ebp), %eax
mov %eax, -32(%ebp)
This enables the unfolding optimization for a subsequent instruction which will
also eliminate the newly introduced store instruction.
llvm-svn: 43192
2007-10-19 21:23:22 +00:00
846c19dd70
Add support for byval function whose argument is not 32 bit aligned.
...
To do this it is necessary to add a "always inline" argument to the
memcpy node. For completeness I have also added this node to memmove
and memset. I have also added getMem* functions, because the extra
argument makes it cumbersome to use getNode and because I get confused
by it :-)
llvm-svn: 43172
2007-10-19 10:41:11 +00:00
463e2ab0ac
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
...
- Fix some copy+paste bugs.
llvm-svn: 43153
2007-10-18 22:40:57 +00:00
aa9a225699
Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
...
llvm-svn: 43150
2007-10-18 21:29:24 +00:00
7f68cf0d57
Fix a typo
...
llvm-svn: 43144
2007-10-18 19:28:55 +00:00
12d5da49d3
Change fp to sint legalization on x86-32 to do 2 x i32
...
loads instead of 1 x i64 loads. This doesn't change any functionality yet.
llvm-svn: 43068
2007-10-17 06:17:29 +00:00
693cbeadff
fix some funny indentation, add comments.
...
llvm-svn: 43066
2007-10-17 06:02:13 +00:00
e5530a35d4
Check for invalid cc's in f80 select.
...
llvm-svn: 43033
2007-10-16 18:09:08 +00:00
b3d58b98d0
Correction to tail call optimization code. The new return address
...
was stored to the acutal stack slot before the parameters were
lowered to their stack slot. This could cause arguments to be
overwritten by the return address if the called function had less
parameters than the caller function. The update should remove the
last failing test case of llc-beta: SPASS.
llvm-svn: 43027
2007-10-16 09:05:00 +00:00
7bcfd8f880
LowerFP_TO_SINT must not create a stack object if it's not needed.
...
llvm-svn: 43004
2007-10-15 20:11:21 +00:00
4099f4f91a
Unbreak x86-64.
...
llvm-svn: 42962
2007-10-14 10:09:39 +00:00
cdf3609130
Revert 42908 for now.
...
llvm-svn: 42960
2007-10-14 05:57:21 +00:00
29af26f147
Clarify that fastcc has a problem with nested function
...
trampolines, rather than with nested functions themselves.
llvm-svn: 42955
2007-10-13 07:38:37 +00:00
7082dcf605
Change unfoldMemoryOperand(). User is now responsible for passing in the
...
register used by the unfolded instructions. User can also specify whether to
unfold the load, the store, or both.
llvm-svn: 42946
2007-10-13 02:35:06 +00:00
e8d0bf2669
Correcting the corrections. Bad bad baaad emacs!
...
llvm-svn: 42935
2007-10-12 21:53:12 +00:00
1f0da1fefb
Corrected many typing errors. And removed 'nest' parameter handling
...
for fastcc from X86CallingConv.td. This means that nested functions
are not supported for calling convention 'fastcc'.
llvm-svn: 42934
2007-10-12 21:30:57 +00:00
a6286bd502
Due to the new tail call optimization, trampolines can no
...
longer be created for fastcc functions.
llvm-svn: 42925
2007-10-12 19:37:31 +00:00
409fa443fc
Update.
...
llvm-svn: 42922
2007-10-12 18:22:55 +00:00
dc35bd79ca
Change the names used for internal labels to use the current
...
function symbol name instead of a codegen-assigned function
number.
Thanks Evan! :-)
llvm-svn: 42908
2007-10-12 14:53:36 +00:00
8d978da3b0
Mark vector ctpop, cttz, and ctlz as Expand on x86.
...
llvm-svn: 42905
2007-10-12 14:09:42 +00:00
09c0fe0a7f
Fold load / store into MOV32to32_ and MOV16to16_.
...
llvm-svn: 42895
2007-10-12 08:38:01 +00:00
f8c23f074b
Flag MOV32to32_ with EXTRACT_SUBREG. They should not be scheduled apart.
...
llvm-svn: 42894
2007-10-12 07:55:53 +00:00
482732af9d
Set ISD::FPOW to Expand.
...
llvm-svn: 42881
2007-10-11 23:21:31 +00:00
62f65edc32
Add missing argument to PALIGNR
...
llvm-svn: 42874
2007-10-11 20:58:37 +00:00
9ccea99165
Added tail call optimization to the x86 back end. It can be
...
enabled by passing -tailcallopt to llc. The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
elf/pic enabled + callee is in module + callee has
visibility protected or hidden
llvm-svn: 42870
2007-10-11 19:40:01 +00:00
e8c8ef5234
LowerIntegerDivOrRem no longer exists.
...
llvm-svn: 42787
2007-10-09 15:45:13 +00:00
51554bf30e
Fix grammar in a comment.
...
llvm-svn: 42786
2007-10-09 15:44:37 +00:00
6d28778bfd
This is done.
...
llvm-svn: 42785
2007-10-09 15:42:21 +00:00
82bc90ac60
Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte.
...
llvm-svn: 42783
2007-10-09 07:14:53 +00:00
f5ec10b64c
Bug fix. X86 was emitting redundant setcc and test instructions before a conditional move.
...
llvm-svn: 42774
2007-10-08 22:16:29 +00:00
a160361c85
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
...
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
llvm-svn: 42762
2007-10-08 18:33:35 +00:00
18109c88c3
Allow x86 compare to be commutable by default.
...
llvm-svn: 42761
2007-10-08 18:27:46 +00:00
b20757d578
disable this entirely: it is causing use of invalidated iterators and infinite looping.
...
llvm-svn: 42739
2007-10-07 22:00:31 +00:00
8dd66ab3b2
Fix many regressions on x86 by avoiding dereferencing the end iterator.
...
llvm-svn: 42738
2007-10-07 21:53:12 +00:00
67ac2de8bf
Oops, I really wanted to commit this part also :)
...
llvm-svn: 42700
2007-10-06 16:39:43 +00:00
c59496f737
Move merge code into new helper function.
...
llvm-svn: 42699
2007-10-06 16:17:49 +00:00
f4b5d491df
Added DAG xforms. e.g.
...
(vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr)
(vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
Remove x86 specific patterns.
llvm-svn: 42677
2007-10-06 02:46:29 +00:00
1151ffde70
Commute x86 cmove instructions by swapping the operands and change the condition
...
to its inverse.
Testing this as llcbeta
llvm-svn: 42661
2007-10-05 23:13:21 +00:00
42a13757de
This is done.
...
llvm-svn: 42656
2007-10-05 22:34:59 +00:00
484cab7a2f
Enable convertToThreeAddress for X86 by default.
...
llvm-svn: 42655
2007-10-05 22:31:10 +00:00
d3ccf00870
INC64_32r -> LEA64_32r is better than INC64_32r -> LEA32r, but it still can
...
cause performance degradation.
llvm-svn: 42653
2007-10-05 21:55:32 +00:00
fa2c828687
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g.
...
leal 1(%ecx), %edi, which requires 67H prefix.
llvm-svn: 42647
2007-10-05 20:34:26 +00:00
aac0f8e351
Add support to convert more 64-bit instructions to 3-address instructions.
...
llvm-svn: 42642
2007-10-05 18:20:36 +00:00
97eba74a52
ADC and SBB uses EFLAGS.
...
llvm-svn: 42640
2007-10-05 17:59:57 +00:00
43c29dce18
Change a few more spaces to tabs in assembly output.
...
llvm-svn: 42638
2007-10-05 15:58:41 +00:00
b074f23dff
Change a space to a tab in the assembly output of a .globl directive
...
for consistency.
llvm-svn: 42637
2007-10-05 15:54:58 +00:00
a8a9c15e30
Testing convertToThreeeAddress as X86 llcbeta.
...
llvm-svn: 42630
2007-10-05 08:04:01 +00:00
a851e2b92e
Added storeRegToAddr, loadRegFromAddr, and unfoldMemoryOperand's.
...
llvm-svn: 42624
2007-10-05 01:34:55 +00:00
6912b50958
Not needed any more.
...
llvm-svn: 42623
2007-10-05 01:34:14 +00:00
1f2b5f0e13
add a note.
...
llvm-svn: 42607
2007-10-04 15:47:27 +00:00
c731c97fac
Use empty() member functions when that's what's being tested for instead
...
of comparing begin() and end().
llvm-svn: 42585
2007-10-03 19:26:29 +00:00
4bdb84fe53
add a note
...
llvm-svn: 42579
2007-10-03 17:10:03 +00:00
21ba176c4b
Bill's example is still not enough to repro this, but it has other issues that
...
seem significant as well.
llvm-svn: 42564
2007-10-03 03:40:24 +00:00
3efc0758ae
Another micro-opt.
...
llvm-svn: 42554
2007-10-02 21:49:31 +00:00
f214ff8701
Another missed optimization with LICM.
...
llvm-svn: 42552
2007-10-02 21:43:06 +00:00
855011e5c6
Small label changes.
...
llvm-svn: 42549
2007-10-02 21:02:53 +00:00
4eb7ca4b4c
Now with source code.
...
llvm-svn: 42548
2007-10-02 21:01:16 +00:00
96ed3bb2d4
Now with LL code!
...
llvm-svn: 42547
2007-10-02 20:54:32 +00:00
9c4d61b523
Another missed optimization.
...
llvm-svn: 42546
2007-10-02 20:42:59 +00:00
88ea107fdb
Micro-optimization -- missed LICM opportunity.
...
llvm-svn: 42542
2007-10-02 19:55:05 +00:00
1f79ba6fe6
Refactor code to add load / store folded instructions -> register only
...
instructions reverse map.
llvm-svn: 42509
2007-10-01 23:44:33 +00:00
a1b7e95039
Typo. X86comi doesn't read / write chain's.
...
llvm-svn: 42492
2007-10-01 18:12:48 +00:00
0b7cf862bc
AsmPrinters overriding getAnalysisUsage should call super.
...
And not super's super, either.
llvm-svn: 42482
2007-09-30 13:39:29 +00:00
5fb5a1f389
Enabling new condition code modeling scheme.
...
llvm-svn: 42459
2007-09-29 00:00:36 +00:00
6c04ac1db0
Refactor the memcpy lowering for the x86 target.
...
The only generated code difference is that now we call memcpy when
the size of the array is unknown. This matches GCC behavior and is
better since the run time value can be arbitrarily large.
llvm-svn: 42433
2007-09-28 12:53:01 +00:00
1f516560d1
Stop inventing new words. :-)
...
llvm-svn: 42429
2007-09-28 01:35:02 +00:00
edfc5b2204
Pessimisively assume ADJCALLSTACKDOWN / ADJCALLSTACKUP (which becomes sub / add) clobbers EFLAGS.
...
llvm-svn: 42426
2007-09-28 01:19:48 +00:00
a1d46c7d0a
TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targets
...
other than PPC64. Instead of fixing it, just remove it and fix all the
places that use it to use TargetData::getPointerSize() instead, as there
aren't very many. Most of the references were in DwarfWriter.cpp.
llvm-svn: 42419
2007-09-27 23:12:31 +00:00
99dc695da5
Use GR64 in 64-bit mode.
...
llvm-svn: 42417
2007-09-27 21:50:05 +00:00
5a71402be6
Doh. Calls clobber EFLAGS.
...
llvm-svn: 42413
2007-09-27 19:01:55 +00:00
8728c3376a
- Added MRegisterInfo::getCrossCopyRegClass() hook. For register classes where reg to reg copies are not possible, this returns another register class which registers in the specified register class can be copied to (and copy back from).
...
- X86 copyRegToReg() now supports copying between EFLAGS and GR32 / GR64 registers.
llvm-svn: 42372
2007-09-26 21:31:07 +00:00
b93de587cb
Some assemblers do not recognize aliases pushfd, pushfq, popfd, and popfq. Just emit them as pushf and popf.
...
llvm-svn: 42371
2007-09-26 21:28:00 +00:00
b6d56401aa
Enable codegen for long double abs, sin, cos
...
llvm-svn: 42368
2007-09-26 21:10:55 +00:00
b4b352656a
Typos: POPQ -> POPFQ, POPD -> POPFD.
...
llvm-svn: 42348
2007-09-26 06:38:29 +00:00
c9e7b8ec50
move PR1160 here.
...
llvm-svn: 42347
2007-09-26 06:29:31 +00:00
c1e4e3743b
Allow copyRegToReg to emit cross register classes copies.
...
Tested with "make check"!
llvm-svn: 42346
2007-09-26 06:25:56 +00:00
fef69f5b4a
move PR1264 here.
...
llvm-svn: 42345
2007-09-26 06:15:48 +00:00
Chris Lattner