8904cc49db
Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset;
...
instead of the second operand in addrmode_imm12.
rdar://problem/9225289
llvm-svn: 128757
2011-04-02 02:24:54 +00:00
4111db6575
Undo changes mistakenly made in revision 128750.
...
llvm-svn: 128751
2011-04-02 00:26:12 +00:00
977f555a76
Insert space before ';' to prevent warnings.
...
llvm-svn: 128750
2011-04-02 00:15:58 +00:00
387b36eaae
Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
...
rdar://problem/9224276
llvm-svn: 128749
2011-04-01 23:30:25 +00:00
6615fa1de0
MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.
...
rdar://problem/9224120
llvm-svn: 128748
2011-04-01 23:15:50 +00:00
1e1010f56f
Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that
...
all the instruction have:
let Inst{31-27} = 0b1110; // non-predicated
Before, the ARM decoder was confusing:
> 0x40 0xf3 0xb8 0x80
as:
Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcs pc, r8, r0, asr #6
since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.
Now, the AR decoder behaves correctly:
> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt
Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcshi pc, r8, r0, asr #6
>
rdar://problem/9223094
llvm-svn: 128746
2011-04-01 22:32:51 +00:00
8b94c295c3
Fix comment.
...
llvm-svn: 128745
2011-04-01 22:29:18 +00:00
5cad45307e
Tweaks to the icmp+sext-to-shifts optimization to address Frits' comments:
...
- Localize the check if an icmp has one use to a place where we know we're
introducing something that's likely more expensive than a sext from i1.
- Add an assert to make sure a case that would lead to a miscompilation is
folded away earlier.
- Fix a typo.
llvm-svn: 128744
2011-04-01 22:22:11 +00:00
88530e6568
Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009
...
llvm-svn: 128743
2011-04-01 22:09:28 +00:00
3d9df607ba
Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed.
...
llvm-svn: 128742
2011-04-01 21:56:02 +00:00
56d9ef53a2
Simplifies logic for printing target flags.
...
llvm-svn: 128741
2011-04-01 21:41:06 +00:00
25ec0d38e1
CMake: remove debug code from previous commit.
...
llvm-svn: 128740
2011-04-01 21:39:38 +00:00
975ddf8035
When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately.
...
llvm-svn: 128739
2011-04-01 21:07:39 +00:00
360c369967
LDRD/STRD instructions should print both Rt and Rt2 in the asm string.
...
llvm-svn: 128736
2011-04-01 20:26:57 +00:00
5f74b39764
tlbgen/MC: StringRef's to temporary objects considered harmful.
...
llvm-svn: 128735
2011-04-01 20:23:52 +00:00
3dfb80afbf
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
...
as invalid.
llvm-svn: 128734
2011-04-01 20:21:38 +00:00
ac2d5657a6
Fix build.
...
llvm-svn: 128733
2011-04-01 20:15:16 +00:00
d121765e64
InstCombine: Turn icmp + sext into bitwise/integer ops when the input has only one unknown bit.
...
int test1(unsigned x) { return (x&8) ? 0 : -1; }
int test3(unsigned x) { return (x&8) ? -1 : 0; }
before (x86_64):
_test1:
andl $8, %edi
cmpl $1, %edi
sbbl %eax, %eax
ret
_test3:
andl $8, %edi
cmpl $1, %edi
sbbl %eax, %eax
notl %eax
ret
after:
_test1:
shrl $3, %edi
andl $1, %edi
leal -1(%rdi), %eax
ret
_test3:
shll $28, %edi
movl %edi, %eax
sarl $31, %eax
ret
llvm-svn: 128732
2011-04-01 20:09:10 +00:00
398b8c5faf
InstCombine: Move (sext icmp) transforms into their own method. No intended functionality change.
...
llvm-svn: 128731
2011-04-01 20:09:03 +00:00
8b1bca1998
Add comments.
...
llvm-svn: 128730
2011-04-01 19:57:01 +00:00
8d68ebd42a
Assign node order numbers to results of call instruction lowering. This should improve src line debug info when sdisel is used. rdar://9199118
...
llvm-svn: 128728
2011-04-01 19:42:22 +00:00
cde00a55c8
Fix assignment of -fPIC to CMAKE_C_FLAGS. Configure llvm-config.in.in
...
with the contents of CMAKE_C(XX)_FLAGS too, else `llvm-config
--c(xx)flags' doesn't tell the absolute truth.
This comes from PR9603 and is based on a patch by Ryuta Suzuki!
llvm-svn: 128727
2011-04-01 19:36:06 +00:00
e625ba46b7
Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly.
...
llvm-svn: 128724
2011-04-01 18:57:38 +00:00
fe6fba3fe6
Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
...
rdar://problem/9219356
llvm-svn: 128722
2011-04-01 18:26:38 +00:00
22430f4141
Update CMakeLists.txt
...
Patch by arrowdoger.
llvm-svn: 128719
2011-04-01 18:03:58 +00:00
93f898f643
Add code for analyzing FP branches. Clean up branch Analysis functions.
...
llvm-svn: 128718
2011-04-01 17:39:08 +00:00
bb21fac250
Initialize HasVMLxForwarding.
...
llvm-svn: 128709
2011-04-01 09:20:31 +00:00
e98f29df8b
Various Instructions' resizeOperands() methods are only used to grow the
...
list of operands. Simplify and rename them accordingly.
llvm-svn: 128708
2011-04-01 08:00:58 +00:00
a6a992a662
Add test case.
...
llvm-svn: 128707
2011-04-01 06:27:25 +00:00
0f86d6de50
FileCheck'ify test.
...
llvm-svn: 128706
2011-04-01 03:36:33 +00:00
2d3cdd686b
While testing dragonegg I noticed that isCastable and getCastOpcode
...
had gotten out of sync: isCastable didn't think it was possible to
cast the x86_mmx type to anything, while it did think it possible
to cast an i64 to x86_mmx.
llvm-svn: 128705
2011-04-01 03:34:54 +00:00
8a05f66139
Add annotations to tablegen-generated processor itineraries, or replace them with something meaningful. I want to be able to read and debug the generated tables.
...
llvm-svn: 128703
2011-04-01 02:22:47 +00:00
db6ed64529
whitespace
...
llvm-svn: 128701
2011-04-01 01:56:55 +00:00
bd76679700
Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.
...
rdar://8911343
llvm-svn: 128696
2011-04-01 00:42:02 +00:00
d911f92c46
Remove unused variables
...
llvm-svn: 128692
2011-04-01 00:06:01 +00:00
100f53fd25
Fix Thumb and Thumb2 tests to be register allocator independent.
...
llvm-svn: 128690
2011-03-31 23:31:50 +00:00
ab8305063b
Apply again changes to support ARM memory asm parsing. I removed
...
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
llvm-svn: 128689
2011-03-31 23:26:08 +00:00
6e597dc8e7
The basic register allocator must also use the inline spiller.
...
It is using a trivial rewriter that doesn't know how to insert spill code
requested by the standard spiller.
llvm-svn: 128688
2011-03-31 23:02:17 +00:00
0709342652
Provide a legal pointer register class when targeting thumb1.
...
The LocalStackSlotAllocation pass was creating illegal registers.
llvm-svn: 128687
2011-03-31 23:02:15 +00:00
903baeac27
Fix SystemZ tests
...
llvm-svn: 128686
2011-03-31 23:02:12 +00:00
d74b72b8a9
Instcombile optimization: extractelement(cast) -> cast(extractelement)
...
llvm-svn: 128683
2011-03-31 22:57:29 +00:00
0888bcf542
Fix ARM tests to be register allocator independent.
...
llvm-svn: 128680
2011-03-31 22:14:03 +00:00
5291054ef1
InstCombine: APFloat can't perform arithmetic on PPC double doubles, don't even try.
...
Thanks Eli!
llvm-svn: 128676
2011-03-31 21:35:49 +00:00
9cd9c4e5c9
Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which
...
amounts to an UNDEFINED instruction.
llvm-svn: 128668
2011-03-31 20:54:30 +00:00
38bf5adcea
Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
...
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2
llvm-svn: 128665
2011-03-31 19:38:48 +00:00
7b203f9cae
Fix single word and unsigned byte data transfer instruction encodings so that
...
Inst{4} = 0.
rdar://problem/9213022
llvm-svn: 128662
2011-03-31 19:28:35 +00:00
f4c9754d5c
Fix Mips, Sparc, and XCore tests that were dependent on register allocation.
...
Add an extra run with -regalloc=basic to keep them honest.
llvm-svn: 128654
2011-03-31 18:42:43 +00:00
a535270d91
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
...
llvm-svn: 128650
2011-03-31 18:26:17 +00:00
9feca67182
Pick better examples. "fpext float 3.1415 to double" won't parse because 3.1415
...
isn't an exact float. Also "fpext float 1.0 to float" is invalid IR because
it's not performing an extension.
llvm-svn: 128647
2011-03-31 18:20:19 +00:00
e6e6750670
Don't completely eliminate identity copies that also modify super register liveness.
...
Turn them into noop KILL instructions instead. This lets the scavenger know when
super-registers are killed and defined.
llvm-svn: 128645
2011-03-31 17:55:25 +00:00
13baa0e650
Add BLXi to the instruction table for disassembly purpose.
...
A8.6.23 BLX (immediate)
rdar://problem/9212921
llvm-svn: 128644
2011-03-31 17:53:50 +00:00
561cea0480
Allow kill flags on two-address instructions. They are harmless.
...
llvm-svn: 128643
2011-03-31 17:52:41 +00:00
9a78835414
Mark all uses as <undef> when joining a copy.
...
This way, shrinkToUses() will ignore the instruction that is about to be
deleted, and we avoid leaving invalid live ranges that SplitKit doesn't like.
Fix a misunderstanding in MachineVerifier about <def,undef> operands. The
<undef> flag is valid on def operands where it has the same meaning as <undef>
on a use operand. It only applies to sub-register defines which also read the
full register.
llvm-svn: 128642
2011-03-31 17:23:25 +00:00
22c5560bc8
Remove stray empty test file.
...
llvm-svn: 128640
2011-03-31 17:01:56 +00:00
e0cbe31ebb
Remove dead code.
...
llvm-svn: 128639
2011-03-31 16:53:49 +00:00
c2452a6f1d
Revert r128632 again, until I figure out what break the tests
...
llvm-svn: 128635
2011-03-31 15:54:36 +00:00
2ee5a0fc7f
Fix bug found by valgrind.
...
llvm-svn: 128634
2011-03-31 15:14:11 +00:00
9a827b30ab
Add XCore intrinsics for initializing / starting / synchronizing threads.
...
llvm-svn: 128633
2011-03-31 15:13:13 +00:00
4c0aebfb91
Reapply r128585 without generating a lib depedency cycle. An updated log:
...
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
addrmode2.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
llvm-svn: 128632
2011-03-31 14:52:28 +00:00
3df5c04fe4
Fix whitespace.
...
llvm-svn: 128631
2011-03-31 13:06:39 +00:00
c60223ef6c
Switch FileRemover from PathV1 to V2.
...
llvm-svn: 128630
2011-03-31 13:04:19 +00:00
41f32c7127
lib/CodeGen/LiveIntervalAnalysis.cpp: [PR9590] Don't use std::pow(float,float) here.
...
We don't expect the real "powf()" on some hosts (and powf() would be available on other hosts).
For consistency, std::pow(double,double) may be called instead.
Or, precision issue might attack us, to see unstable regalloc and stack coloring.
llvm-svn: 128629
2011-03-31 12:11:33 +00:00
be209ab8a2
InstCombine: Fix transform to use the swapped predicate.
...
Thanks Frits!
llvm-svn: 128628
2011-03-31 10:46:03 +00:00
d159d94644
InstCombine: fold fcmp (fneg x), (fneg y) -> fcmp x, y
...
llvm-svn: 128627
2011-03-31 10:12:22 +00:00
a8c5d0872d
InstCombine: fold fcmp pred (fneg x), C -> fcmp swap(pred) x, -C
...
llvm-svn: 128626
2011-03-31 10:12:15 +00:00
cbb18e91a8
InstCombine: Shrink "fcmp (fpext x), C" to "fcmp x, C" if C can be losslessly converted to the type of x.
...
Fixes PR9592.
llvm-svn: 128625
2011-03-31 10:12:07 +00:00
2ccfbc8b71
InstCombine: fold fcmp (fpext x), (fpext y) -> fcmp x, y.
...
llvm-svn: 128624
2011-03-31 10:11:58 +00:00
7c2b338a7e
Will not compile without the spec!
...
llvm-svn: 128623
2011-03-31 10:03:32 +00:00
6ae98633dd
Strip trailing whitespace.
...
llvm-svn: 128622
2011-03-31 09:58:51 +00:00
01cbbd8555
Testcase for r128619 (PR9571).
...
llvm-svn: 128620
2011-03-31 08:13:57 +00:00
ae044c06bf
Pick a conservative register class when creating a small live range for remat.
...
The rematerialized instruction may require a more constrained register class
than the register being spilled. In the test case, the spilled register has been
inflated to the DPR register class, but we are rematerializing a load of the
ssub_0 sub-register which only exists for DPR_VFP2 registers.
The register class is reinflated after spilling, so the conservative choice is
only temporary.
llvm-svn: 128610
2011-03-31 03:54:44 +00:00
73906b05ca
Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"
...
This revision introduced a dependency cycle, as nlewycky mentioned by email.
llvm-svn: 128597
2011-03-31 00:39:16 +00:00
41198698aa
Fix typo in generated HTML.
...
llvm-svn: 128594
2011-03-31 00:23:57 +00:00
271efda884
Use intrinsics for Neon vmull operations. Radar 9208957.
...
llvm-svn: 128591
2011-03-31 00:09:35 +00:00
abda3caf67
Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler.
...
llvm-svn: 128587
2011-03-30 23:45:29 +00:00
ee9d45dd55
Don't try to create zero-sized stack objects.
...
llvm-svn: 128586
2011-03-30 23:44:13 +00:00
280264b889
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
...
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser
llvm-svn: 128585
2011-03-30 23:32:32 +00:00
53dd03d537
Add a ARM-specific SD node for VBSL so that forms with a constant first operand
...
can be recognized. This fixes <rdar://problem/9183078>.
llvm-svn: 128584
2011-03-30 23:01:21 +00:00
11ab9ca1cd
Tidy up. Whitespace and 80-columns.
...
llvm-svn: 128583
2011-03-30 22:38:13 +00:00
5034159c5f
* The DSE code that tested for overlapping needed to take into account the fact
...
that one of the numbers is signed while the other is unsigned. This could lead
to a wrong result when the signed was promoted to an unsigned int.
* Add the data layout line to the testcase so that it will test the appropriate
thing.
Patch by David Terei!
llvm-svn: 128577
2011-03-30 21:37:19 +00:00
4e9ca1b3ba
fixed typo
...
llvm-svn: 128574
2011-03-30 21:15:35 +00:00
aab97dce6a
Don't add the same analysis implementation pair twice.
...
Prevent infinite growth of the list.
Patch by José Fonseca!
llvm-svn: 128568
2011-03-30 18:32:53 +00:00
846f95080c
Reset StringMap's NumTombstones on clears and rehashes.
...
StringMap was not properly updating NumTombstones after a clear or rehash.
This was not fatal until now because the table was growing faster than
NumTombstones could, but with the previous change of preventing infinite
growth of the table the invariant (NumItems + NumTombstones <= NumBuckets)
stopped being observed, causing infinite loops in certain situations.
Patch by José Fonseca!
llvm-svn: 128567
2011-03-30 18:32:51 +00:00
bdc1b01217
Prevent infinite growth of SmallPtrSet instances.
...
Rehash but don't grow when full of tombstones.
Patch by José Fonseca!
llvm-svn: 128566
2011-03-30 18:32:48 +00:00
f587f4419c
Prevent infinite growth of SmallMap instances.
...
Rehash but don't grow when full of tombstones.
Patch by José Fonseca!
llvm-svn: 128565
2011-03-30 18:32:44 +00:00
5ca05e1801
Prevent infinite growth of the DenseMap.
...
When the hash function uses object pointers all free entries eventually
become tombstones as they are used at least once, regardless of the size.
DenseMap cannot function with zero empty keys, so it double size to get
get ridof the tombstones.
However DenseMap never shrinks automatically unless it is cleared, so
the net result is that certain tables grow infinitely.
The solution is to make a fresh copy of the table without tombstones
instead of doubling size, by simply calling grow with the current size.
Patch by José Fonseca!
llvm-svn: 128564
2011-03-30 18:32:41 +00:00
ae917a3740
Fix evil VirtRegRewriter bug.
...
The rewriter can keep track of multiple stack slots in the same register if they
happen to have the same value. When an instruction modifies a stack slot by
defining a register that is mapped to a stack slot, other stack slots in that
register are no longer valid.
This is a very rare problem, and I don't have a simple test case. I get the
impression that VirtRegRewriter knows it is about to be deleted, inventing a
last opaque problem.
<rdar://problem/9204040>
llvm-svn: 128562
2011-03-30 18:14:07 +00:00
69129256dd
Teach VirtRegRewriter about the new virtual register numbers. No functional change.
...
llvm-svn: 128561
2011-03-30 18:14:04 +00:00
af0ed953c5
Avoid turning a floating point division with a constant power of two into a denormal multiplication.
...
Some platforms may treat denormals as zero, on other platforms multiplication
with a subnormal is slower than dividing by a normal.
llvm-svn: 128555
2011-03-30 17:02:54 +00:00
8564e0de96
InstCombine: If the divisor of an fdiv has an exact inverse, turn it into an fmul.
...
Fixes PR9587.
llvm-svn: 128546
2011-03-30 15:42:35 +00:00
03fd672609
Add APFloat::getExactInverse.
...
The idea is, that if an ieee 754 float is divided by a power of two, we can
turn the division into a cheaper multiplication. This function sees if we can
get an exact multiplicative inverse for a divisor and returns it if possible.
This is the hard part of PR9587.
I tested many inputs against llvm-gcc's frotend implementation of this
optimization and didn't find any difference. However, floating point is the
land of weird edge cases, so any review would be appreciated.
llvm-svn: 128545
2011-03-30 15:42:27 +00:00
36bc3aec2d
Fix more zero length memset warnings.
...
llvm-svn: 128543
2011-03-30 15:31:02 +00:00
83507db904
Add a comment on PHINode::Create().
...
llvm-svn: 128540
2011-03-30 13:29:06 +00:00
52131344a2
Remove PHINode::reserveOperandSpace(). Instead, add a parameter to
...
PHINode::Create() giving the (known or expected) number of operands.
llvm-svn: 128537
2011-03-30 11:28:46 +00:00
e0938d8a87
(Almost) always call reserveOperandSpace() on newly created PHINodes.
...
llvm-svn: 128535
2011-03-30 11:19:20 +00:00
4b7c20587d
Revert a minor comment change inadvertently included with r128502.
...
llvm-svn: 128526
2011-03-30 05:26:51 +00:00
dd9a2ecef7
Treat clones the same as their origin.
...
When DCE clones a live range because it separates into connected components,
make sure that the clones enter the same register allocator stage as the
register they were cloned from.
For instance, clones may be split even when they where created during spilling.
Other registers created during spilling are not candidates for splitting or even
(re-)spilling.
llvm-svn: 128524
2011-03-30 02:52:39 +00:00
c73eda1e89
Remove dead code.
...
llvm-svn: 128519
2011-03-30 01:03:48 +00:00
0ae2501fd2
Add a test case for thumb stc2 instruction.
...
llvm-svn: 128517
2011-03-30 01:02:06 +00:00
bcc3388252
ClangSAEmClangSACheckersEmitter, emit info about groups.
...
llvm-svn: 128515
2011-03-30 00:22:00 +00:00
46a2b5b3b7
Set the unnamed_addr only when we're creating a new GV in the dest module.
...
llvm-svn: 128507
2011-03-29 23:31:06 +00:00
cfb2036689
Revert r128501. It caused test failures.
...
llvm-svn: 128506
2011-03-29 23:28:02 +00:00
1900c73a97
Tidy up. 80 columns and trailing whitespace.
...
llvm-svn: 128504
2011-03-29 23:20:22 +00:00
c68476480e
Update CMake link dependency.
...
llvm-svn: 128503
2011-03-29 23:18:51 +00:00
18381b4257
Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. Frontends
...
was lowering them to sext / uxt + mul instructions. Unfortunately the
optimization passes may hoist the extensions out of the loop and separate them.
When that happens, the long multiplication instructions can be broken into
several scalar instructions, causing significant performance issue.
Note the vmla and vmls intrinsics are not added back. Frontend will codegen them
as intrinsics vmull* + add / sub. Also note the isel optimizations for catching
mul + sext / zext are not changed either.
First part of rdar://8832507, rdar://9203134
llvm-svn: 128502
2011-03-29 23:06:19 +00:00
985bef24d1
We need to copy over the unnamed_addr attribute.
...
llvm-svn: 128501
2011-03-29 23:05:41 +00:00
ee6231ce6b
Revert accidental change to LLVMLibDeps.cmake
...
llvm-svn: 128499
2011-03-29 22:42:41 +00:00
bceec7f9a8
Quiet a gcc warning about changed name lookup rules
...
llvm-svn: 128497
2011-03-29 22:25:36 +00:00
272f2b0044
InstCombine: Add a few missing combines for ANDs and ORs of sign bit tests.
...
On x86 we now compile "if (a < 0 && b < 0)" into
testl %edi, %esi
js IF.THEN
llvm-svn: 128496
2011-03-29 22:06:41 +00:00
df4935cc90
Adding a test for "-inf" as well.
...
llvm-svn: 128495
2011-03-29 21:54:10 +00:00
a0f0b5d9f0
Add a test case for MSRi.
...
llvm-svn: 128494
2011-03-29 21:52:02 +00:00
143f9aea2b
Add Neon SINT_TO_FP and UINT_TO_FP lowering from v4i16 to v4f32. Fixes
...
<rdar://problem/8875309> and <rdar://problem/9057191>.
llvm-svn: 128492
2011-03-29 21:41:55 +00:00
e991f728d6
Recompute register class and hint for registers created during spilling.
...
The spill weight is not recomputed for an unspillable register - it stays infinite.
llvm-svn: 128490
2011-03-29 21:20:19 +00:00
42d0a6c770
In ClangSACheckersEmitter:
...
- Also emit a list of packages and groups sorted by name
- Avoid iterating over DenseSet so that the output of the arrays is deterministic.
llvm-svn: 128489
2011-03-29 21:16:19 +00:00
5bbe957155
Added support symbolic floating point constants in the MC assembler for Infinity
...
and Nans with the same strings as GAS supports. rdar://8673024
llvm-svn: 128488
2011-03-29 21:11:52 +00:00
dcb29ae8ee
Add a thumb test file for printf (iOS 4.3).
...
llvm-svn: 128487
2011-03-29 21:09:30 +00:00
6cfbcc8954
Instantiate a JITMemoryManager for MCJIT Dyld
...
llvm-svn: 128485
2011-03-29 21:03:05 +00:00
978e5284fa
Fixed the build of Clang's unit tests on MinGW. Also removed some
...
unnecesary conditionals and introduced a new convenience function.
The problem was that the list of libraries for Clang's unit tests was
<clang libraries> <system libraries> <llvm libraries>. As the llvm
libraries references symbols defined on the system libraries, those
were reported as undefined.
llvm-svn: 128484
2011-03-29 20:51:08 +00:00
e41395ac24
DSE: Remove an early exit optimization that depended on the ordering of a SmallPtrSet.
...
Fixes PR9569 and will hopefully make selfhost on ASLR-enabled systems more deterministic.
llvm-svn: 128482
2011-03-29 20:28:57 +00:00
7ac53ad643
Check early if this is an unsupported opcode, so that we can avoid needlessly instantiating the base register in some cases.
...
llvm-svn: 128481
2011-03-29 20:27:38 +00:00
4bc2baeb28
A8.6.188 STC, STC2
...
The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.
rdar://problem/9200661
llvm-svn: 128478
2011-03-29 19:49:38 +00:00
7927569f05
Rename invalid-VLDMSDB-arm.txt to be invalid-VLDMSDB_UPD-arm.txt.
...
llvm-svn: 128477
2011-03-29 19:10:06 +00:00
ec6f76ed38
Add and modify some tests.
...
llvm-svn: 128476
2011-03-29 19:08:52 +00:00
2de9d572e8
For ClangSACheckersEmitter, allow a package to belong to checker group, in which all its checkers will go into the group.
...
llvm-svn: 128474
2011-03-29 18:53:00 +00:00
0ed9ebca58
Remember to use the correct register when rematerializing for snippets.
...
llvm-svn: 128469
2011-03-29 17:47:02 +00:00
add79c6abf
Run dead code elimination immediately after rematerialization.
...
This may eliminate some uses of the spilled registers, and we don't want to
insert reloads for that.
llvm-svn: 128468
2011-03-29 17:47:00 +00:00
c48981f729
Add safety check that didn't show up in testing.
...
llvm-svn: 128467
2011-03-29 17:42:25 +00:00
1c6b681413
Document llvm.dbg.sp, llvm.dbg.gv and llvm.dbg.enum
...
llvm-svn: 128466
2011-03-29 17:27:08 +00:00
dd1cf3279e
Inline check that's used only once.
...
llvm-svn: 128465
2011-03-29 17:12:55 +00:00
d6c5a741b5
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
...
llvm-svn: 128461
2011-03-29 16:45:53 +00:00
fb63d55fe8
Rework the logic (and removing the bad check for an unreachable block) so that
...
the FailBB dominator is correctly calculated. Believe it or not, there isn't a
functionality change here.
llvm-svn: 128455
2011-03-29 07:28:52 +00:00
ff811cc475
Do some simple copy propagation through integer loads and stores when promoting
...
vector types. This helps a lot with inlined functions when using the ARM soft
float ABI. Fixes <rdar://problem/9184212>.
llvm-svn: 128453
2011-03-29 05:19:52 +00:00
220c9f045b
Don't try to add stack protector logic to a dead basic block. It messes up
...
dominator information.
llvm-svn: 128452
2011-03-29 05:15:48 +00:00
225d9b15b5
Spruce up the error output.
...
llvm-svn: 128451
2011-03-29 04:28:26 +00:00
12877b8a15
Handle the special case when all uses follow the last split point.
...
llvm-svn: 128450
2011-03-29 03:12:04 +00:00
d8af5298d1
Properly enable rematerialization when spilling after live range splitting.
...
The instruction to be rematerialized may not be the one defining the register
that is being spilled. The traceSiblingValue() function sees through sibling
copies to find the remat candidate.
llvm-svn: 128449
2011-03-29 03:12:02 +00:00
30d0bdd1df
C-API: Include DataTypes.h instead of stdint.h.
...
llvm-svn: 128446
2011-03-29 02:30:34 +00:00
6b2fac21ca
Reduce test case.
...
llvm-svn: 128445
2011-03-29 02:18:54 +00:00
e2086e740f
Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
...
isel lowering to fold the zero-extend's and take advantage of no-stall
back to back vmul + vmla:
vmull q0, d4, d6
vmlal q0, d5, d6
is faster than
vaddl q0, d4, d5
vmovl q1, d6
vmul q0, q0, q1
This allows us to vmull + vmlal for:
f = vmull_u8( vget_high_u8(s), c);
f = vmlal_u8(f, vget_low_u8(s), c);
rdar://9197392
llvm-svn: 128444
2011-03-29 01:56:09 +00:00
3cf622a832
Fix the MSVC build.
...
llvm-svn: 128441
2011-03-29 00:30:01 +00:00
4a2737aa26
Expoert c interface for disassembler.
...
llvm-svn: 128440
2011-03-29 00:01:39 +00:00
96f962fdff
In some cases, the "fail BB dominator" may be null after the BB was split (and
...
becomes reachable when before it wasn't). Check to make sure that it's not null
before trying to use it.
llvm-svn: 128434
2011-03-28 23:02:18 +00:00
3e2b335903
Integrated-As: Add support for setting the AllowTemporaryLabels flag via
...
integrated-as.
llvm-svn: 128431
2011-03-28 22:49:19 +00:00
4ee0d03274
MC: Add support for disabling "temporary label" behavior. Useful for debugging
...
on Darwin.
llvm-svn: 128430
2011-03-28 22:49:15 +00:00
2d45693446
Unbreak CMake build.
...
llvm-svn: 128426
2011-03-28 20:43:53 +00:00
94d1979a95
Remove scripts used by TEST=dbg from here. They now live inside llvm test suite.
...
llvm-svn: 128425
2011-03-28 20:28:30 +00:00
f9cd139369
Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases.
...
Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.
llvm-svn: 128417
2011-03-28 18:41:58 +00:00
f3070dc40d
Again adding a C API to the disassembler for use by such tools as Darwin's
...
otool(1), this time with the needed fix for case sensitive file systems :) .
This is a work in progress as the interface for producing symbolic operands is
not done. But a hacked prototype using information from the object file's
relocation entiries and replacing immediate operands with MCExpr's has been
shown to work with no changes to the instrucion printer. These APIs will be
moved into a dynamic library at some point.
llvm-svn: 128415
2011-03-28 18:25:07 +00:00
ebc2f3a68c
Remove tabs I accidentally added.
...
llvm-svn: 128413
2011-03-28 17:48:26 +00:00
1c83965f5a
Make more use of PHINode::getNumIncomingValues().
...
llvm-svn: 128406
2011-03-28 13:03:10 +00:00
cdedaf1f7d
ptx: clean up branch code a bit
...
llvm-svn: 128405
2011-03-28 10:23:13 +00:00
10b96cb34b
docs/GettingStarted.html: [PR8850] Add a note for x86_64-w64-mingw32.
...
llvm-svn: 128404
2011-03-28 06:27:12 +00:00
05c00021da
docs/GettingStarted.html: Add blurb "--enable-shared" on cygming.
...
llvm-svn: 128403
2011-03-28 06:27:06 +00:00
d14d991bf7
Add some debug output when -instcombine uses RAUW. This can make debug output for those cases much clearer since without this it only showed that the original instruction was removed, not what it was replaced with.
...
llvm-svn: 128399
2011-03-27 23:32:31 +00:00
bd6b86e489
Amend debug output.
...
llvm-svn: 128398
2011-03-27 22:49:23 +00:00
28d79cdeab
Drop interference reassignment in favor of eviction.
...
The reassignment phase was able to move interference with a higher spill weight,
but it didn't happen very often and it was fairly expensive.
The existing interference eviction picks up the slack.
llvm-svn: 128397
2011-03-27 22:49:21 +00:00
8544228d5a
Teach the transformation that moves binary operators around selects to preserve
...
the subclass optional data.
llvm-svn: 128388
2011-03-27 19:51:23 +00:00
1f90da127f
Use APInt's umul_ov instead of rolling our own overflow detection.
...
llvm-svn: 128380
2011-03-27 15:04:38 +00:00
0bb2ad2cf7
Constant folding support for calls to umul.with.overflow(), basically identical to the smul.with.overflow() code.
...
llvm-svn: 128379
2011-03-27 14:26:13 +00:00
d5f631cd2a
Partially revert commit 127155: I think it is much more convenient
...
to have structured log files rather than one big file produced by
piping output.
llvm-svn: 128378
2011-03-27 13:52:32 +00:00
83167df787
Add a small missed optimization: turn X == C ? X : Y into X == C ? C : Y. This
...
removes one use of X which helps it pass the many hasOneUse() checks.
In my analysis, this turns up very often where X = A >>exact B and that can't be
simplified unless X has one use (except by increasing the lifetime of A which is
generally a performance loss).
llvm-svn: 128373
2011-03-27 07:30:57 +00:00
af66980d8a
Fix whitespace.
...
llvm-svn: 128370
2011-03-27 01:44:40 +00:00
e466345675
Use individual register classes when spilling snippets.
...
The main register class may have been inflated by live range splitting, so that
register class is not necessarily valid for the snippet instructions.
Use the original register class for the stack slot interval.
llvm-svn: 128351
2011-03-26 22:16:41 +00:00
355ce07425
Turn SelectionDAGBuilder::GetRegistersForValue into a local function.
...
It couldn't be used outside of the file because SDISelAsmOperandInfo
is local to SelectionDAGBuilder.cpp. Making it a static function avoids
a weird linkage dance.
llvm-svn: 128342
2011-03-26 16:35:10 +00:00
8d2227373d
Make helper static.
...
llvm-svn: 128338
2011-03-26 12:38:19 +00:00
b5139920d6
Simplification noticed by Frits.
...
llvm-svn: 128333
2011-03-26 09:32:07 +00:00
19f33b9393
Rework the logic that determines if a store completely overlaps an ealier store.
...
There are two ways that a later store can comletely overlap a previous store:
1. They both start at the same offset, but the earlier store's size is <= the
later's size, or
2. The earlier store's offset is > the later's offset, but it's offset + size
doesn't extend past the later's offset + size.
llvm-svn: 128332
2011-03-26 08:02:59 +00:00
d4174ee43e
Fix a typo and add a test.
...
llvm-svn: 128331
2011-03-26 04:58:50 +00:00
fa38bd3dfe
Extend Clang's TableGen emitter for attributes to support bool arguments.
...
llvm-svn: 128330
2011-03-26 03:40:01 +00:00
9a624fa993
Collect and coalesce DBG_VALUE instructions before emitting the function.
...
Correctly terminate the range of register DBG_VALUEs when the register is
clobbered or when the basic block ends.
The code is now ready to deal with variables that are sometimes in a register
and sometimes on the stack. We just need to teach emitDebugLoc to say 'stack
slot'.
llvm-svn: 128327
2011-03-26 02:19:36 +00:00
923f3dac01
Fixed the t2PLD and friends disassembly and add two test cases.
...
llvm-svn: 128322
2011-03-26 01:32:48 +00:00
d553096688
Fix the bfi handling for or (and a mask) (and b mask). We need the two
...
masks to match inversely for the code as is to work. For the example given
we actually want:
bfi r0, r2, #1 , #1
not #0 , however, given the way the pattern is written it's not possible
at the moment.
Fixes rdar://9177502
llvm-svn: 128320
2011-03-26 01:21:03 +00:00
db40b5c899
PR9561: A store with a negative offset (via GEP) could erroniously say that it
...
completely overlaps a previous store, thus mistakenly deleting that store. Check
for this condition.
llvm-svn: 128319
2011-03-26 01:20:37 +00:00
d077a857cc
Remove the files for r128308 as it is causing a buildbot failure.
...
llvm-svn: 128309
2011-03-26 00:23:05 +00:00
c8b4078654
Adding a C API to the disassembler for use by such tools as Darwin's otool(1).
...
This is a work in progress as the interface for producing symbolic operands is
not done. But a hacked prototype using information from the object file's
relocation entiries and replacing immediate operands with MCExpr's has been
shown to work with no changes to the instrucion printer. These APIs will be
moved into a dynamic library at some point.
llvm-svn: 128308
2011-03-26 00:06:33 +00:00
1572bf40b4
Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt.
...
llvm-svn: 128306
2011-03-25 23:02:58 +00:00
6e31bf1f6f
Add two test cases t2SMLABT and t2SMMULR for DisassembleThumb2Mul().
...
llvm-svn: 128305
2011-03-25 22:43:28 +00:00
49316e40ba
Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID.
...
Also add some test cases.
rdar://problem/9189829
llvm-svn: 128304
2011-03-25 22:19:07 +00:00
aaf2c69400
DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases.
...
rdar://problem/9182892
llvm-svn: 128299
2011-03-25 19:35:37 +00:00
4fd2194638
A8.6.226 TBB, TBH:
...
Add two test cases.
llvm-svn: 128295
2011-03-25 18:40:21 +00:00
b35548f44d
Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to
...
t2LDREX/t2STREX instructions. Add two test cases.
llvm-svn: 128293
2011-03-25 18:29:49 +00:00
6f4c9425eb
MC: Improve some diagnostics on uses of '.' pseudo-symbol.
...
llvm-svn: 128289
2011-03-25 17:47:17 +00:00
3f56104be1
Tidyness.
...
llvm-svn: 128288
2011-03-25 17:47:14 +00:00
dc0082b087
Add a note.
...
llvm-svn: 128286
2011-03-25 17:32:40 +00:00
aa84d41dfc
Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that.
...
rdar://problem/9184053
llvm-svn: 128285
2011-03-25 17:31:16 +00:00
1886a4c823
Emit less labels for debug info and stop emitting .loc directives for DBG_VALUEs.
...
The .dot directives don't need labels, that is a leftover from when we created
line number info manually.
Instructions following a DBG_VALUE can share its label since the DBG_VALUE
doesn't produce any code.
llvm-svn: 128284
2011-03-25 17:20:59 +00:00
757ca69770
Also need to handle invalid imod values for CPS2p.
...
rdar://problem/9186136
llvm-svn: 128283
2011-03-25 17:03:12 +00:00
5343a406f8
Useful script for finding regressions in the nightly testsuite.
...
I think it was written by Pawel Worach.
llvm-svn: 128268
2011-03-25 07:17:44 +00:00
ce2fccffc2
Remove redundant compression option.
...
llvm-svn: 128267
2011-03-25 06:43:59 +00:00
3bd8b7a388
Fix for -pre-RA-sched=source.
...
Yet another case of unchecked NULL node (for physreg copy).
May fix PR9509.
llvm-svn: 128266
2011-03-25 06:40:55 +00:00
0e25c8b364
No functionality change, just adjust some whitespace for coding style compliance.
...
llvm-svn: 128257
2011-03-25 06:05:50 +00:00
d73218e4a3
No functionality change. Fix up some whitespace and switch out "" for '' when
...
printing a single character.
llvm-svn: 128256
2011-03-25 06:04:26 +00:00
a1e3156ebd
Ignore special ARM allocation hints for unexpected register classes.
...
Add an assertion to linear scan to prevent it from allocating registers outside
the register class.
<rdar://problem/9183021>
llvm-svn: 128254
2011-03-25 01:48:18 +00:00
a52143bff3
Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed),
...
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.
llvm-svn: 128252
2011-03-25 01:09:48 +00:00
72f4a95144
delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that.
...
llvm-svn: 128249
2011-03-25 00:17:42 +00:00
ceef55466a
The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since
...
the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add
test cases for that.
llvm-svn: 128247
2011-03-24 23:42:31 +00:00
73193f2475
The ARM disassembler was confused with the 16-bit tSTMIA instruction.
...
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.
llvm-svn: 128246
2011-03-24 23:21:14 +00:00
71536de752
Move test in x86 specific area.
...
llvm-svn: 128245
2011-03-24 22:39:09 +00:00
303e3161bb
Suppress an unused variable warning in -asserts builds
...
llvm-svn: 128244
2011-03-24 22:05:48 +00:00
9302df0ad9
Handle the added VBICiv*i* NEON instructions, too.
...
llvm-svn: 128243
2011-03-24 22:04:39 +00:00
3a213a50fe
Testcase for llvm-gcc commit r128230.
...
llvm-svn: 128242
2011-03-24 21:59:03 +00:00
02e59ad506
Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!
...
llvm-svn: 128241
2011-03-24 21:42:55 +00:00
6469ca0c33
T2 Load/Store Multiple:
...
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add a test case.
llvm-svn: 128240
2011-03-24 21:36:56 +00:00
dd9eb21c3f
Plug a leak in the arm disassembler and put the tests back.
...
llvm-svn: 128238
2011-03-24 21:14:28 +00:00
f170f8bff6
Add asm parsing support w/ testcases for strex/ldrex family of instructions
...
llvm-svn: 128236
2011-03-24 21:04:58 +00:00
471f5aa233
Remove these two test files as they cause llvm-i686-linux-vg_leak build to fail 'test-llvm'.
...
These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble.
llvm-svn: 128235
2011-03-24 20:56:23 +00:00
8bbc12824a
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
...
Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.
llvm-svn: 128234
2011-03-24 20:42:48 +00:00
e01b75cb89
Keep track of directory namd and fIx regression caused by Rafael's patch r119613.
...
A better approach would be to move source id handling inside MC.
llvm-svn: 128233
2011-03-24 20:30:50 +00:00
a3df87fb01
Clean up assembly statement separator support.
...
The MC asm lexer wasn't honoring a non-default (anything but ';') statement
separator. Fix that, and generalize a bit to support multi-character
statement separators.
llvm-svn: 128227
2011-03-24 18:46:34 +00:00
c5207f7167
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the
...
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case.
llvm-svn: 128226
2011-03-24 18:40:38 +00:00
1dd041083d
Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,
...
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.
llvm-svn: 128220
2011-03-24 17:04:22 +00:00
a4ec5b2c19
revert r128199 until it can be made to work with Frontend/dependency-gen.c.
...
llvm-svn: 128218
2011-03-24 16:43:37 +00:00
74157ab3e5
Debug intrinsics must be skipped at the beginning and ends of blocks, lest they
...
affect the generated code.
llvm-svn: 128217
2011-03-24 16:34:59 +00:00
b03bd5983d
Fix typo in comment.
...
llvm-svn: 128216
2011-03-24 16:18:19 +00:00
669ce55a42
fix description, PR9542
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llvm-svn: 128214
2011-03-24 16:13:31 +00:00
2edfe778ec
It is enough for the CallInst to have no uses to be made a tail call with a ret
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void; it doesn't need to have a void type.
llvm-svn: 128212
2011-03-24 15:54:11 +00:00
8f606d7b9b
s/UpdateDT/ModifiedDT/g
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llvm-svn: 128211
2011-03-24 15:35:25 +00:00
521eb7c11e
Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets.
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FIXME: Some cleanups would be needed.
llvm-svn: 128206
2011-03-24 07:07:00 +00:00
3854bad4a1
llvm-stub.cpp: mingw-w64 tweak.
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llvm-svn: 128205
2011-03-24 07:06:45 +00:00
e8954f1ee1
Add comment to clarify what MachineConstantPoolEntry::isMachineConstantPoolEntry() means.
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llvm-svn: 128204
2011-03-24 06:28:45 +00:00
f098bf1199
Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry
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entries being compared may not be ARMConstantPoolValue. Without checking
whether they are ARMConstantPoolValue first, and if the stars and moons
are aligned properly, the equality test may return true (when the first few
words of two Constants' values happen to be identical) and very bad things can
happen.
rdar://9125354
llvm-svn: 128203
2011-03-24 06:20:03 +00:00
e42162ad59
Remove all uses of PATH_MAX and MAXPATHLEN from PathV2.
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llvm-svn: 128199
2011-03-24 05:23:40 +00:00
4649f17db1
Do early taildup of ret in CodeGenPrepare for potential tail calls that have a
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void return type. This fixes PR9487.
llvm-svn: 128197
2011-03-24 04:52:10 +00:00
0e331c05ae
Use an early return instead of a long if block.
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llvm-svn: 128196
2011-03-24 04:52:07 +00:00
dd84bcce8f
When UpdateDT is set, DT is invalid, which could cause problems when trying to
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use it later. I couldn't make a test that hits this with the current code.
llvm-svn: 128195
2011-03-24 04:52:04 +00:00
47e7175fe9
Check for TLI so that -codegenprepare can be used from opt.
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llvm-svn: 128194
2011-03-24 04:51:51 +00:00
a75d158c41
CPS3p: Let's reject impossible imod values by returning false from the DisassembleMiscFrm() function.
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Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing)
Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
Before:
cpsUnknown imod operand
UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123!
After:
/Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding
0x93 0x1c 0x2 0xf1
^
llvm-svn: 128192
2011-03-24 02:24:36 +00:00
0f5d52d658
Load/Store Multiple:
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These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add two test cases.
llvm-svn: 128191
2011-03-24 01:40:42 +00:00
1de8cc6f95
STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
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We now tag them as IndexModePost.
llvm-svn: 128189
2011-03-24 01:07:26 +00:00
f949d8e13d
The r128103 fix to cope with the removal of addressing modes from the MC instructions
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were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.
llvm-svn: 128186
2011-03-24 00:28:38 +00:00
67d3d915cc
Runtime dylib simple ARM 24-bit branch relocation support.
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llvm-svn: 128184
2011-03-23 23:35:17 +00:00
abc77347a7
Enable GlobalMerge on darwin.
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llvm-svn: 128183
2011-03-23 23:34:19 +00:00
c7ca640529
Fix comments.
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llvm-svn: 128182
2011-03-23 23:32:48 +00:00
4ab9a16569
Revert r128175.
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I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix.
llvm-svn: 128181
2011-03-23 23:11:02 +00:00
425489d397
Cmp peephole optimization isn't always safe for signed arithmetics.
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int tries = INT_MAX;
while (tries > 0) {
tries--;
}
The check should be:
subs r4, #1
cmp r4, #0
bgt LBB0_1
The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop
canonicalization apparently does in this case). cmp #0 would have cleared
it while not changing the N and Z bits. Since BGT is dependent on the V
bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0 .
rdar://9172742
llvm-svn: 128179
2011-03-23 22:52:04 +00:00
4c192305bf
PR9535: add support for splitting and scalarizing vector ISD::FP_ROUND.
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Also cleaning up some duplicated code while I'm here.
llvm-svn: 128176
2011-03-23 22:18:48 +00:00
4046a0de91
Reapply Eli's r127852 now that the pre-RA scheduler can spill EFLAGS.
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(target-specific branchless method for double-width relational comparisons on x86)
llvm-svn: 128175
2011-03-23 22:16:02 +00:00
c80099aa04
Split out relocation resolution into target-specific bits.
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llvm-svn: 128173
2011-03-23 22:06:06 +00:00
8543d4f8a1
The high bit of a Thumb2 ADR's offset is stored in bit 26, not bit 25.
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This fixes 464.h264ref with the integrated assembler.
llvm-svn: 128172
2011-03-23 22:03:44 +00:00
98775c4358
Fix double-free of Module.
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The ExecutionEngine constructor already added the module, so there's no
need to call addModule() directly. Doing so causes a double-free of the
Module at program termination.
llvm-svn: 128171
2011-03-23 21:35:02 +00:00
ab234158b8
Fix a bug introduced by my patch yesterday: BL is a 4-byte instructions like BLX, rather than a 2-byte instruction like B.
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llvm-svn: 128169
2011-03-23 21:19:56 +00:00
13acae040c
Ensure that def-side physreg copies are scheduled above any other uses
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so the scheduler can't create new interferences on the copies
themselves. Prior to this fix the scheduler could get stuck in a loop
creating copies.
Fixes PR9509.
llvm-svn: 128164
2011-03-23 20:42:39 +00:00
a8846e0540
whitespace
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llvm-svn: 128163
2011-03-23 20:40:18 +00:00
6a85a05130
Start of relocation resolution for the runtime dyld library.
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llvm-svn: 128161
2011-03-23 19:52:00 +00:00
c114d89ea2
Make sure to report any errors from the runtime dyld.
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llvm-svn: 128160
2011-03-23 19:51:34 +00:00
a87d80cdca
Don't coalesce identical DBG_VALUE instructions prematurely.
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Each of these instructions may have a RegsClobberInsn entry that can't be
ignored. Consecutive ranges are coalesced later when DwarfDebug::emitDebugLoc
merges entries.
llvm-svn: 128155
2011-03-23 18:37:30 +00:00
465f93645f
Supports building with a list of targets that does not contain
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X86. Fixes PR9533.
llvm-svn: 128154
2011-03-23 17:42:13 +00:00
06c8a38223
PTX: Improve support for 64-bit addressing
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- Fix bug in ADDRrr/ADDRri/ADDRii selection for 64-bit addresses
- Add comparison selection for i64
- Add zext selection for i32 -> i64
- Add shl/shr/sha support for i64
llvm-svn: 128153
2011-03-23 16:58:51 +00:00
c4f0ab397c
Revert r128140 for now.
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llvm-svn: 128149
2011-03-23 15:51:12 +00:00
10ebc189ee
Fix PR9464 by correcting some math that just happened to be right in most cases
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that were hit in practice.
llvm-svn: 128146
2011-03-23 05:25:55 +00:00
Johnny Chen