bd10af96bd
Add a function for profiling to run at shutdown. Unlike the existing API, this
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can be used even when main() isn't present in the Module, but it means that you
don't get to read argv[].
llvm-svn: 129163
2011-04-08 22:19:52 +00:00
4e1796e8d1
Fix an apparent typo that made GCC complain
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llvm-svn: 129160
2011-04-08 21:59:49 +00:00
e39647951b
Do not emit DW_AT_upper_bound and DW_AT_lower_bound for unbouded array.
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If lower bound is more then upper bound then consider it is an unbounded array.
An array is unbounded if non-zero lower bound is same as upper bound.
If lower bound and upper bound are zero than array has one element.
llvm-svn: 129156
2011-04-08 21:55:10 +00:00
c5d44ae3f4
Missing closed tag.
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llvm-svn: 129155
2011-04-08 21:43:08 +00:00
74d92c1924
Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time.
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llvm-svn: 129152
2011-04-08 21:37:21 +00:00
ecd7043883
Workaround g++ 4.2.1 warning diagnostic false positive.
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llvm-svn: 129149
2011-04-08 21:11:20 +00:00
f2faf4e53a
Check opcoe (dmb, dsb) instead of bitfields matching.
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llvm-svn: 129148
2011-04-08 20:03:46 +00:00
a9570f77d5
Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.
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PR9650
rdar://problem/9257565
llvm-svn: 129147
2011-04-08 19:41:22 +00:00
875e0e4626
Sanity check the option operand for DMB/DSB.
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PR9648
rdar://problem/9257634
llvm-svn: 129146
2011-04-08 19:18:07 +00:00
a5dcd98a47
Mark hasExtraDefRegAllocReq=1 on LDRD.
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The previous cleanup of LDRD got overzealous and removed it, causing post-RA
scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued.
rdar://9244161
llvm-svn: 129144
2011-04-08 18:47:05 +00:00
a868bbbb66
reindent this whole file and do a variety of stylistic cleanups.
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This code is still a long way from following best practices.
llvm-svn: 129140
2011-04-08 18:02:51 +00:00
ca320f54da
fix this to build with the recent StructType changes.
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llvm-svn: 129139
2011-04-08 17:56:47 +00:00
18b81c52bb
Refactor MCJIT 32-bit section loading.
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Teach 32-bit section loading to use the Memory Manager interface, just like
the 64-bit loading does. Tidy up a few other things here and there.
llvm-svn: 129138
2011-04-08 17:31:24 +00:00
74c74ba81c
MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it.
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Add tests for that.
llvm-svn: 129137
2011-04-08 17:29:58 +00:00
466d0c1f93
llvm.global_[cd]tor is defined to be either external, or appending with an array
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of { i32, void ()* }. Teach the verifier to verify that, deleting copies of
checks strewn about.
llvm-svn: 129128
2011-04-08 07:30:21 +00:00
33984c6973
Only emit the AvailableFeatures variable if it's used.
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llvm-svn: 129124
2011-04-08 04:08:57 +00:00
a21d470870
Also add the late notes for Mips in the current release note
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llvm-svn: 129122
2011-04-08 03:06:22 +00:00
7e51b4640f
Add sanity checking for bad register specifier(s) for the DPFrm instructions.
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Add more test cases to exercise the logical branches related to the above change.
llvm-svn: 129117
2011-04-08 00:29:09 +00:00
9a1a34b105
Update tests
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llvm-svn: 129116
2011-04-07 23:51:25 +00:00
b80875edee
Micro optimization and improved similarity with gas' output:
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When two section names share a suffix, reuse the entry in shstrtab.
llvm-svn: 129115
2011-04-07 23:21:52 +00:00
bc3d8b212f
Do not let debug info interfer with branch folding.
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llvm-svn: 129114
2011-04-07 23:11:25 +00:00
165a07adf9
Add a VEXT test.
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llvm-svn: 129111
2011-04-07 22:04:01 +00:00
bc3f79044a
Replace the old algorithm that emitted the "print the alias for an instruction"
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with the newer, cleaner model. It uses the IAPrinter class to hold the
information that is needed to match an instruction with its alias. This also
takes into account the available features of the platform.
There is one bit of ugliness. The way the logic determines if a pattern is
unique is O(N**2), which is gross. But in reality, the number of items it's
checking against isn't large. So while it's N**2, it shouldn't be a massive time
sink.
llvm-svn: 129110
2011-04-07 21:20:06 +00:00
ece7c9c282
If present, use gold's support for getting a file view. This prevents having
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to map the file both in the linker and in the plugin.
llvm-svn: 129109
2011-04-07 21:11:00 +00:00
9a3f2772f0
Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183.
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llvm-svn: 129107
2011-04-07 20:31:12 +00:00
88bc341061
Add support for .skip.
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Patch by Roman Divacky.
Fixes PR9361.
llvm-svn: 129106
2011-04-07 20:26:23 +00:00
052163e6d3
Fix indentation.
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llvm-svn: 129105
2011-04-07 20:25:10 +00:00
94ee37e487
Update ATUsed every time after expandRegLargeImmPair is called.
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llvm-svn: 129104
2011-04-07 20:23:26 +00:00
27f3330132
Fixed encoding for VEXTqf
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llvm-svn: 129101
2011-04-07 19:56:12 +00:00
2ad0b37318
Added a check in the preRA scheduler for potential interference on a
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induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.
Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing
llvm-svn: 129100
2011-04-07 19:54:57 +00:00
d6f1c58914
Fix handling of functions with internal linkage.
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llvm-svn: 129099
2011-04-07 19:51:44 +00:00
04efb8f6ce
Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
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Add some test cases.
llvm-svn: 129098
2011-04-07 19:28:58 +00:00
07606661f9
Add sanity checking for invalid register encodings for saturating instructions.
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llvm-svn: 129096
2011-04-07 19:02:08 +00:00
64beb47783
Recompute hasPHIKill flags when shrinking live intervals.
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PHI values may be deleted, causing the flags to be wrong. This fixes PR9616.
llvm-svn: 129092
2011-04-07 18:43:14 +00:00
194a2267ad
Add some more comments about checkings of invalid register numbers.
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And two test cases.
llvm-svn: 129090
2011-04-07 18:33:19 +00:00
e4e4e37580
Expose more passes to the C API.
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llvm-svn: 129087
2011-04-07 18:20:46 +00:00
994c16833c
Avoid moving iterators when the previous block was just visited.
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llvm-svn: 129081
2011-04-07 17:27:50 +00:00
1c0db0fd21
Prefer multiplications to divisions.
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llvm-svn: 129080
2011-04-07 17:27:48 +00:00
6d2bbc1c20
Extract SpillPlacement::addLinks for handling the special transparent blocks.
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llvm-svn: 129079
2011-04-07 17:27:46 +00:00
197c35298a
While hoisting common code from if/else, hoist debug info intrinsics if they match.
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llvm-svn: 129078
2011-04-07 17:27:36 +00:00
266792a55a
Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.
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llvm-svn: 129074
2011-04-07 15:24:20 +00:00
65bef04ea7
Fix a bit of nonsense.
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llvm-svn: 129073
2011-04-07 12:41:09 +00:00
5ddaab1789
add faust too
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llvm-svn: 129053
2011-04-07 03:09:21 +00:00
caefe9346d
add a few late stragglers.
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llvm-svn: 129052
2011-04-07 03:08:22 +00:00
6c6be946fc
Fixed a bug where missing EDInstInfo would cause
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tokenization to crash and burn.
llvm-svn: 129051
2011-04-07 01:56:01 +00:00
313ec7953a
Sanity check MSRi for invalid mask values and reject it as invalid.
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rdar://problem/9246844
llvm-svn: 129050
2011-04-07 01:37:34 +00:00
c5f22a7815
PR9634: Don't unconditionally tell the AliasSetTracker that the PreheaderLoad
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is equivalent to any other relevant value; it isn't true in general.
If it is equivalent, the LoopPromoter will tell the AST the equivalence.
Also, delete the PreheaderLoad if it is unused.
Chris, since you were the last one to make major changes here, can you check
that this is sane?
llvm-svn: 129049
2011-04-07 01:35:06 +00:00
c0e86fb965
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
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for USAD8 and USADA8.
rdar://problem/9247060
llvm-svn: 129047
2011-04-07 01:05:52 +00:00
a7c7b54dde
Change -arm-divmod-libcall to a target neutral option.
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llvm-svn: 129045
2011-04-07 00:58:44 +00:00
b7c9c407f9
Remove dead code. rdar://9221736.
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llvm-svn: 129044
2011-04-07 00:56:37 +00:00
Nick Lewycky