Commit Graph

8931 Commits

Author SHA1 Message Date
Dmitry Preobrazhensky 9e3f86e273 [AMDGPU][MC][NFC][DOC] Updated description of registers
Corrected list of available register tuples to reflect changes introduced by
commits https://reviews.llvm.org/D103672 and https://reviews.llvm.org/D103800

See bug https://bugs.llvm.org/show_bug.cgi?id=51388
2021-09-03 13:09:54 +03:00
Yuichi Yoshida 1708d17423 Reformulate OrcJIT tutorial doc to make it more clear.
Fixed a minor writing error. The text was hard to understand.

Reviewed By: lhames, mehdi_amini

Differential Revision: https://reviews.llvm.org/D106235
2021-09-03 04:59:37 +00:00
Roman Lebedev 3f1f08f0ed
Revert @llvm.isnan intrinsic patchset.
Please refer to
https://lists.llvm.org/pipermail/llvm-dev/2021-September/152440.html
(and that whole thread.)

TLDR: the original patch had no prior RFC, yet it had some changes that
really need a proper RFC discussion. It won't be productive to discuss
such an RFC, once it's actually posted, while said patch is already
committed, because that introduces bias towards already-committed stuff,
and the tree is potentially in broken state meanwhile.

While the end result of discussion may lead back to the current design,
it may also not lead to the current design.

Therefore i take it upon myself
to revert the tree back to last known good state.

This reverts commit 4c4093e6e3.
This reverts commit 0a2b1ba33a.
This reverts commit d9873711cb.
This reverts commit 791006fb8c.
This reverts commit c22b64ef66.
This reverts commit 72ebcd3198.
This reverts commit 5fa6039a5f.
This reverts commit 9efda541bf.
This reverts commit 94d3ff09cf.
2021-09-02 13:53:56 +03:00
Simon Moll ea2cdbf5e6 [VP] Declaration and docs for vp.select intrinsic
llvm.vp.select extends the regular select instruction with an explicit
vector length (%evl).

All lanes with indexes at and above %evl are
undefined. Lanes below %evl are taken from the first input where the
mask is true and from the second input otherwise.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D105351
2021-09-02 11:17:14 +02:00
Arthur Eubanks 2413d6063b [docs] Mention that the legacy PM is deprecated and will be removed after 14
Per https://lists.llvm.org/pipermail/llvm-dev/2021-August/152305.html.

Reviewed By: MaskRay, fhahn

Differential Revision: https://reviews.llvm.org/D109080
2021-09-01 23:31:48 -07:00
Scott Linder 0022426917 [AMDGPU] Update Call Convention docs for GFX90A
Document the CSR AGPRs for GFX90A.

Remove the TODO for gfx908, as the answer is that we don't mark any
AGPRs as callee-saved except for GFX90A, i.e. the docs as-is are correct
for gfx908.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D109009
2021-09-01 20:02:41 +00:00
Sylvestre Ledru d396d09fc2 Document LLVM_ENABLE_RUNTIMES
Reviewed By: phosek, MaskRay

Differential Revision: https://reviews.llvm.org/D108890
2021-09-01 08:45:40 +02:00
Sylvestre Ledru c28473fe4a Fix some typos in the llvm docs 2021-08-31 21:31:20 +02:00
Shivam Gupta 8254f4afcb [Docs][Phabricator] Mention how to create a draft revision
https://llvm.org/docs/Phabricator.html have two links to Arcnist guide but
none of them mention how to create a draft revision. It would create some less noise if
developers create draft revisoin in this(--draft) way instead of [WIP] tag way.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D108970
2021-08-31 11:43:04 +05:30
Shivam Gupta 387a8dea72 [Docs] Remove subversion reference from MyFirstTypoFix.rst 2021-08-31 11:33:30 +05:30
pooja2299 843da6f408 [docs][GlobalISel]Adding info for G_JUMP_TABLE generic opcode
Added description of jump table and G_JUMP_TABLE opcode.

Differential Revision: https://reviews.llvm.org/D107630
2021-08-31 00:41:28 +05:30
Shivam Gupta 3a6b722db8 [docs] Add a new tutorial that talk about how to make a change to llvm
This tutorial will guide you through the process of making a change to LLVM, and contributing it back to the LLVM project.
We'll be making a change to Clang, but the steps for other parts of LLVM are the same. Even though the change we'll be making is simple,
we're going to cover steps like building LLVM, running the tests, and code review. This is good practice, and you'll be prepared for making larger changes.

Authors: @meikeb , @gribozavr
Commit: Zhiqian Xia

PS - This is a duplicate revision of https://reviews.llvm.org/D100714 which was actually used for patch review.

Reviewed By: kuhnel

Differential Revision: https://reviews.llvm.org/D108267
2021-08-30 07:01:04 +00:00
Kazu Hirata 5294a0f7c3 [llvm] Fix typos in documentation (NFC) 2021-08-28 06:37:03 -07:00
Michał Górny 2f69c82cec [llvm] [lit] Support forcing lexical test order
Add a new --order option to choose between available test orders:
the default "smart" order, predictable "lexical" order or "random"
order.  Default to using lexical order and one job in the lit test
suite.

Differential Revision: https://reviews.llvm.org/D107695
2021-08-27 20:47:11 +02:00
Dmitry Preobrazhensky 8ea3e9d9a2 [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- Added f16 omod modifier (bug 51386).
- Corrected names of data types (bug 48638).
- Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231).
- Corrected description of integer operands (bug 51130).
- Corrected description of 8-bit DS offsets (bug 51536).
- Improved PERMLANE op_sel description.
- Corrected *SAD* opcode types.
2021-08-27 17:23:20 +03:00
Yaron Keren 692ebe5395 [docs] Add DIA register instructions to Getting Started with Visual Studio page
Since Visual Studio 2017 the DIA libs are not registered by default, see:
https://docs.microsoft.com/en-us/visualstudio/extensibility/breaking-changes-2017?view=vs-2019#change-reduce-registry-impact
LLDB building instruction already specify registering these DLLs, required
both the LLVM PDB tests and LLDB build.

Differential Revision: https://reviews.llvm.org/D108811
2021-08-27 13:10:19 +03:00
Matt Arsenault 088cc63640 AMDGPU: Invert AMDGPUAttributor
Switch to using BitIntegerState for each of the inputs, and invert
their meanings.

This now diverges more from the old AMDGPUAnnotateKernelFeatures, but
this isn't used yet anyway.
2021-08-26 21:32:13 -04:00
Fangrui Song a42bd1b560 [CMake] Change -DENABLE_EXPERIMENTAL_NEW_PASS_MANAGER=off to -DLLVM_ENABLE_NEW_PASS_MANAGER=off
LLVM_ENABLE_NEW_PASS_MANAGER is set to ENABLE_EXPERIMENTAL_NEW_PASS_MANAGER, so
-DLLVM_ENABLE_NEW_PASS_MANAGER=off has no effect.

Change the cache variable to LLVM_ENABLE_NEW_PASS_MANAGER instead.
A user opting out the new PM needs to switch from
-DENABLE_EXPERIMENTAL_NEW_PASS_MANAGER=off to
-DLLVM_ENABLE_NEW_PASS_MANAGER=off.

Also give a warning that -DLLVM_ENABLE_NEW_PASS_MANAGER=off is deprecated.

Reviewed By: aeubanks, phosek

Differential Revision: https://reviews.llvm.org/D108775
2021-08-26 14:25:31 -07:00
RamNalamothu 9b9e7f6f4e [docs, AMDGPU] Fix typo in dwarf register number mapping
Reviewed By: xgupta

Differential Revision: https://reviews.llvm.org/D108557
2021-08-26 23:55:29 +05:30
Yaron Keren 1958575859 [docs] Update Getting Started with Visual Studio guide
Update this document for 2021.

Reviewed By: aaron.ballman, kuhnel, amccarth

Differential Revision: https://reviews.llvm.org/D108513
2021-08-26 21:21:36 +03:00
Patrick Holland fe01014faa [MCA] Moved View.h and View.cpp from /tools/llvm-mca/ to /lib/MCA/.
Moved View.h and View.cpp from /tools/llvm-mca/Views/ to /lib/MCA/ and
/include/llvm/MCA/. This is so that targets can define their own Views within
the /lib/Target/ directory (so that the View can use backend functionality).
To enable these Views within mca, targets will need to add them to the vector of
Views returned by their target's CustomBehaviour::getViews() methods.

Differential Revision: https://reviews.llvm.org/D108520
2021-08-25 12:12:47 -07:00
Nick Desaulniers 846e562dcc [Clang] add support for error+warning fn attrs
Add support for the GNU C style __attribute__((error(""))) and
__attribute__((warning(""))). These attributes are meant to be put on
declarations of functions whom should not be called.

They are frequently used to provide compile time diagnostics similar to
_Static_assert, but which may rely on non-ICE conditions (ie. relying on
compiler optimizations). This is also similar to diagnose_if function
attribute, but can diagnose after optimizations have been run.

While users may instead simply call undefined functions in such cases to
get a linkage failure from the linker, these provide a much more
ergonomic and actionable diagnostic to users and do so at compile time
rather than at link time. Users instead may be able use inline asm .err
directives.

These are used throughout the Linux kernel in its implementation of
BUILD_BUG and BUILD_BUG_ON macros. These macros generally cannot be
converted to use _Static_assert because many of the parameters are not
ICEs. The Linux kernel still needs to be modified to make use of these
when building with Clang; I have a patch that does so I will send once
this feature is landed.

To do so, we create a new IR level Function attribute, "dontcall" (both
error and warning boil down to one IR Fn Attr).  Then, similar to calls
to inline asm, we attach a !srcloc Metadata node to call sites of such
attributed callees.

The backend diagnoses these during instruction selection, while we still
know that a call is a call (vs say a JMP that's a tail call) in an arch
agnostic manner.

The frontend then reconstructs the SourceLocation from that Metadata,
and determines whether to emit an error or warning based on the callee's
attribute.

Link: https://bugs.llvm.org/show_bug.cgi?id=16428
Link: https://github.com/ClangBuiltLinux/linux/issues/1173

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D106030
2021-08-25 10:34:18 -07:00
Fangrui Song 40aab0412f [test] Migrate -gcc-toolchain with space separator to --gcc-toolchain=
Space separated driver options are uncommon but Clang traditionally
did not do a good job. --gcc-toolchain= is the preferred form.
2021-08-20 15:24:58 -07:00
Jessica Paquette af8e09d4bb [GlobalISel] Add G_LLROUND
Basically the same as G_LROUND. Handles the llvm.llround family of intrinsics.

Also add a helper function to the MachineVerifier for checking if all of the
(virtual register) operands of an instruction are scalars. Seems like a useful
thing to have.

Differential Revision: https://reviews.llvm.org/D108429
2021-08-20 14:07:21 -07:00
Alexander Potapenko b0391dfc73 [clang][Codegen] Introduce the disable_sanitizer_instrumentation attribute
The purpose of __attribute__((disable_sanitizer_instrumentation)) is to
prevent all kinds of sanitizer instrumentation applied to a certain
function, Objective-C method, or global variable.

The no_sanitize(...) attribute drops instrumentation checks, but may
still insert code preventing false positive reports. In some cases
though (e.g. when building Linux kernel with -fsanitize=kernel-memory
or -fsanitize=thread) the users may want to avoid any kind of
instrumentation.

Differential Revision: https://reviews.llvm.org/D108029
2021-08-20 14:01:06 +02:00
Yaron Keren 25c8ffa223 [docs] Clarify how to run cmake and llvm-lit with Visual Studio addressing PR45978
Differential Revision: https://reviews.llvm.org/D108444
2021-08-20 10:54:35 +03:00
Jessica Paquette 3118926483 [GlobalISel] Add a G_LROUND instruction
Meant to represent the `@llvm.lround.*` family.

Add the opcode, docs, and verification.

Differential Revision: https://reviews.llvm.org/D108417
2021-08-19 17:06:24 -07:00
Yaron Keren 1987eb9e9c [docs] Document how to install sphinx and recommonmark on Ubuntu
Differential Revision: https://reviews.llvm.org/D108374
2021-08-19 18:24:17 +03:00
Yaron Keren 23b16d2453 [docs] Document that psutil should be installed in non-user location
Differential Revision: https://reviews.llvm.org/D108356
2021-08-19 13:42:31 +03:00
Jessica Paquette 0a2b1ba33a [GlobalISel] Add G_ISNAN
Add a generic opcode equivalent to the `llvm.isnan` intrinsic +
MachineVerifier support for it.

We need an opcode here because we may want target-specific lowering later on.

Differential Revision: https://reviews.llvm.org/D108222
2021-08-18 10:42:05 -07:00
Nikhil Gupta 8ea60cf1de Adding an Nvidia representative to security group
Adding Nikhil Gupta as an Nvidia representative to the llvm security
group.

Differential Revision: https://reviews.llvm.org/D106906
2021-08-18 12:08:11 +02:00
Fraser Cormack f3e9047249 [VP] Add vector-predicated reduction intrinsics
This patch adds vector-predicated ("VP") reduction intrinsics corresponding to
each of the existing unpredicated `llvm.vector.reduce.*` versions. Unlike the
unpredicated reductions, all VP reductions have a start value. This start value
is returned when the no vector element is active.

Support for expansion on targets without native vector-predication support is
included.

This patch is based on the ["reduction
slice"](https://reviews.llvm.org/D57504#1732277) of the LLVM-VP reference patch
(https://reviews.llvm.org/D57504).

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D104308
2021-08-17 17:56:35 +01:00
Fangrui Song 676f16bed5 [docs] Change llvm-xray options to use the preferred double-dash forms 2021-08-15 21:09:35 -07:00
Florian Hahn f999312872
Recommit "[Matrix] Overload stride arg in matrix.columnwise.load/store."
This reverts the revert 28c04794df.

The failing MLIR test that caused the revert should be fixed  in this
version.

Also includes a PPC test fix previously in 1f87c7c478.
2021-08-12 18:31:57 +01:00
Mehdi Amini 28c04794df Revert "[Matrix] Overload stride arg in matrix.columnwise.load/store."
This reverts commit a1ef81de35.

Broke the MLIR buildbot.
2021-08-12 11:57:19 +00:00
Florian Hahn a1ef81de35
[Matrix] Overload stride arg in matrix.columnwise.load/store.
This patch adjusts the intrinsics definition of
llvm.matrix.column.major.load and llvm.matrix.column.major.store to
allow overloading the type of the stride. The bitwidth of the stride is
used to perform the offset computation.

This fixes a crash when using __builtin_matrix_column_major_load or
__builtin_matrix_column_major_store on 32 bit platforms. The stride argument
of the builtins are defined as `size_t`, which is 32 bits wide on 32 bit
platforms.

Note that we still perform offset computations with 64 bit width on 32
bit platforms for accesses that do not take a user-specified stride.
This can be fixed separately.

Fixes PR51304.

Reviewed By: erichkeane

Differential Revision: https://reviews.llvm.org/D107349
2021-08-12 10:45:25 +01:00
Volodymyr Sapsai 178da37b18 [docs] Clarify variable-width integer (VBR) encoding example.
Show that the bit chunks are placed starting at the least significant
bit. Select a different number, so the bit chunks have different values
and it is more obvious where they are in the encoded result.

Differential Revision: https://reviews.llvm.org/D107796
2021-08-10 12:59:06 -07:00
Paul Robinson ca58d9af73 [Security] Replace Josh Eads with Tim Penge as a Sony rep 2021-08-10 12:54:23 -04:00
Wang, Pengfei 6f7f5b54c8 [X86] AVX512FP16 instructions enabling 1/6
1. Enable FP16 type support and basic declarations used by following patches.
2. Enable new instructions VMOVW and VMOVSH.

Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D105263
2021-08-10 12:46:01 +08:00
Paul Robinson 5b2037fa95 Revert "Reapply "[lit] Have REQUIRES support the target triple""
This reverts commit 187c69e9ef.
compiler-rt/test/cross_over_uniform_dist.test refuses to pass.
2021-08-09 12:14:57 -07:00
Paul Robinson 187c69e9ef Reapply "[lit] Have REQUIRES support the target triple"
This reverts commit 3229c97151.

With a2acac6 in place this should provide enough info to work out
any repeat of the failure in cross_ovver_uniform_dist.test.
2021-08-09 06:43:52 -07:00
Christian Kühnel 15acaad79d [doc] added section on generating the html doc
Added a new section on generating the html documentation
from the rst/md sources to our documentation.

Background: I wanted to check what my documenation
changes would look like on the website and had a hard
time finding how to do that. So I wanted to save other
folks the effort.

Differential Revision: https://reviews.llvm.org/D107460
2021-08-09 07:27:56 +00:00
Paul Robinson 3229c97151 Revert "[lit] Have REQUIRES support the target triple"
This reverts commit 100a7b6197.

Speculating that this is the reason behind a sanitizer failure:
https://lab.llvm.org/buildbot/#/builders/37/builds/5945
2021-08-06 15:03:49 -07:00
Paul Robinson 100a7b6197 [lit] Have REQUIRES support the target triple
Currently the UNSUPPORTED and XFAIL clauses support specifying
substrings of the target triple; but REQUIRES does not, which can trip
people up or lead to hacking config files to insert substitute feature
names.  Consistency across all three lit clauses seems preferable.

Differential Revision: https://reviews.llvm.org/D107162
2021-08-06 07:31:15 -07:00
Dmitry Preobrazhensky 02b1c3f052 [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Corrected sendmsg description (bug https://bugs.llvm.org/show_bug.cgi?id=49648).
2021-08-06 15:52:26 +03:00
Reshabh Sharma 5173854f19 [AMDGPU] Handle functions in llvm's global ctors and dtors list
This patch introduces a new code object metadata field, ".kind"
which is used to add support for init and fini kernels.

HSAStreamer will use function attributes, "device-init" and
"device-fini" to distinguish between init and fini kernels from
the regular kernels and will emit metadata with ".kind" set to
"init" and "fini" respectively.

To reduce the number of init and fini kernels, the ctors and
dtors present in the llvm's global.ctors and global.dtors lists
are called from a single init and fini kernel respectively.

Reviewed by: yaxunl

Differential Revision: https://reviews.llvm.org/D105682
2021-08-06 15:53:33 +05:30
Serge Pavlov 4c4093e6e3 Introduce intrinsic llvm.isnan
This is recommit of the patch 16ff91ebcc,
reverted in 0c28a7c990 because it had
an error in call of getFastMathFlags (base type should be FPMathOperator
but not Instruction). The original commit message is duplicated below:

    Clang has builtin function '__builtin_isnan', which implements C
    library function 'isnan'. This function now is implemented entirely in
    clang codegen, which expands the function into set of IR operations.
    There are three mechanisms by which the expansion can be made.

    * The most common mechanism is using an unordered comparison made by
      instruction 'fcmp uno'. This simple solution is target-independent
      and works well in most cases. It however is not suitable if floating
      point exceptions are tracked. Corresponding IEEE 754 operation and C
      function must never raise FP exception, even if the argument is a
      signaling NaN. Compare instructions usually does not have such
      property, they raise 'invalid' exception in such case. So this
      mechanism is unsuitable when exception behavior is strict. In
      particular it could result in unexpected trapping if argument is SNaN.

    * Another solution was implemented in https://reviews.llvm.org/D95948.
      It is used in the cases when raising FP exceptions by 'isnan' is not
      allowed. This solution implements 'isnan' using integer operations.
      It solves the problem of exceptions, but offers one solution for all
      targets, however some can do the check in more efficient way.

    * Solution implemented by https://reviews.llvm.org/D96568 introduced a
      hook 'clang::TargetCodeGenInfo::testFPKind', which injects target
      specific code into IR. Now only SystemZ implements this hook and it
      generates a call to target specific intrinsic function.

    Although these mechanisms allow to implement 'isnan' with enough
    efficiency, expanding 'isnan' in clang has drawbacks:

    * The operation 'isnan' is hidden behind generic integer operations or
      target-specific intrinsics. It complicates analysis and can prevent
      some optimizations.

    * IR can be created by tools other than clang, in this case treatment
      of 'isnan' has to be duplicated in that tool.

    Another issue with the current implementation of 'isnan' comes from the
    use of options '-ffast-math' or '-fno-honor-nans'. If such option is
    specified, 'fcmp uno' may be optimized to 'false'. It is valid
    optimization in general, but it results in 'isnan' always returning
    'false'. For example, in some libc++ implementations the following code
    returns 'false':

        std::isnan(std::numeric_limits<float>::quiet_NaN())

    The options '-ffast-math' and '-fno-honor-nans' imply that FP operation
    operands are never NaNs. This assumption however should not be applied
    to the functions that check FP number properties, including 'isnan'. If
    such function returns expected result instead of actually making
    checks, it becomes useless in many cases. The option '-ffast-math' is
    often used for performance critical code, as it can speed up execution
    by the expense of manual treatment of corner cases. If 'isnan' returns
    assumed result, a user cannot use it in the manual treatment of NaNs
    and has to invent replacements, like making the check using integer
    operations. There is a discussion in https://reviews.llvm.org/D18513#387418,
    which also expresses the opinion, that limitations imposed by
    '-ffast-math' should be applied only to 'math' functions but not to
    'tests'.

    To overcome these drawbacks, this change introduces a new IR intrinsic
    function 'llvm.isnan', which realizes the check as specified by IEEE-754
    and C standards in target-agnostic way. During IR transformations it
    does not undergo undesirable optimizations. It reaches instruction
    selection, where is lowered in target-dependent way. The lowering can
    vary depending on options like '-ffast-math' or '-ffp-model' so the
    resulting code satisfies requested semantics.

    Differential Revision: https://reviews.llvm.org/D104854
2021-08-06 14:32:27 +07:00
Christian Kühnel 4b8806d957 [doc] added links to discord and discourse
Some folks are not aware that we have a Discourse server in addition to the mailing lists and a Discord server in addition to IRC. So I think we should add that.
These were announced on the mailing list a while ago: https://lists.llvm.org/pipermail/llvm-dev/2019-November/136880.html

Differential Revision: https://reviews.llvm.org/D100943
2021-08-06 07:04:52 +00:00
Reshabh Sharma dce35ef104 Revert "[AMDGPU] Handle functions in llvm's global ctors and dtors list"
This reverts commit d42e70b3d3.
2021-08-04 23:33:31 +05:30
Reshabh Sharma d42e70b3d3 [AMDGPU] Handle functions in llvm's global ctors and dtors list
This patch introduces a new code object metadata field, ".kind"
which is used to add support for init and fini kernels.

HSAStreamer will use function attributes, "device-init" and
"device-fini" to distinguish between init and fini kernels from
the regular kernels and will emit metadata with ".kind" set to
"init" and "fini" respectively.

To reduce the number of init and fini kernels, the ctors and
dtors present in the llvm's global.ctors and global.dtors lists
are called from a single init and fini kernel respectively.

Reviewed by: yaxunl

Differential Revision: https://reviews.llvm.org/D105682
2021-08-04 19:53:33 +05:30