maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
95,588 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

16254 Commits

Author SHA1 Message Date
Chris Lattner 9c9bfb6870 per a suggestion by Frits van Bommel, mark all MBlaze Pseudo 
instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.

llvm-svn: 118125
 2010-11-02 23:57:05 +00:00
Owen Anderson 0ebd1fd594 Revert r118097 to fix buildbots. 
llvm-svn: 118121
 2010-11-02 23:47:29 +00:00
Chris Lattner cc5dce89d4 Completely reject instructions that have an operand in their 
ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).

llvm-svn: 118119
 2010-11-02 23:40:41 +00:00
Bill Wendling f9eebb58b9 Obsessive formatting changes. No functionality impact. 
llvm-svn: 118103
 2010-11-02 22:53:11 +00:00
Bill Wendling 23436b6530 Omit unused parameter name. 
llvm-svn: 118099
 2010-11-02 22:46:04 +00:00
Bill Wendling 91da9abbee Simplify the EncodeInstruction method now that a lot of the special case stuff 
is handled with the MC encoder.

llvm-svn: 118098
 2010-11-02 22:44:12 +00:00
Owen Anderson 7c30390277 Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning. 
llvm-svn: 118097
 2010-11-02 22:41:42 +00:00
Bill Wendling 603bd8f54c Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work 
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094
 2010-11-02 22:31:46 +00:00
Owen Anderson a4b63e19d2 Rename encoder methods to match naming convention. 
llvm-svn: 118093
 2010-11-02 22:28:01 +00:00
Chris Lattner 15977afb02 mark a few codegenonly instructions. 
llvm-svn: 118092
 2010-11-02 22:26:33 +00:00
Owen Anderson dec87e10fd Provide correct encodings for the remaining vst variants that we currently generate. 
llvm-svn: 118087
 2010-11-02 22:18:18 +00:00
Owen Anderson adf88d4c5f Tentative encodings for the "single element from one lane" variant of vst1. 
llvm-svn: 118084
 2010-11-02 21:54:45 +00:00
Owen Anderson b95618cfe0 Add correct encodings for basic variants for vst3 and vst4. 
llvm-svn: 118082
 2010-11-02 21:47:03 +00:00
Bob Wilson d80b29d6f7 Add NEON VST1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 118069
 2010-11-02 21:18:25 +00:00
Owen Anderson fa08e1e277 Add correct encodings for the basic variants for vst2. 
llvm-svn: 118068
 2010-11-02 21:16:58 +00:00
Owen Anderson 87c62e54e6 Add correct encodings for the basic form of vst1. 
llvm-svn: 118067
 2010-11-02 21:06:06 +00:00
Owen Anderson 9f20daf3b4 Factor out a common encoding class for loads and stores with a lane parameter. 
llvm-svn: 118055
 2010-11-02 20:47:39 +00:00
Owen Anderson a83859539f Add correct encodings for the rest of the vld instructions that we generate. 
llvm-svn: 118053
 2010-11-02 20:40:59 +00:00
Jim Grosbach 93a4d44ee6 Sort bit assignments. Cosmetic change only. 
llvm-svn: 118029
 2010-11-02 17:59:04 +00:00
Jim Grosbach 0b7fda23cc Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke 
assumptions about stack layout. Specifically, LR must be saved next to FP.

llvm-svn: 118026
 2010-11-02 17:35:25 +00:00
Owen Anderson 526ffd57d2 Add correct NEON encodings for vld2, vld3, and vld4 basic variants. 
llvm-svn: 117997
 2010-11-02 01:24:55 +00:00
Eric Christopher b2abb508ae Remove an assert - it's possible to be hit, and we just want to avoid 
handling those cases for now.

llvm-svn: 117996
 2010-11-02 01:24:49 +00:00
Eric Christopher ac746e1b38 Whitespeace 
llvm-svn: 117995
 2010-11-02 01:22:45 +00:00
Eric Christopher e8fccc82e4 No really, no thumb1 for arm fast isel. Also add an informative comment as 
to what someone would need to do to support thumb1.

llvm-svn: 117994
 2010-11-02 01:21:28 +00:00
Owen Anderson b3ca2060c0 Attempt to provide correct encodings for a number of other vld1 variants, which we can't test 
since we can neither generate nor parse them at the moment.

llvm-svn: 117988
 2010-11-02 00:24:52 +00:00
Owen Anderson f1610f7910 Add aesthetic break. 
llvm-svn: 117986
 2010-11-02 00:14:00 +00:00
Owen Anderson ad40234eff Add correct NEON encodings for the "multiple single elements" form of vld. 
llvm-svn: 117984
 2010-11-02 00:05:05 +00:00
Jim Grosbach 2ba03aa618 Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME 
for handling the fixup necessary.

llvm-svn: 117978
 2010-11-01 23:45:50 +00:00
Jim Grosbach a3efae35f5 Remove unused function. 
llvm-svn: 117977
 2010-11-01 23:40:56 +00:00
Bob Wilson dd9fbaa9c0 Add support for alignment operands on VLD1-lane instructions. 
This is another part of the fix for Radar 8599955.

llvm-svn: 117976
 2010-11-01 23:40:51 +00:00
Bill Wendling 3f37ade36e Missed reverting this bit. 
llvm-svn: 117971
 2010-11-01 23:17:54 +00:00
Bill Wendling f7e176a3ec Minor cleanup. 
llvm-svn: 117969
 2010-11-01 23:11:22 +00:00
Chris Lattner 60d555c178 rearrange a bit. 
llvm-svn: 117967
 2010-11-01 23:07:52 +00:00
Bob Wilson dc44990c7d Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 117964
 2010-11-01 22:04:05 +00:00
Bill Wendling 418bd53008 Move the machine operand MC encoding patterns to the parent classes. 
llvm-svn: 117956
 2010-11-01 21:17:06 +00:00
Chris Lattner 865dd96f22 use our fancy new MnemonicAlias mechanism to remove a bunch of hacks 
from X86AsmParser.cpp

llvm-svn: 117952
 2010-11-01 21:06:34 +00:00
Bill Wendling c6627eec13 When we look at instructions to convert to setting the 's' flag, we need to look 
at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.

llvm-svn: 117950
 2010-11-01 20:41:43 +00:00
Bob Wilson 44be217af1 NEON does not support truncating vector stores. Radar 8598391. 
llvm-svn: 117940
 2010-11-01 18:31:39 +00:00
Jim Grosbach 7d45c101e5 Add FIXME. 
llvm-svn: 117936
 2010-11-01 18:11:14 +00:00
Jim Grosbach fddf36d254 Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates 
codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931
 2010-11-01 17:08:58 +00:00
Jim Grosbach 0190a649e8 Mark ARM subtarget features that are available for the assembler. 
llvm-svn: 117929
 2010-11-01 16:59:54 +00:00
Jim Grosbach 99710a871c trailing whitespace 
llvm-svn: 117927
 2010-11-01 16:44:21 +00:00
Jim Grosbach 5b373341fc The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the 
patterns as such

llvm-svn: 117923
 2010-11-01 15:59:52 +00:00
Bill Wendling 2623343625 Move instruction encoding bits into the parent class and remove the temporary 
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906
 2010-11-01 06:00:39 +00:00
Chris Lattner 1acd6b1edc "mov[zs]x (mem), GR16" are not ambiguous: the mem 
must be 8 bits.  Support this memory form.

llvm-svn: 117902
 2010-11-01 05:41:10 +00:00
Chris Lattner dd3b09c234 Implement enough of the missing instalias support to get 
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901
 2010-11-01 05:34:34 +00:00
Chris Lattner 178f4bb62d make the asm matcher emitter reject instructions that have comments 
in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897
 2010-11-01 04:44:29 +00:00
Chris Lattner 941c19b7ba reject instructions that contain a \n in their asmstring. Mark 
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884
 2010-11-01 00:46:16 +00:00
Chris Lattner 7ff334687d fix the !eq operator in tblgen to return a bit instead of an int. 
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862
 2010-10-31 19:22:57 +00:00
Chris Lattner 9492c17baf two changes: make the asmmatcher generator ignore ARM pseudos properly, 
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861
 2010-10-31 19:15:18 +00:00
Chris Lattner 33fc3e095b reapply r117858 with apparent editor malfunction fixed (somehow I 
got a dulicated line).

llvm-svn: 117860
 2010-10-31 19:10:56 +00:00
Chris Lattner e59eef3dd1 revert r117858 while I check out a failure I missed. 
llvm-svn: 117859
 2010-10-31 19:05:32 +00:00
Chris Lattner 9293008e90 the asm matcher can't handle operands with modifiers (like ${foo:bar}). 
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858
 2010-10-31 18:48:12 +00:00
Chris Lattner eb8c0fc2eb sketch out the planned instruction alias mechanism, add some comments about 
how the push/pop mnemonic aliases are wrong.

llvm-svn: 117857
 2010-10-31 18:43:46 +00:00
Duncan Sands fb0a48ef96 Factorize the duplicated logic for choosing the right argument 
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.

llvm-svn: 117856
 2010-10-31 13:21:44 +00:00
Duncan Sands fa7e6f2417 Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86, 
which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.

llvm-svn: 117855
 2010-10-31 13:02:38 +00:00
Eric Christopher 04b0a3e651 Make sure we have a legal type (and simple) before continuing. 
llvm-svn: 117848
 2010-10-30 21:25:26 +00:00
Chris Lattner aac142cc06 Resolve a terrible hack in tblgen: instead of hardcoding 
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831
 2010-10-30 19:38:20 +00:00
Chris Lattner 2cb092dc55 Implement (and document!) support for MnemonicAlias's to have Requires 
directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830
 2010-10-30 19:23:13 +00:00
Chris Lattner 57bfc66d60 really zap alias. 
llvm-svn: 117824
 2010-10-30 18:23:25 +00:00
Chris Lattner 462bc666d2 move fcompi alias to .td file and zap some useless code. 
llvm-svn: 117823
 2010-10-30 18:22:53 +00:00
Chris Lattner daae9eea8a move rep aliases to td file 
llvm-svn: 117822
 2010-10-30 18:17:33 +00:00
Chris Lattner fa40aee871 move sal aliases to .td file. 
llvm-svn: 117821
 2010-10-30 18:14:54 +00:00
Chris Lattner 4d9f157203 fix an encoding mismatch where "sal %eax, 1" was not using the short encoding 
for shl.  Caught by inspection.

llvm-svn: 117820
 2010-10-30 18:13:10 +00:00
Chris Lattner 069132311a move a bunch more aliases from .cpp -> .td file. 
llvm-svn: 117819
 2010-10-30 18:07:17 +00:00
Chris Lattner b4a1674421 move cmov aliases to .td file. 
llvm-svn: 117818
 2010-10-30 17:56:50 +00:00
Chris Lattner f04cbe6291 move setcc and jcc aliases from .cpp to .td 
llvm-svn: 117817
 2010-10-30 17:51:45 +00:00
Chris Lattner 72c0b59e81 move some code. 
llvm-svn: 117816
 2010-10-30 17:38:55 +00:00
Chris Lattner ba7b4fea97 implement (and document!) the first kind of MC assembler alias, which 
just remaps one mnemonic to another.  Convert a few of the X86 aliases
from .cpp to .td code.

llvm-svn: 117815
 2010-10-30 17:36:36 +00:00
Jim Grosbach bbe2bbd7f7 Add FIXME. 
llvm-svn: 117787
 2010-10-30 14:54:23 +00:00
Jim Grosbach 4cf25f5ba9 Clean up comments. 
llvm-svn: 117785
 2010-10-30 13:48:28 +00:00
Jim Grosbach a71c9e2ebf Tidy up. 
llvm-svn: 117782
 2010-10-30 12:59:16 +00:00
Chris Lattner de30afc3d9 stay out of the reserved namespace 
llvm-svn: 117773
 2010-10-30 04:57:14 +00:00
Chris Lattner 549a31cd34 simplify this code. 
llvm-svn: 117771
 2010-10-30 04:35:59 +00:00
Chris Lattner 44e5981c1b split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic. 
llvm-svn: 117769
 2010-10-30 04:09:10 +00:00
Jim Grosbach 7b275105d6 Avoid re-evaluating MI.getNumOperands() every iteration of the loop. 
llvm-svn: 117766
 2010-10-30 01:40:16 +00:00
Bob Wilson 7ed597149b Overhaul memory barriers in the ARM backend. Radar 8601999. 
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

llvm-svn: 117756
 2010-10-30 00:54:37 +00:00
Jim Grosbach 74ef9e184e Encode the register list operands for ARM mode LDM/STM instructions. 
llvm-svn: 117753
 2010-10-30 00:37:59 +00:00
Bill Wendling 193961bb1a Some instructions end with an "ls" prefix, but it doesn't indicate that they are 
conditional. Check for those instructions explicitly.

llvm-svn: 117747
 2010-10-29 23:50:21 +00:00
Jim Grosbach 069f38d1bf Remove hard tab characters. 
llvm-svn: 117742
 2010-10-29 23:23:15 +00:00
Jim Grosbach 5f0d616ae5 80 column fix. 
llvm-svn: 117741
 2010-10-29 23:21:57 +00:00
Jim Grosbach 96d828448f trailing whitespace 
llvm-svn: 117740
 2010-10-29 23:21:03 +00:00
Jim Grosbach 58018e62a8 s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand 
encoder functions.

llvm-svn: 117738
 2010-10-29 23:19:55 +00:00
Evan Cheng 99cce36cf5 Fix fpscr <-> GPR latency info. 
llvm-svn: 117737
 2010-10-29 23:16:55 +00:00
Jim Grosbach 31f23b48ba add FIXME 
llvm-svn: 117718
 2010-10-29 21:56:51 +00:00
Jim Grosbach 4a0c2d73c3 Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in 
the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714
 2010-10-29 21:35:25 +00:00
Eric Christopher 5c308f8452 Handle comparison values we already have - this fixes the consumer-typeset 
failure for llvm-gcc on arm fast isel.

llvm-svn: 117710
 2010-10-29 21:08:19 +00:00
Jim Grosbach e477b1ad30 ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to 
handle it in the asm lowering.

llvm-svn: 117707
 2010-10-29 20:37:06 +00:00
Jim Grosbach cb8aec8ec9 Fix typo. 
llvm-svn: 117703
 2010-10-29 20:21:49 +00:00
Jim Grosbach 3b7e05bb97 ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS. 
llvm-svn: 117702
 2010-10-29 20:21:36 +00:00
Jim Grosbach 4e57b52394 ARM mode LDREX*/STREX* binary encodings. 
llvm-svn: 117695
 2010-10-29 19:58:57 +00:00
Jim Grosbach 6ae3fba7c8 Encoding information for ARM conditional move instructions. 
llvm-svn: 117687
 2010-10-29 19:28:17 +00:00
Evan Cheng 6c1414f9c2 Avoiding overly aggressive latency scheduling. If the two nodes share an 
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.

BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB

=>

BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB

This fixed the recent 256.bzip2 regression.

llvm-svn: 117675
 2010-10-29 18:09:28 +00:00
Evan Cheng 0c4c5ca6e1 - Don't schedule nodes with only MVT::Flag and MVT::Other values for latency. 
- Compute CopyToReg use operand latency correctly.

llvm-svn: 117674
 2010-10-29 18:07:31 +00:00
Jim Grosbach 16bd9f1ab5 Handle ARM addrmode5 instructions with an offset. 
llvm-svn: 117672
 2010-10-29 17:41:25 +00:00
John Thompson e8360b7182 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. 
llvm-svn: 117667
 2010-10-29 17:29:13 +00:00
Jim Grosbach 305ec65927 Revert 117660. Apparently it's not as trivial as that... 
llvm-svn: 117663
 2010-10-29 16:50:53 +00:00
Jim Grosbach 8682b69b81 ARM addrmode5 instructions have neither writeback nor post-indexed modes. 
llvm-svn: 117660
 2010-10-29 16:38:59 +00:00
Jim Grosbach 624bcc7371 Trailing whitespace. 
llvm-svn: 117651
 2010-10-29 14:46:02 +00:00
Benjamin Kramer 08b8c534f7 ARMAsmParser: Plug a memory leak. 
llvm-svn: 117648
 2010-10-29 09:43:39 +00:00
Eric Christopher 91d7b90185 Add an unreachable to silence warning - the switch is actually 
fully enumerated.

llvm-svn: 117647
 2010-10-29 09:26:59 +00:00
Chris Lattner 5d6f6a061b add simple support for addrmode5 operands, allowing 
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626
 2010-10-29 00:27:31 +00:00
Chris Lattner d27b05e54a give better error diagnostics, for example: 
t.s:1:14: error: invalid operand for instruction
vldr.64	d17, [r0]   
       	     ^

instead of:

t.s:1:1: error: unrecognized instruction
vldr.64	d17, [r0]   
^

llvm-svn: 117611
 2010-10-28 21:41:58 +00:00
Chris Lattner f20f79808e hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes 
the opcode string in the inst dump, e.g.:
	vmov	r2, r3, d17             @ encoding: [0x31,0x2b,0x53,0xec]
                                        @ <MCInst #989 VMOVRRD
                                        @  <MCOperand Reg:68>
                                        @  <MCOperand Reg:69>
                                        @  <MCOperand Reg:19>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>>

The "VMOVRRD" is new.

llvm-svn: 117609
 2010-10-28 21:37:33 +00:00
Chris Lattner 9487de6160 move a method out of line. 
llvm-svn: 117605
 2010-10-28 21:28:01 +00:00
Chris Lattner 9f9f4ebf0c remove the rest of hte owningptr's, no functionality change. 
llvm-svn: 117603
 2010-10-28 20:52:15 +00:00
Benjamin Kramer 851a994a42 Reduce malloc thrashing. 
llvm-svn: 117572
 2010-10-28 18:41:23 +00:00
Jim Grosbach 505607e4c6 PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. 
llvm-svn: 117571
 2010-10-28 18:34:10 +00:00
Chris Lattner b24ba7be49 rearrange ParseRegisterList. 
llvm-svn: 117560
 2010-10-28 17:23:41 +00:00
Chris Lattner bd7c9fa36b refactor some code to simplify it, eliminating some owningptr's. 
llvm-svn: 117559
 2010-10-28 17:20:03 +00:00
Evan Cheng ff310737e5 Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. 
llvm-svn: 117531
 2010-10-28 06:47:08 +00:00
Evan Cheng e2c211c1b9 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh. 
llvm-svn: 117520
 2010-10-28 02:00:25 +00:00
Evan Cheng ff1c862f8e - Assign load / store with shifter op address modes the right itinerary classes. 
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519
 2010-10-28 01:49:06 +00:00
Dale Johannesen 9c3f6bf2bf Fix pastos in handling of AVX cvttsd2si, PR8491. 
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!

llvm-svn: 117514
 2010-10-28 00:35:54 +00:00
Owen Anderson 2ef668840a Add correct NEON encodings for vtbl and vtbx. 
llvm-svn: 117513
 2010-10-28 00:18:46 +00:00
Owen Anderson 14be930317 Add correct NEON encodings for vext, vtrn, vuzp, and vzip. 
llvm-svn: 117512
 2010-10-27 23:56:39 +00:00
Bob Wilson 6c55007edb Fix compiler warnings about signed/unsigned comparisons. 
llvm-svn: 117511
 2010-10-27 23:49:00 +00:00
Evan Cheng 59bbc545e0 Shifter ops are not always free. Do not fold them (especially to form 
complex load / store addressing mode) when they have higher cost and
when they have more than one use.

llvm-svn: 117509
 2010-10-27 23:41:30 +00:00
Jim Grosbach 338de3ee56 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
 2010-10-27 23:12:14 +00:00
Owen Anderson fadb951e5b Provide correct encodings for NEON vcvt, which has its own special immediate encoding 
for specifying fractional bits for fixed point conversions.

llvm-svn: 117501
 2010-10-27 22:49:00 +00:00
Jim Grosbach 055de2c789 Trailing whitespace 
llvm-svn: 117496
 2010-10-27 21:39:08 +00:00
Owen Anderson ed9652f959 Provide correct encodings for the get_lane and set_lane variants of vmov. 
llvm-svn: 117495
 2010-10-27 21:28:09 +00:00
Kevin Enderby 5e7cb5fc27 Added the x86 instruction ud2b (2nd official undefined instruction). 
llvm-svn: 117485
 2010-10-27 20:46:49 +00:00
Jim Grosbach f4ea7084c5 JIT imm12 encoding for constant pool entry references. 
llvm-svn: 117483
 2010-10-27 20:39:40 +00:00
Bob Wilson c7334a146e SelectionDAG shuffle nodes do not allow operands with different numbers of 
elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

llvm-svn: 117482
 2010-10-27 20:38:28 +00:00
Jim Grosbach 333b0a9e74 ARM JIT fix for LDRi12 and company. 
llvm-svn: 117478
 2010-10-27 19:55:59 +00:00
Owen Anderson 40d24a4abf Provide correct NEON encodings for vdup. 
llvm-svn: 117475
 2010-10-27 19:25:54 +00:00
Michael J. Spencer 7db918f1e9 x86-Win32: Switch ftol2 calling convention from stdcall to C. 
llvm-svn: 117474
 2010-10-27 18:52:38 +00:00
Jim Grosbach ba1c6cd62f The new LDR* instruction patterns should handle the necessary encoding of 
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

llvm-svn: 117461
 2010-10-27 17:52:51 +00:00
Owen Anderson 8576a42cf3 Add correct NEON encodings for vsli and vsri. 
llvm-svn: 117459
 2010-10-27 17:40:08 +00:00
Owen Anderson d7e8135e1e Add correct NEON encodings for vsra and vrsra. 
llvm-svn: 117458
 2010-10-27 17:29:29 +00:00
Jim Grosbach 8bf1483a3d The immediate operands of an LDRi12 instruction doesn't need the addrmode2 
encoding tricks. Handle the 'imm doesn't fit in the insn' case.

llvm-svn: 117454
 2010-10-27 16:50:31 +00:00
Kevin Enderby 9ad2166899 Yet another tweak to X86 instructions to add ud2a as an alias to ud2 
(still to add ud2b).

llvm-svn: 117435
 2010-10-27 03:01:02 +00:00
Kevin Enderby 20b021c970 Another tweak to X86 instructions to add the missing flex instruction (without 
the wait prefix).

llvm-svn: 117434
 2010-10-27 02:53:04 +00:00
Kevin Enderby a1917c7555 Tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433
 2010-10-27 02:32:19 +00:00
Jim Grosbach 9d2d1f0f00 LDRi12 machine instructions handle negative offset operands normally (simple 
integer values), not with the addrmode2 encoding.

llvm-svn: 117429
 2010-10-27 01:19:41 +00:00
Kevin Enderby ba985d9dd5 Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc 
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427
 2010-10-27 00:59:28 +00:00
Jim Grosbach 2577b2e8b1 One more spot where the new arm mode LDR instruction representation 
doesn't need the additional addrmode2 register operand. Missed it the first
time around.

llvm-svn: 117421
 2010-10-27 00:38:16 +00:00
Wesley Peck e9b429e96f Adding disassembler to the MicroBlaze backend. 
llvm-svn: 117420
 2010-10-27 00:23:01 +00:00
Jim Grosbach 5a7c715470 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

llvm-svn: 117419
 2010-10-27 00:19:44 +00:00
Jim Grosbach a92801b695 Since I parameterized this bit, I should probably actually use said parameter. 
llvm-svn: 117418
 2010-10-26 23:58:04 +00:00
Dale Johannesen e660f4d072 Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches 
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet).  No functional change except
for dump output.

llvm-svn: 117413
 2010-10-26 23:11:10 +00:00
Owen Anderson 825b2d1946 Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun. 
llvm-svn: 117411
 2010-10-26 22:50:46 +00:00
Jim Grosbach 1e4d9a17c2 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Owen Anderson 2888e2c7f9 Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn. 
llvm-svn: 117402
 2010-10-26 21:58:41 +00:00
Owen Anderson e18579976f Simplify classes for shift instructions, which are never commutable. 
llvm-svn: 117398
 2010-10-26 21:13:59 +00:00
Owen Anderson 3665fee8de Provide correct NEON encodings for vshl, register and immediate forms. 
llvm-svn: 117394
 2010-10-26 20:56:57 +00:00
Jim Grosbach 9302bfdd5a Grammar. 
llvm-svn: 117388
 2010-10-26 19:34:41 +00:00
Jim Grosbach 79b3bf4d81 Nuke extraneous comment. It's applicable elsewhere, but not in this func. 
llvm-svn: 117387
 2010-10-26 19:22:23 +00:00
Owen Anderson 691ce68d3c Add correct NEON encoding for vpadal. 
llvm-svn: 117380
 2010-10-26 18:18:03 +00:00
Rafael Espindola d94f3b4ae9 handle X86::EH_RETURN64 and X86::EH_RETURN. 
llvm-svn: 117378
 2010-10-26 18:09:55 +00:00
Owen Anderson 284cb361d1 Add NEON encodings for vmov and vmvn of immediates. 
llvm-svn: 117374
 2010-10-26 17:40:54 +00:00
Rafael Espindola e8ae98817a Implement some relaxations for arithmetic instructions. The limitation 
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.

llvm-svn: 117364
 2010-10-26 14:09:12 +00:00
Kalle Raiskila a49d062234 Change v64 datalayout in SPU. 
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays, 
we use array alignment for v64 too. This makes the 
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.

This also makes an "unaligned store" test to be 
aligned, with different (but functionally equivalent)
code generated.

llvm-svn: 117360
 2010-10-26 10:45:47 +00:00
Evan Cheng e96b8d7ab6 Use instruction itinerary to determine what instructions are 'cheap'. 
llvm-svn: 117348
 2010-10-26 02:08:50 +00:00
Evan Cheng b45591979b NEON vmov's are in Neon domain. 
llvm-svn: 117347
 2010-10-26 02:03:05 +00:00
Bob Wilson 59f7cdaf98 Tidy up redundant check. 
llvm-svn: 117331
 2010-10-26 00:02:19 +00:00
Rafael Espindola d9d0c348df Produce the headers directly in the Finish method. This allows us to use 
the existing streamer methods that are endian safe.

llvm-svn: 117323
 2010-10-25 22:26:55 +00:00
Dale Johannesen ec57ac1c3c An stdcall function calling a non-stdcall function 
cannot use tailcall.  PR 8461.

llvm-svn: 117322
 2010-10-25 22:17:05 +00:00
Owen Anderson 1f6aad053d Add correct encodings for NEON vabal. 
llvm-svn: 117315
 2010-10-25 21:29:04 +00:00
Owen Anderson b9c91679aa Add correct NEON encodings for vaba. 
llvm-svn: 117309
 2010-10-25 20:52:57 +00:00
Owen Anderson dd001b89d7 Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment. 
llvm-svn: 117294
 2010-10-25 20:17:22 +00:00
Owen Anderson dea09c7564 Provide correct NEON encodings for vbsl. 
llvm-svn: 117293
 2010-10-25 20:13:13 +00:00
Jim Grosbach e6fe1a03c7 imm12 operands aren't Thumb2 only, so rename the printer helper function. 
llvm-svn: 117291
 2010-10-25 20:00:01 +00:00
Owen Anderson 2477446ee5 Add correct instruction encodings for vbic, vorn, and vmvn. 
llvm-svn: 117282
 2010-10-25 18:43:52 +00:00
Rafael Espindola 752913d6ba Add a virtual destructor. 
llvm-svn: 117280
 2010-10-25 18:38:32 +00:00
Owen Anderson dff239c5f9 Provide correct NEON encodings for vand, veor, and vorr. 
llvm-svn: 117279
 2010-10-25 18:28:30 +00:00
Owen Anderson feb3ee0c93 Add NEON encoding tests for vcgt and vacgt. 
llvm-svn: 117276
 2010-10-25 18:03:59 +00:00
Rafael Espindola 0ed1543d4e Add support for emitting ARM file attributes. 
llvm-svn: 117275
 2010-10-25 17:50:35 +00:00
Owen Anderson e5d0677173 Add tests for NEON encodings of vcge and vacge. 
llvm-svn: 117274
 2010-10-25 17:49:32 +00:00
Owen Anderson c178b80f65 Add a warning about our inability to test the encoding of vceq with immediate zero. 
llvm-svn: 117273
 2010-10-25 17:33:02 +00:00
Rafael Espindola 800fd3533c Add X86::reloc_global_offset_table and use it to have a single place where 
we check for _GLOBAL_OFFSET_TABLE_.

llvm-svn: 117241
 2010-10-24 17:35:42 +00:00
Eric Christopher c9616f26bd Move rejection of NEON parameters earlier in fast isel call processing, 
note that we can actually handle some f64 arguments.

llvm-svn: 117209
 2010-10-23 09:37:17 +00:00
Benjamin Kramer de0a4fbf3b Make the disassembler tables const so they end up in read-only memory. 
llvm-svn: 117206
 2010-10-23 09:10:44 +00:00
Michael J. Spencer aa19ee17c0 X86: Emit _fltused instead of __fltused on Windows x64. 
llvm-svn: 117205
 2010-10-23 09:06:59 +00:00
Chandler Carruth 82058c05f8 Move the remaining attribute macros to systematic names based on the attribute 
name and prefixed with 'LLVM_'.

llvm-svn: 117203
 2010-10-23 08:40:19 +00:00
Chandler Carruth 9873c9039e Remove a define which is never referenced. 
llvm-svn: 117202
 2010-10-23 08:25:16 +00:00
Chandler Carruth 88c54b82c1 Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names 
until other LLVM projects using these are cleaned up.

llvm-svn: 117200
 2010-10-23 08:10:43 +00:00
Evan Cheng 817bbac4f7 Enable ARM fastcc. 
llvm-svn: 117194
 2010-10-23 02:19:37 +00:00
Evan Cheng ad79526471 Latency between CPSR def and branch is zero. 
llvm-svn: 117192
 2010-10-23 02:04:38 +00:00
Jim Grosbach 696fe9d36c Trailing whitespace. 
llvm-svn: 117188
 2010-10-22 23:48:29 +00:00
Gabor Greif b171ca0a47 fix memory-layout assumption which only holds on little-endian systems 
llvm-svn: 117176
 2010-10-22 23:16:11 +00:00
Jim Grosbach 2c9ae05c67 ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. 
llvm-svn: 117165
 2010-10-22 22:12:16 +00:00
Evan Cheng 77a38320c7 Transfer implicit ops when forming load multiple and return instructions. 
llvm-svn: 117151
 2010-10-22 21:29:58 +00:00
Owen Anderson 9d0122af7d Add correct NEON encodings for vqdmlal. 
llvm-svn: 117134
 2010-10-22 19:35:48 +00:00
Jim Grosbach 2b80543fc2 Add the encoding information for the rest of the ARM mode multiply instructions. 
llvm-svn: 117133
 2010-10-22 19:15:30 +00:00
Owen Anderson 3d0264667f Provide correct encodings for NEON vmlal. 
llvm-svn: 117131
 2010-10-22 19:05:25 +00:00
Evan Cheng 21abfc9450 Silence compiler warnings. 
llvm-svn: 117128
 2010-10-22 18:57:05 +00:00
Owen Anderson f48719f1b5 Provide correct NEON encodings for vmla. 
llvm-svn: 117126
 2010-10-22 18:54:37 +00:00
Jim Grosbach 6956a60563 More ARM multiply instuction binary encodings. 
llvm-svn: 117121
 2010-10-22 18:35:16 +00:00
Evan Cheng 08dd8c8295 Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now. 
llvm-svn: 117119
 2010-10-22 18:23:05 +00:00
Jim Grosbach f98df0849f Parameterize a bit of ARM encoding information, simplifying some instruction 
definitions.

llvm-svn: 117114
 2010-10-22 17:42:06 +00:00
Benjamin Kramer 9192e7ab12 Make some symbols static, move classes into anonymous namespaces. 
llvm-svn: 117111
 2010-10-22 17:35:07 +00:00
Jim Grosbach 22261600a8 More ARM multiply instruction encoding information. 
llvm-svn: 117108
 2010-10-22 17:16:17 +00:00
Wesley Peck 1851090515 Making the e_machine configurable by the target backend in ELFObjectWriter. 
llvm-svn: 117099
 2010-10-22 15:52:49 +00:00
Andrew Trick edd006c1c3 Reverting r117031 to cleanup valgrind errors. 
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.

llvm-svn: 117087
 2010-10-22 03:58:29 +00:00
Eric Christopher 93bbe6599f Add some basic ret instruction support to arm fast-isel. 
llvm-svn: 117085
 2010-10-22 01:28:00 +00:00
Sean Callanan 9f6c622f88 Fixed handling of immediate operand sizes, which 
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix.  Also added
a test case for this.

llvm-svn: 117084
 2010-10-22 01:24:11 +00:00
Jim Grosbach e2ec62e252 ARM binary encoding for some of the multiply instructions. 
llvm-svn: 117080
 2010-10-21 22:52:30 +00:00
Jim Grosbach a97becfaac ARM binary encodings for MVN variants. 
llvm-svn: 117076
 2010-10-21 22:19:32 +00:00
Jim Grosbach 5edb03ee57 ARM Binary encoding information for BFC/BFI instructions. 
llvm-svn: 117072
 2010-10-21 22:03:21 +00:00
Eric Christopher 2f8637d393 These don't need to be virtual. 
llvm-svn: 117068
 2010-10-21 21:47:51 +00:00
Owen Anderson 2bfa8ed045 Move the encoding logic for Q registers into getMachineOpValue(). 
llvm-svn: 117060
 2010-10-21 20:49:13 +00:00
Owen Anderson 9e44cf2bb2 ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower 
half of the Q register), rather than with just regno.  This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.

llvm-svn: 117056
 2010-10-21 20:21:49 +00:00
Eric Christopher b353e4f579 Handle storing args to the stack for calls. 
llvm-svn: 117055
 2010-10-21 20:09:54 +00:00
Wesley Peck a7f6150c14 Adding initial AsmParser implementation for the MBlaze backend. It is 
mostly based on the ARM AsmParser at this time and is not particularly
functional.

Changed the MBlaze data layout from:
    "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32"
to:
    "E-p:32:32:32-i8:8:8-i16:16:16"
because the MicroBlaze doesn't have i64, f64, v64, or v128 data types.

Cleaned up the MBlaze source code:
    1. The floating point register class has been removed. The
       MicroBlaze does not have floating point registers. Floating
       point values are simply stored in integer registers.
    2. Renaming the CPURegs register class to GPR to reflect the
       standard naming.
    3. Removing a lot of stale code from AsmPrinter after
       the conversion to InstPrinter.
    4. Simplified sign extended loads by marking them as
       expanded in ISelLowering.

llvm-svn: 117054
 2010-10-21 19:48:38 +00:00
Eric Christopher 73bc5b0f86 More load/store refactoring, call reg+offset simplification from within 
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.

llvm-svn: 117051
 2010-10-21 19:40:30 +00:00
Jim Grosbach d37f0715b1 trailing whitespace 
llvm-svn: 117050
 2010-10-21 19:38:40 +00:00
Owen Anderson 6b7e401049 Add correct NEON encodings for vhadd and vrhadd. 
llvm-svn: 117047
 2010-10-21 18:55:04 +00:00
Owen Anderson 9561084188 Add correct encodings for NEON vaddw.s* and vaddw.u*. 
llvm-svn: 117040
 2010-10-21 18:20:25 +00:00
Owen Anderson 15c97706e8 Provide correct NEON encodings for vaddl.u* and vaddl.s*. 
llvm-svn: 117039
 2010-10-21 18:09:17 +00:00
Kevin Enderby 0138a05557 More tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler allows
for these instructions.  Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).

llvm-svn: 117031
 2010-10-21 17:16:46 +00:00
Duncan Sands b014abf3ef The return value of this call is not used, so no point 
in assigning it to a variable (gcc-4.6 warning).

llvm-svn: 117024
 2010-10-21 16:06:28 +00:00
Duncan Sands ee4eb2bad1 Remove some variables that are never really used 
(gcc-4.6 warns about these).

llvm-svn: 117021
 2010-10-21 16:03:28 +00:00
Duncan Sands 1f0d37e892 Add parentheses to pacify gcc, which warns otherwise. 
llvm-svn: 117020
 2010-10-21 16:02:12 +00:00
Wesley Peck f7ecd9e8bb Removing stale AsmPrinter directory from MicroBlaze backend. 
llvm-svn: 116998
 2010-10-21 05:05:06 +00:00
Oscar Fuentes 3e79a47a7a Deleted lib/Target/MBlaze/AsmPrinter/CMakeLists.txt. This way the 
CMake build does not try to build that library, which collides with
MBlaze/InstPrinter.

llvm-svn: 116997
 2010-10-21 05:01:26 +00:00
Wesley Peck c16f77fb27 Recommit 116986 with capitalization typo fixed. 
llvm-svn: 116993
 2010-10-21 03:57:26 +00:00
Andrew Trick f4ebec03e0 putback r116983 and fix simple-fp-encoding.ll tests 
llvm-svn: 116992
 2010-10-21 03:40:16 +00:00
Wesley Peck 078db00f1d Reverting the commit 116986. It was breaking the build on llvm-x86_64-linux though it 
compiles on OS X. I'll ensure that it builds on a linux machine before committing
again.

llvm-svn: 116991
 2010-10-21 03:34:22 +00:00
Owen Anderson 9e00f27e14 Revert r116983, which is breaking all the buildbots. 
llvm-svn: 116987
 2010-10-21 03:11:16 +00:00
Wesley Peck f608ac4db9 Major update of the MicroBlaze backend. The new features are: 
1. A delay slot filler that searches for valid instructions
       to fill the delay slot with. Previously NOPs would always
       be inserted into delay slots.
    2. Support for MC based instruction printer added.
    3. Support for MC based machine code generation and ELF
       file generation. ELF file generation does not yet
       completely work as much of the ELF support infrastructure
       is still x86/x86-64 specific.
    4. General clean up of the MBlaze backend code. Much of the
       tablegen code has been cleanup and simplified.

Bug Fixes:
    1. Removed duplicate periods from subtarget feature descriptions.
    2. Many of the instructions had bad machine code information
       in the tablegen files. Much of this has been fixed.

llvm-svn: 116986
 2010-10-21 03:09:55 +00:00
Michael J. Spencer f509c6ca27 X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424. 
llvm-svn: 116984
 2010-10-21 01:41:01 +00:00
Evan Cheng 15c2ac90ec Add missing scheduling itineraries for transfers between core registers and VFP registers. 
llvm-svn: 116983
 2010-10-21 01:12:00 +00:00
Owen Anderson 6083502848 Implement correct encodings for NEON vadd, both integer and floating point. 
llvm-svn: 116981
 2010-10-21 00:48:00 +00:00
Michael J. Spencer 83ce5f181f CodeGen-Windows: Only emit _fltused if a VarArg function is called with floating point args. 
This should be the minimum set of functions that could possibly need it.

llvm-svn: 116978
 2010-10-21 00:08:21 +00:00
Eric Christopher 4ac3ed0219 Custom lower f64 args passed in integer registers. 
llvm-svn: 116977
 2010-10-21 00:01:47 +00:00
Michael J. Spencer 9cafc872ab Fix Whitespace. 
llvm-svn: 116972
 2010-10-20 23:40:27 +00:00
Bill Wendling a65f914bb0 Add encoding for moving a value between two ARM core registers and a doublework 
extension register.

llvm-svn: 116970
 2010-10-20 23:37:40 +00:00
Bill Wendling 058190507b Add encodings for movement between ARM core registers and single-precision 
registers.

llvm-svn: 116961
 2010-10-20 22:44:54 +00:00
Dale Johannesen ff37675c72 Fix crash introduced in 116852. 8573915. 
llvm-svn: 116955
 2010-10-20 22:03:37 +00:00
Dale Johannesen 320a553319 Remove Synthesizable from the Type system; as MMX vector 
types are no longer Legal on X86, we don't need it.
No functional change.  8499854.

llvm-svn: 116947
 2010-10-20 21:32:10 +00:00
Rafael Espindola 89f6613e76 Handle _GLOBAL_OFFSET_TABLE_ correctly. 
llvm-svn: 116932
 2010-10-20 16:46:08 +00:00
Chandler Carruth 1898262a33 Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three 
#includes in the process.

llvm-svn: 116919
 2010-10-20 08:27:02 +00:00
Eric Christopher af719ef86b Fix a TODO by removing some unnecesary copies. 
llvm-svn: 116915
 2010-10-20 08:02:24 +00:00
Jim Grosbach 723159ef77 Fix backwards conditional. 
llvm-svn: 116897
 2010-10-20 01:10:01 +00:00
Jim Grosbach cb6fc2b2de Add dynamic realignment when rematerializing the base register. 
llvm-svn: 116886
 2010-10-20 00:02:50 +00:00
Jim Grosbach f99ee7cd91 Nuke a commented out bit that got missed a while back. 
llvm-svn: 116883
 2010-10-19 23:48:47 +00:00
Jim Grosbach bbdc5d2ef9 Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any 
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268

llvm-svn: 116879
 2010-10-19 23:27:08 +00:00
Jim Grosbach 3ed6338ff2 Update comments to remove obsolete references. 
llvm-svn: 116863
 2010-10-19 21:34:47 +00:00
Dale Johannesen 710a2d9d46 Enable using vdup for vector constants which are splat of 
integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's.  8003375.

llvm-svn: 116852
 2010-10-19 20:00:17 +00:00
Evan Cheng 63c7608c34 Re-enable register pressure aware machine licm with fixes. Hoist() may have 
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.

llvm-svn: 116845
 2010-10-19 18:58:51 +00:00
Owen Anderson 6c18d1aac0 Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 
must be called in the pass's constructor.  This function uses static dependency declarations to recursively initialize
the pass's dependencies.

Clients that only create passes through the createFooPass() APIs will require no changes.  Clients that want to use the
CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h
before parsing commandline arguments.

I have tested this with all standard configurations of clang and llvm-gcc on Darwin.  It is possible that there are problems
with the static dependencies that will only be visible with non-standard options.  If you encounter any crash in pass
registration/creation, please send the testcase to me directly.

llvm-svn: 116820
 2010-10-19 17:21:58 +00:00
Daniel Dunbar 418204e523 Revert r116781 "- Add a hook for target to determine whether an instruction def 
is", which breaks some nightly tests.

llvm-svn: 116816
 2010-10-19 17:14:24 +00:00
Che-Liang Chiou 05046a177d Add lower argument and return of device function 
llvm-svn: 116805
 2010-10-19 13:14:40 +00:00
Michael J. Spencer 3e64de9504 X86: Add MS-CRT libcalls. 
llvm-svn: 116801
 2010-10-19 07:32:52 +00:00
Michael J. Spencer 8b382e7e10 Fix Whitespace. 
llvm-svn: 116800
 2010-10-19 07:32:42 +00:00
Evan Cheng 8249dfe6ce - Add a hook for target to determine whether an instruction def is 
"long latency" enough to hoist even if it may increase spilling. Reloading
  a value from spill slot is often cheaper than performing an expensive
  computation in the loop. For X86, that means machine LICM will hoist
  SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
  instructions.
- Enable register pressure aware machine LICM by default.

llvm-svn: 116781
 2010-10-19 00:55:07 +00:00
Bob Wilson b6d61dc291 Support alignment for NEON vld-lane and vst-lane instructions. 
llvm-svn: 116776
 2010-10-19 00:16:32 +00:00
Kevin Enderby 49843c0162 Added a few tweaks to the Intel Descriptor-table support instructions to allow 
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes.  This is again for use just with assembly source for llvm-mc .

llvm-svn: 116773
 2010-10-19 00:01:44 +00:00