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11995 Commits

Author SHA1 Message Date
Dan Gohman d16aa541af SelectionDAG shouldn't have a FunctionLoweringInfo member. RegsForValue 
shouldn't have a TargetLoweringInfo member. And FunctionLoweringInfo::set
doesn't needs its EnableFastISel argument.

llvm-svn: 105101
 2010-05-29 17:03:36 +00:00
Nick Lewycky 04a21441a7 Fix typo. 
llvm-svn: 105096
 2010-05-29 06:11:16 +00:00
Dan Gohman 0d7f3b8195 Split the logic behind CastInst::isNoopCast into a separate static function, 
as is done with most other cast opcode predicates.

llvm-svn: 105008
 2010-05-28 21:41:37 +00:00
Dan Gohman d1d96c2c7c Fix a comment; vectors are not a special case here. 
llvm-svn: 105006
 2010-05-28 21:22:45 +00:00
Jakob Stoklund Olesen 64824ea99f Add a TargetRegisterInfo::composeSubRegIndices hook with a default 
implementation that is correct for most targets. Tablegen will override where
needed.

Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing
subreg indices when sustituting registers.

llvm-svn: 104985
 2010-05-28 18:18:53 +00:00
Dan Gohman 826bdf8c10 Move FindAvailableLoadedValue isSafeToLoadUnconditionally out of 
lib/Transforms/Utils and into lib/Analysis so that Analysis passes
can use them.

llvm-svn: 104949
 2010-05-28 16:19:17 +00:00
Dan Gohman 4412c9c551 Fix a comment. 
llvm-svn: 104947
 2010-05-28 16:06:09 +00:00
Jakob Stoklund Olesen b613ae2c89 Add a -regalloc=default option that chooses a register allocator based on the -O 
optimization level.

This only really affects llc for now because both the llvm-gcc and clang front
ends override the default register allocator. I intend to remove that code later.

llvm-svn: 104904
 2010-05-27 23:57:25 +00:00
Jakob Stoklund Olesen 775ec12b72 Remove ancient prototype. 
llvm-svn: 104903
 2010-05-27 23:57:19 +00:00
Jim Grosbach c9f532dddc back out 104862/104869. Can reuse stacksave after all. Very cool. 
llvm-svn: 104897
 2010-05-27 23:11:57 +00:00
Dan Gohman caf0ab658d Make ParseIRFile and getLazyIRFileModule incoporate the underlying 
error message string into their own error message string, so that
the information isn't lost.

llvm-svn: 104887
 2010-05-27 20:47:38 +00:00
Dan Gohman d9225cee20 Don't special-case stdout in llvm::WriteBitcodeToFile; just consider 
it to be the caller's responsibility to provide a stream in binary
mode. This fixes a layering violation and avoids an outs() call.

llvm-svn: 104878
 2010-05-27 20:06:51 +00:00
Jim Grosbach b68dfb45f5 hook ISD::STACKADDR to an intrinsic 
llvm-svn: 104869
 2010-05-27 18:52:11 +00:00
Jim Grosbach 5cde219fb1 add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH 
to update the jmpbuf in the presence of VLAs.

llvm-svn: 104862
 2010-05-27 18:23:48 +00:00
Dan Gohman c36b1f35f0 Add basic error checking to MemoryBuffer::getSTDIN. 
llvm-svn: 104855
 2010-05-27 17:31:51 +00:00
Jim Grosbach 9b253e6518 remove incorrect GCCBuiltin<> usage 
llvm-svn: 104833
 2010-05-27 15:04:02 +00:00
Gabor Greif b50c58a792 typo 
llvm-svn: 104832
 2010-05-27 09:48:47 +00:00
Dan Gohman 084bcb1322 Fix Lint printing warnings multiple times. Remove the ErrorStr 
option from lintModule, which was an artifact from being
based on Verifier code.

llvm-svn: 104765
 2010-05-26 22:28:53 +00:00
Daniel Dunbar b33dfbcba4 MC: Add TargetMachine support for setting the value of MCRelaxAll with 
-filetype=obj.

llvm-svn: 104747
 2010-05-26 21:48:55 +00:00
Jakob Stoklund Olesen d1d7ed63ff Add StringRef::compare_numeric and use it to sort TableGen register records. 
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

llvm-svn: 104745
 2010-05-26 21:47:28 +00:00
Jim Grosbach c98892fdaa Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in 
ISD::. No functional change.

llvm-svn: 104734
 2010-05-26 20:22:18 +00:00
Bill Wendling 0c3bfd3fb0 Move the check for "calls setjmp" to SelectionDAGISel so that it can be used by 
more than just the stack slot coloring algorithm.

llvm-svn: 104722
 2010-05-26 19:46:12 +00:00
Dan Gohman 52c2738324 Eliminate the use of PriorityQueue and just use a std::vector, 
implementing pop with a linear search for a "best" element. The priority
queue was a neat idea, but in practice the comparison functions depend
on dynamic information.

llvm-svn: 104718
 2010-05-26 18:52:00 +00:00
Dan Gohman b3807452fe Fix indentation. 
llvm-svn: 104717
 2010-05-26 18:37:48 +00:00
Daniel Dunbar 7c8bd0fc98 MC: Change RelaxInstruction to only take the input and output instructions. 
llvm-svn: 104713
 2010-05-26 18:15:06 +00:00
Daniel Dunbar a19838e107 MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it 
before encoding.

llvm-svn: 104707
 2010-05-26 17:45:29 +00:00
Jakob Stoklund Olesen 7de379467e Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704
 2010-05-26 17:27:12 +00:00
Daniel Dunbar b34440a6a8 MC: Eliminate MCAsmFixup, replace with MCFixup. 
llvm-svn: 104699
 2010-05-26 15:18:56 +00:00
Daniel Dunbar 4f2bae4f7d MC: Simplify MCFixup and increase the available offset size. 
llvm-svn: 104698
 2010-05-26 15:18:40 +00:00
Daniel Dunbar 353a91ff76 MC: Use accessors for access to MCAsmFixup. 
llvm-svn: 104697
 2010-05-26 15:18:31 +00:00
Daniel Dunbar 870e5759e7 MC: Eliminate MCFragment vtable, which was unnecessary. 
llvm-svn: 104689
 2010-05-26 06:50:57 +00:00
Eric Christopher e805ea9e39 Temporarily revert r104655 as it's breaking the bots. 
llvm-svn: 104664
 2010-05-26 01:59:55 +00:00
Jakob Stoklund Olesen 50eec620f4 Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." 
This reverts commit 104654.

llvm-svn: 104660
 2010-05-26 01:21:14 +00:00
Dan Gohman 7c00576a62 Change push_all to a non-virtual function and implement it in the 
base class, since all the implementations are the same.

llvm-svn: 104659
 2010-05-26 01:10:55 +00:00
Dan Gohman 5112aea14d Delete an unused function. 
llvm-svn: 104658
 2010-05-26 00:56:27 +00:00
Bill Wendling c5222d6c38 Dale and Evan suggested putting the "check for setjmp" much earlier in the 
machine code generation. That's a good idea, so I made it so.

llvm-svn: 104655
 2010-05-26 00:32:40 +00:00
Jakob Stoklund Olesen 0b0274524c Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654
 2010-05-26 00:28:19 +00:00
Eric Christopher e7b64dcc1e Start adding mach-o tls reloc support. 
llvm-svn: 104651
 2010-05-26 00:02:12 +00:00
Jakob Stoklund Olesen 66c939a2ca Drop the SuperregHashTable. It is essentially the same as SubregHashTable. 
llvm-svn: 104650
 2010-05-25 23:43:18 +00:00
Jakob Stoklund Olesen 1ad0d5e25b Print symbolic SubRegIndex names on machine operands. 
llvm-svn: 104628
 2010-05-25 19:49:38 +00:00
Jakob Stoklund Olesen 673e7e0f37 Remove NumberHack entirely. 
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

llvm-svn: 104627
 2010-05-25 19:49:33 +00:00
Eric Christopher f6562d35ac Make sure aeskeygenassist uses an unsigned immediate field. 
Fixes rdar://8017638

llvm-svn: 104617
 2010-05-25 17:33:22 +00:00
Jakob Stoklund Olesen fdb25de17e Switch SubRegSet to using symbolic SubRegIndices 
llvm-svn: 104571
 2010-05-24 23:03:18 +00:00
Jakob Stoklund Olesen edab242488 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data 
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563
 2010-05-24 21:46:58 +00:00
Evan Cheng 1b79babdec Avoid adding duplicate function live-in's. 
llvm-svn: 104560
 2010-05-24 21:33:37 +00:00
Jakob Stoklund Olesen 1c69646e99 Add the SubRegIndex TableGen class. 
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

llvm-svn: 104492
 2010-05-24 14:48:12 +00:00
Daniel Dunbar 3ff1a06de6 MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches. 
llvm-svn: 104463
 2010-05-23 17:44:06 +00:00
Daniel Dunbar 346782c12c tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one. 
llvm-svn: 104452
 2010-05-22 21:02:29 +00:00
John Mosby 987a1576d2 Trivial change to dump() function for SparseBitVector 
llvm-svn: 104433
 2010-05-22 05:13:17 +00:00
Evan Cheng 168ced94d8 Implement @llvm.returnaddress. rdar://8015977. 
llvm-svn: 104421
 2010-05-22 01:47:14 +00:00