Commit Graph

7 Commits

Author SHA1 Message Date
Krzysztof Parzyszek 5bb417bed2 [Hexagon] Handle block live-ins with lane masks in HexagonBlockRanges
llvm-svn: 284522
2016-10-18 19:47:20 +00:00
David Majnemer 42531260b3 Use the range variant of find/find_if instead of unpacking begin/end
If the result of the find is only used to compare against end(), just
use is_contained instead.

No functionality change is intended.

llvm-svn: 278469
2016-08-12 03:55:06 +00:00
Benjamin Kramer 922efd7a67 [hexagon] Move BlockRanges and RDF stuff into the llvm namespace.
No functional change intended.

llvm-svn: 270980
2016-05-27 10:06:40 +00:00
Krzysztof Parzyszek c06e79356f [Hexagon] Properly close live range in HexagonBlockRanges
llvm-svn: 267173
2016-04-22 17:27:22 +00:00
Mehdi Amini b550cb1750 [NFC] Header cleanup
Removed some unused headers, replaced some headers with forward class declarations.

Found using simple scripts like this one:
clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap'

Patch by Eugene Kosov <claprix@yandex.ru>

Differential Revision: http://reviews.llvm.org/D19219

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 266595
2016-04-18 09:17:29 +00:00
Alexey Samsonov 7217d27ee6 Fix Windows buildbot breakage.
llvm-svn: 260766
2016-02-12 23:51:06 +00:00
Krzysztof Parzyszek 7793ddb043 [Hexagon] Optimize stack slot spills
Replace spills to memory with spills to registers, if possible. This
applies mostly to predicate registers (both scalar and vector), since
they are very limited in number. A spill of a predicate register may
happen even if there is a general-purpose register available. In cases
like this the stack spill/reload may be eliminated completely.

This optimization will consider all stack objects, regardless of where
they came from and try to match the live range of the stack slot with
a dead range of a register from an appropriate register class.

llvm-svn: 260758
2016-02-12 22:53:35 +00:00