ecb1dafd3d
Turn of jump tables for a bit, there are still some issues to work out with
...
updating the machine CFG.
llvm-svn: 27949
2006-04-22 23:51:56 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
b21d3bfd1f
The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrap
...
miscompares). Switch RISC targets to use the list-td scheduler, which isn't.
llvm-svn: 27933
2006-04-21 17:16:16 +00:00
662e940f73
Fix a couple more memory issues
...
llvm-svn: 27930
2006-04-21 15:32:26 +00:00
cc47ab3305
Fix a really subtle and obnoxious memory bug that caused issues with an
...
llvm-gcc4 boostrap. Whenever a node is deleted by the dag combiner, it
*must* be returned by the visit function, or the dag combiner will not
know that the node has been processed (and will, e.g., send it to the
target dag combine xforms).
llvm-svn: 27922
2006-04-20 23:55:59 +00:00
dcc1f995eb
This field no longer exists
...
llvm-svn: 27899
2006-04-20 18:32:41 +00:00
a38c3580bd
Remove some of the obvious V9-specific cruft
...
llvm-svn: 27893
2006-04-20 18:08:53 +00:00
a320abc494
Turn a VAND into a VECTOR_SHUFFLE is applicable.
...
DAG combiner can turn a VAND V, <-1, 0, -1, -1>, i.e. vector clear elements,
into a vector shuffle with a zero vector. It only does so when TLI tells it
the xform is profitable.
llvm-svn: 27874
2006-04-20 08:56:16 +00:00
bc1b262725
Implement folding of a bunch of binops with undef
...
llvm-svn: 27863
2006-04-20 05:39:12 +00:00
73eb58e1a2
Simplify some code
...
llvm-svn: 27846
2006-04-19 23:17:50 +00:00
916ae0775e
Fix handling of calls in functions that use vectors. This fixes a crash on
...
the code in GCC PR26546.
llvm-svn: 27780
2006-04-17 22:10:08 +00:00
bec79b4a59
Add a MachineInstr::eraseFromParent convenience method.
...
llvm-svn: 27775
2006-04-17 21:35:41 +00:00
326870b40b
Codegen insertelement with constant insertion points as scalar_to_vector
...
and a shuffle. For this:
void %test2(<4 x float>* %F, float %f) {
%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
%tmp3 = add <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
%tmp2 = insertelement <4 x float> %tmp3, float %f, uint 2 ; <<4 x float>> [#uses=2]
%tmp6 = add <4 x float> %tmp2, %tmp2 ; <<4 x float>> [#uses=1]
store <4 x float> %tmp6, <4 x float>* %F
ret void
}
we now get this on X86 (which will get better):
_test2:
movl 4(%esp), %eax
movaps (%eax), %xmm0
addps %xmm0, %xmm0
movaps %xmm0, %xmm1
shufps $3, %xmm1, %xmm1
movaps %xmm0, %xmm2
shufps $1, %xmm2, %xmm2
unpcklps %xmm1, %xmm2
movss 8(%esp), %xmm1
unpcklps %xmm1, %xmm0
unpcklps %xmm2, %xmm0
addps %xmm0, %xmm0
movaps %xmm0, (%eax)
ret
instead of:
_test2:
subl $28, %esp
movl 32(%esp), %eax
movaps (%eax), %xmm0
addps %xmm0, %xmm0
movaps %xmm0, (%esp)
movss 36(%esp), %xmm0
movss %xmm0, 8(%esp)
movaps (%esp), %xmm0
addps %xmm0, %xmm0
movaps %xmm0, (%eax)
addl $28, %esp
ret
llvm-svn: 27765
2006-04-17 19:21:01 +00:00
91226e5799
Add support for promoting stores from one legal type to another, allowing us
...
to write one pattern for vector stores instead of 4.
llvm-svn: 27730
2006-04-16 01:36:45 +00:00
7e7ad593cc
Make these predicates return true for bit_convert(buildvector)'s as well as
...
buildvectors.
llvm-svn: 27723
2006-04-15 23:38:00 +00:00
086e986e94
Make this assertion better
...
llvm-svn: 27695
2006-04-14 06:08:35 +00:00
709eaacb36
Expand some code with temporary variables to rid ourselves of the warning
...
about "dereferencing type-punned pointer will break strict-aliasing rules"
llvm-svn: 27671
2006-04-13 18:29:58 +00:00
119266ea92
Promote vector AND, OR, and XOR
...
llvm-svn: 27632
2006-04-12 21:20:24 +00:00
be8a8933e6
Vector type promotion for ISD::LOAD and ISD::SELECT
...
llvm-svn: 27606
2006-04-12 16:33:18 +00:00
d3b504ae10
Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload
...
llvm-svn: 27604
2006-04-12 16:20:43 +00:00
417b96b6dd
Don't memoize vloads in the load map! Don't memoize them anywhere here, let
...
getNode do it. This fixes CodeGen/Generic/2006-04-11-vecload.ll
llvm-svn: 27602
2006-04-12 03:25:41 +00:00
7256b0ae05
Only get Tmp2 for cases where number of operands is > 1. Fixed return void.
...
llvm-svn: 27586
2006-04-11 06:33:39 +00:00
6cf3bbbe17
add some todos
...
llvm-svn: 27580
2006-04-11 02:00:08 +00:00
2eb22eef7d
Add basic support for legalizing returns of vectors
...
llvm-svn: 27578
2006-04-11 01:31:51 +00:00
dca2655daa
Use existing information.
...
llvm-svn: 27574
2006-04-10 23:09:19 +00:00
cb73b8d419
Missing break
...
llvm-svn: 27559
2006-04-10 18:54:36 +00:00
02274a5265
Add code generator support for VSELECT
...
llvm-svn: 27542
2006-04-08 22:22:57 +00:00
e1401e3610
Canonicalize vvector_shuffle(x,x) -> vvector_shuffle(x,undef) to enable patterns
...
to match again :)
llvm-svn: 27533
2006-04-08 05:34:25 +00:00
098c01e94e
Codegen shufflevector as VVECTOR_SHUFFLE
...
llvm-svn: 27529
2006-04-08 04:15:24 +00:00
101ea66813
add a sanity check: LegalizeOp should return a value that is the same type
...
as its input.
llvm-svn: 27528
2006-04-08 04:13:17 +00:00
78e3d565af
INSERT_VECTOR_ELT lowering bug:
...
store vector to $esp
store element to $esp + sizeof(VT) * index
load vector from $esp
The bug is VT is the type of the vector element, not the type of the vector!
llvm-svn: 27517
2006-04-08 01:46:37 +00:00
aa3185f12e
Stub out shufflevector
...
llvm-svn: 27514
2006-04-08 01:19:25 +00:00
7d4592733c
Remove section change in function end, preventing override of function's real
...
section.
llvm-svn: 27503
2006-04-08 00:35:59 +00:00
c0d6518f27
Make sure that debug labels are defined within the same section and after the
...
entry point of a function.
llvm-svn: 27494
2006-04-07 20:44:42 +00:00
2d7298c362
Foundation for call frame information.
...
llvm-svn: 27491
2006-04-07 16:34:46 +00:00
613996c55e
1. If both vector operands of a vector_shuffle are undef, turn it into an undef.
...
2. A shuffle mask element can also be an undef.
llvm-svn: 27472
2006-04-06 23:20:43 +00:00
4a2413a590
Make a vector live across blocks have the correct Vec type. This fixes
...
CodeGen/X86/2006-04-04-CrossBlockCrash.ll
llvm-svn: 27436
2006-04-05 06:54:42 +00:00
9fa8959dce
Exapnd a VECTOR_SHUFFLE to a BUILD_VECTOR if target asks for it to be expanded
...
or custom lowering fails.
llvm-svn: 27432
2006-04-05 06:07:11 +00:00
4ea52cac01
Do not create ZEXTLOAD's unless we are before legalize or the operation is
...
legal.
llvm-svn: 27402
2006-04-04 17:39:18 +00:00
6be79823e7
* Add supprot for SCALAR_TO_VECTOR operations where the input needs to be
...
promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC).
* Add support for targets to request that VECTOR_SHUFFLE nodes be promoted
to a canonical type, for example, we only want v16i8 shuffles on PPC.
* Move isShuffleLegal out of TLI into Legalize.
* Teach isShuffleLegal to allow shuffles that need to be promoted.
llvm-svn: 27399
2006-04-04 17:23:26 +00:00
a9e77d14c7
Constant fold bitconvert(undef)
...
llvm-svn: 27391
2006-04-04 01:02:22 +00:00
b710a81e54
The stack alignment is now computed dynamically, just verify it is correct.
...
llvm-svn: 27380
2006-04-03 21:39:57 +00:00
6bc4b9c7f8
Remove unused method
...
llvm-svn: 27379
2006-04-03 21:39:03 +00:00
e1e3adf802
Add a missing check, this fixes UnitTests/Vector/sumarray.c
...
llvm-svn: 27375
2006-04-03 17:29:28 +00:00
04c00fc844
Add a missing check, which broke a bunch of vector tests.
...
llvm-svn: 27374
2006-04-03 17:21:50 +00:00
94f012f606
back this out
...
llvm-svn: 27367
2006-04-03 03:16:50 +00:00
015eaf5f33
This should be a win of every arch
...
llvm-svn: 27364
2006-04-02 21:42:45 +00:00
4993249a04
Add a little dag combine to compile this:
...
int %AreSecondAndThirdElementsBothNegative(<4 x float>* %in) {
entry:
%tmp1 = load <4 x float>* %in ; <<4 x float>> [#uses=1]
%tmp = tail call int %llvm.ppc.altivec.vcmpgefp.p( int 1, <4 x float> < float 0x7FF8000000000000, float 0.000000e+00, float 0.000000e+00, float 0x7FF8000000000000 >, <4 x float> %tmp1 ) ; <int> [#uses=1]
%tmp = seteq int %tmp, 0 ; <bool> [#uses=1]
%tmp3 = cast bool %tmp to int ; <int> [#uses=1]
ret int %tmp3
}
into this:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
lvx v0, 0, r3
lvx v1, r5, r4
vcmpgefp. v0, v1, v0
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
mtspr 256, r2
blr
instead of this:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
lvx v0, 0, r3
lvx v1, r5, r4
vcmpgefp. v0, v1, v0
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
xori r3, r3, 1
cntlzw r3, r3
srwi r3, r3, 5
mtspr 256, r2
blr
llvm-svn: 27356
2006-04-02 06:11:11 +00:00
42a5fca47e
Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to work with PowerPC.
...
llvm-svn: 27349
2006-04-02 05:06:04 +00:00
87f080949b
Implement the Expand action for binary vector operations to break the binop
...
into elements and operate on each piece. This allows generic vector integer
multiplies to work on PPC, though the generated code is horrible.
llvm-svn: 27347
2006-04-02 03:57:31 +00:00
a9c59156be
Intrinsics that just load from memory can be treated like loads: they don't
...
have to serialize against each other. This allows us to schedule lvx's
across each other, for example.
llvm-svn: 27346
2006-04-02 03:41:14 +00:00
0442a18758
Constant fold all of the vector binops. This allows us to compile this:
...
"vector unsigned char mergeLowHigh = (vector unsigned char)
( 8, 9, 10, 11, 16, 17, 18, 19, 12, 13, 14, 15, 20, 21, 22, 23 );
vector unsigned char mergeHighLow = vec_xor( mergeLowHigh, vec_splat_u8(8));"
aka:
void %test2(<16 x sbyte>* %P) {
store <16 x sbyte> cast (<4 x int> xor (<4 x int> cast (<16 x ubyte> < ubyte 8, ubyte 9, ubyte 10, ubyte 11, ubyte 16, ubyte 17, ubyte 18, ubyte 19, ubyte 12, ubyte 13, ubyte 14, ubyte 15, ubyte 20, ubyte 21, ubyte 22, ubyte 23 > to <4 x int>), <4 x int> cast (<16 x sbyte> < sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8 > to <4 x int>)) to <16 x sbyte>), <16 x sbyte> * %P
ret void
}
into this:
_test2:
mfspr r2, 256
oris r4, r2, 32768
mtspr 256, r4
li r4, lo16(LCPI2_0)
lis r5, ha16(LCPI2_0)
lvx v0, r5, r4
stvx v0, 0, r3
mtspr 256, r2
blr
instead of this:
_test2:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI2_0)
lis r5, ha16(LCPI2_0)
vspltisb v0, 8
lvx v1, r5, r4
vxor v0, v1, v0
stvx v0, 0, r3
mtspr 256, r2
blr
... which occurs here:
http://developer.apple.com/hardware/ve/calcspeed.html
llvm-svn: 27343
2006-04-02 03:25:57 +00:00
ef598059f2
Add a new -view-legalize-dags command line option
...
llvm-svn: 27342
2006-04-02 03:07:27 +00:00
e4e64b6b85
Implement constant folding of bit_convert of arbitrary constant vbuild_vector nodes.
...
llvm-svn: 27341
2006-04-02 02:53:43 +00:00
1c22728787
These entries already exist
...
llvm-svn: 27340
2006-04-02 02:51:27 +00:00
1985e1cbb8
Add some missing node names
...
llvm-svn: 27339
2006-04-02 02:41:18 +00:00
bec582f4cd
Prefer larger register classes over smaller ones when a register occurs in
...
multiple register classes. This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll
llvm-svn: 27334
2006-04-02 00:24:45 +00:00
39dcf1a9e2
Delete identity shuffles, implementing CodeGen/Generic/vector-identity-shuffle.ll
...
llvm-svn: 27317
2006-03-31 22:16:43 +00:00
d9e4daabd2
Do not endian swap split vector loads. This fixes UnitTests/Vector/sumarray-dbl on PPC.
...
Now all UnitTests/Vector/* tests pass on PPC.
llvm-svn: 27299
2006-03-31 18:22:37 +00:00
8d90f526d7
Do not endian swap the operands to a store if the operands came from a vector.
...
This fixes UnitTests/Vector/simple.c with altivec.
llvm-svn: 27298
2006-03-31 18:20:46 +00:00
7e30af3887
Remove dead *extloads. This allows us to codegen vector.ll:test_extract_elt
...
to:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 12, r32
;;
ldfs f8 = [r8]
mov ar.pfs = r3
br.ret.sptk.many rp
instead of:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 28, r32
adds r9 = 24, r32
adds r10 = 20, r32
adds r11 = 16, r32
;;
ldfs f6 = [r8]
;;
ldfs f6 = [r9]
adds r8 = 12, r32
adds r9 = 8, r32
adds r14 = 4, r32
;;
ldfs f6 = [r10]
;;
ldfs f6 = [r11]
ldfs f8 = [r8]
;;
ldfs f6 = [r9]
;;
ldfs f6 = [r14]
;;
ldfs f6 = [r32]
mov ar.pfs = r3
br.ret.sptk.many rp
llvm-svn: 27297
2006-03-31 18:10:41 +00:00
2d8551c85b
Delete dead loads in the dag. This allows us to compile
...
vector.ll:test_extract_elt2 into:
_test_extract_elt2:
lfd f1, 32(r3)
blr
instead of:
_test_extract_elt2:
lfd f0, 56(r3)
lfd f0, 48(r3)
lfd f0, 40(r3)
lfd f1, 32(r3)
lfd f0, 24(r3)
lfd f0, 16(r3)
lfd f0, 8(r3)
lfd f0, 0(r3)
blr
llvm-svn: 27296
2006-03-31 18:06:18 +00:00
6f42325dca
Implement PromoteOp for VEXTRACT_VECTOR_ELT. Thsi fixes
...
Generic/vector.ll:test_extract_elt on non-sse X86 systems.
llvm-svn: 27294
2006-03-31 17:55:51 +00:00
8e1fcab2bc
Scalarized vector stores need not be legal, e.g. if the vector element type
...
needs to be promoted or expanded. Relegalize the scalar store once created.
This fixes CodeGen/Generic/vector.ll:test1 on non-SSE x86 targets.
llvm-svn: 27293
2006-03-31 17:37:22 +00:00
ba38035e21
Make sure to pass enough values to phi nodes when we are dealing with
...
decimated vectors. This fixes UnitTests/Vector/sumarray-dbl.c
llvm-svn: 27280
2006-03-31 02:12:18 +00:00
5fe1f54c17
Significantly improve handling of vectors that are live across basic blocks,
...
handling cases where the vector elements need promotion, expansion, and when
the vector type itself needs to be decimated.
llvm-svn: 27278
2006-03-31 02:06:56 +00:00
168e45b0b3
Expand INSERT_VECTOR_ELT to store vec, sp; store elt, sp+k; vec = load sp;
...
llvm-svn: 27274
2006-03-31 01:27:51 +00:00
67271869a8
Bug fixes: handle constantexpr insert/extract element operations
...
Handle constantpacked vectors with constantexpr elements.
This fixes CodeGen/Generic/vector-constantexpr.ll
llvm-svn: 27241
2006-03-29 00:11:43 +00:00
20e619fba3
When building a VVECTOR_SHUFFLE node from extract_element operations, make
...
sure to build it as SHUFFLE(X, undef, mask), not SHUFFLE(X, X, mask).
The later is not canonical form, and prevents the PPC splat pattern from
matching. For a particular splat, we go from generating this:
li r10, lo16(LCPI1_0)
lis r11, ha16(LCPI1_0)
lvx v3, r11, r10
vperm v3, v2, v2, v3
to generating:
vspltw v3, v2, 3
llvm-svn: 27236
2006-03-28 22:19:47 +00:00
a46dfe80c8
Canonicalize VECTOR_SHUFFLE(X, X, Y) -> VECTOR_SHUFFLE(X,undef,Y')
...
llvm-svn: 27235
2006-03-28 22:11:53 +00:00
c9992548fc
Turn a series of extract_element's feeding a build_vector into a
...
vector_shuffle node. For this:
void test(__m128 *res, __m128 *A, __m128 *B) {
*res = _mm_unpacklo_ps(*A, *B);
}
we now produce this code:
_test:
movl 8(%esp), %eax
movaps (%eax), %xmm0
movl 12(%esp), %eax
unpcklps (%eax), %xmm0
movl 4(%esp), %eax
movaps %xmm0, (%eax)
ret
instead of this:
_test:
subl $76, %esp
movl 88(%esp), %eax
movaps (%eax), %xmm0
movaps %xmm0, (%esp)
movaps %xmm0, 32(%esp)
movss 4(%esp), %xmm0
movss 32(%esp), %xmm1
unpcklps %xmm0, %xmm1
movl 84(%esp), %eax
movaps (%eax), %xmm0
movaps %xmm0, 16(%esp)
movaps %xmm0, 48(%esp)
movss 20(%esp), %xmm0
movss 48(%esp), %xmm2
unpcklps %xmm0, %xmm2
unpcklps %xmm1, %xmm2
movl 80(%esp), %eax
movaps %xmm2, (%eax)
addl $76, %esp
ret
GCC produces this (with -fomit-frame-pointer):
_test:
subl $12, %esp
movl 20(%esp), %eax
movaps (%eax), %xmm0
movl 24(%esp), %eax
unpcklps (%eax), %xmm0
movl 16(%esp), %eax
movaps %xmm0, (%eax)
addl $12, %esp
ret
llvm-svn: 27233
2006-03-28 20:28:38 +00:00
f6f94d3bce
Teach Legalize how to pack VVECTOR_SHUFFLE nodes into VECTOR_SHUFFLE nodes.
...
llvm-svn: 27232
2006-03-28 20:24:43 +00:00
8d57da2ffc
new node
...
llvm-svn: 27231
2006-03-28 19:54:42 +00:00
b7163598f9
Don't crash on X^X if X is a vector. Instead, produce a vector of zeros.
...
llvm-svn: 27229
2006-03-28 19:11:05 +00:00
ffec47ebff
Add an assertion
...
llvm-svn: 27228
2006-03-28 19:04:49 +00:00
dea0348853
Refactor address attributes. Add base register to frame info.
...
llvm-svn: 27226
2006-03-28 14:58:32 +00:00
67a636c587
More bulletproofing of llvm.dbg.declare.
...
llvm-svn: 27224
2006-03-28 13:45:20 +00:00
8374e9c4eb
More bulletproofing of DebugInfoDesc verify.
...
llvm-svn: 27203
2006-03-28 01:30:18 +00:00
e55d171ccd
Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
...
llvm-svn: 27201
2006-03-28 00:40:33 +00:00
d387cc5cde
Reactivate llvm.dbg.declare.
...
llvm-svn: 27192
2006-03-27 23:31:10 +00:00
5bb1d90afd
Disable dbg_declare, it currently breaks the CFE build
...
llvm-svn: 27182
2006-03-27 21:36:03 +00:00
d5f94c9574
Fix legalization of intrinsics with chain and result values
...
llvm-svn: 27181
2006-03-27 20:28:29 +00:00
0e84f1e532
Unbreak the build on non-apple compilers :-(
...
llvm-svn: 27173
2006-03-27 16:10:59 +00:00
d09b05b0bc
Try again
...
llvm-svn: 27171
2006-03-27 08:10:26 +00:00
64efb35c32
Incorrect check for FP all one's
...
llvm-svn: 27169
2006-03-27 07:26:17 +00:00
c70e33cd6e
Change isBuildVectorAllOnesInteger to isBuildVectorAllOnes. Also check for
...
floating point cases.
llvm-svn: 27165
2006-03-27 06:58:47 +00:00
52fcad3a37
Instead of printing "INTRINSIC" on intrinsic node, print the intrinsic name.
...
llvm-svn: 27164
2006-03-27 06:45:25 +00:00
6e792f9ff8
Pass llvm/test/Regression/CodeGen/Generic/debug-info.ll.
...
llvm-svn: 27158
2006-03-27 01:51:47 +00:00
ed728c1291
SelectionDAGISel can now natively handle Switch instructions, in the same
...
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
llvm-svn: 27156
2006-03-27 01:32:24 +00:00
7092888bcc
Bullet proof against undefined args produced by upgrading ols-style debug info.
...
llvm-svn: 27155
2006-03-26 22:46:27 +00:00
84c2f0a705
How to be dumb on $5/day. Need a tri-state to track valid debug descriptors.
...
llvm-svn: 27154
2006-03-26 22:45:20 +00:00
a67899195f
Add ISD::isBuildVectorAllZeros predicate
...
llvm-svn: 27147
2006-03-26 09:50:58 +00:00
30ee72586d
Allow targets to custom lower their own intrinsics if desired.
...
llvm-svn: 27146
2006-03-26 09:12:51 +00:00
b6e2d0027a
Add some comments.
...
llvm-svn: 27133
2006-03-25 23:00:56 +00:00
f6e3b957b8
Fix a bug in ISD::isBuildVectorAllOnesInteger that caused it to always return
...
false
llvm-svn: 27131
2006-03-25 22:59:28 +00:00
c2d2811a07
Implement the ISD::isBuildVectorAllOnesInteger predicate
...
llvm-svn: 27130
2006-03-25 22:57:01 +00:00
dc1eab5886
Don't call SimplifyDemandedBits on vectors
...
llvm-svn: 27128
2006-03-25 22:19:00 +00:00
313229c74b
fix inverted conditional
...
llvm-svn: 27089
2006-03-24 22:49:42 +00:00
3324c7236f
Hack no more.
...
llvm-svn: 27079
2006-03-24 21:10:36 +00:00
68d9bf26c8
Only to vector shuffle for {x,x,y,y} cases when SCALAR_TO_VECTOR is free.
...
llvm-svn: 27071
2006-03-24 18:45:20 +00:00
53f1ecc560
Rename for truth in advertising.
...
llvm-svn: 27063
2006-03-24 09:50:27 +00:00
77e271cb4e
prefer to generate constant pool loads over splats. This prevents us from
...
using a splat for {1.0,1.0,1.0,1.0}
llvm-svn: 27055
2006-03-24 07:29:17 +00:00
87b1dddb1c
fix spello
...
llvm-svn: 27053
2006-03-24 07:15:07 +00:00
a4f6805a86
legalize vbit_convert nodes whose result is a legal type.
...
Legalize intrinsic nodes.
llvm-svn: 27036
2006-03-24 02:26:29 +00:00
d96b09a7b9
Lower target intrinsics into an INTRINSIC node
...
llvm-svn: 27035
2006-03-24 02:22:33 +00:00
6b05290922
fix some bogus assertions: noop bitconverts are legal
...
llvm-svn: 27032
2006-03-24 02:20:47 +00:00
1d2e995fc1
Lower BUILD_VECTOR to VECTOR_SHUFFLE if there are two distinct nodes (and if
...
the target can handle it). Issue two SCALAR_TO_VECTOR ops followed by a
VECTOR_SHUFFLE to select from the two vectors.
llvm-svn: 27023
2006-03-24 01:17:21 +00:00
ebac9a4adf
Identify the INTRINSIC node
...
llvm-svn: 27020
2006-03-24 01:04:30 +00:00
fb39d2a7f7
Unneeded forward.
...
llvm-svn: 27004
2006-03-23 23:05:52 +00:00
f7cfa52e7a
Make sure types are allocated in the scope of their use.
...
llvm-svn: 27002
2006-03-23 23:02:34 +00:00
d7c4e7d255
add support for splitting casts. This implements
...
CodeGen/Generic/vector.ll:test_cast_2.
llvm-svn: 26999
2006-03-23 21:16:34 +00:00
2b74656f25
Generate local variable and scope information and equivalent dwarf forms.
...
llvm-svn: 26989
2006-03-23 18:07:55 +00:00
a8bdac875d
Handle new forms of llvm.dbg intrinsics.
...
llvm-svn: 26988
2006-03-23 18:06:46 +00:00
9ea1b3f9fd
simplify some code
...
llvm-svn: 26972
2006-03-23 05:29:04 +00:00
b893d04a67
Fix a typo
...
llvm-svn: 26965
2006-03-22 22:20:49 +00:00
2f4119a608
Implement simple support for vector casting. This can currently only handle
...
casts between legal vector types.
llvm-svn: 26961
2006-03-22 20:09:35 +00:00
8fa445a89d
Endianness does not affect the order of vector fields. This fixes
...
SingleSource/UnitTests/Vector/build.c
llvm-svn: 26936
2006-03-22 01:46:54 +00:00
5be4352124
Enclose some variables in a scope to avoid error with some gcc versions
...
llvm-svn: 26934
2006-03-22 00:12:37 +00:00
340a6b5c26
add expand support for extractelement
...
llvm-svn: 26931
2006-03-21 21:02:03 +00:00
7c0cd8cafc
add some trivial support for extractelement.
...
llvm-svn: 26928
2006-03-21 20:44:12 +00:00
672a42d731
Add a hacky workaround for crashes due to vectors live across blocks.
...
Note that this code won't work for vectors that aren't legal on the
target. Improvements coming.
llvm-svn: 26925
2006-03-21 19:20:37 +00:00
21e68c8001
If a target supports splatting with SHUFFLE_VECTOR, lower to it from BUILD_VECTOR(x,x,x,x)
...
llvm-svn: 26885
2006-03-20 01:52:29 +00:00
6b20104410
TargetData doesn't know the alignment of vectors :(
...
llvm-svn: 26884
2006-03-20 01:51:46 +00:00
00f0589bc0
Add very basic support for VECTOR_SHUFFLE
...
llvm-svn: 26880
2006-03-19 23:56:04 +00:00
79fb91cc69
Allow SCALAR_TO_VECTOR to be custom lowered.
...
llvm-svn: 26867
2006-03-19 06:47:21 +00:00
9cdc5a0ce7
Add SCALAR_TO_VECTOR support
...
llvm-svn: 26866
2006-03-19 06:31:19 +00:00
eb5b2e705c
Don't bother storing undef elements of BUILD_VECTOR's
...
llvm-svn: 26858
2006-03-19 05:46:04 +00:00
5d3ff12c8f
Implement expand of BUILD_VECTOR containing variable elements.
...
This implements CodeGen/Generic/vector.ll:test_variable_buildvector
llvm-svn: 26852
2006-03-19 04:18:56 +00:00
5336a59e4b
fold insertelement(buildvector) -> buildvector if the inserted element # is
...
a constant. This implements test_constant_insert in CodeGen/Generic/vector.ll
llvm-svn: 26851
2006-03-19 01:27:56 +00:00
29b2301460
implement basic support for INSERT_VECTOR_ELT.
...
llvm-svn: 26849
2006-03-19 01:17:20 +00:00
f4e1a53647
Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR. Allow*BUILD_VECTOR to take variable inputs.
...
llvm-svn: 26847
2006-03-19 00:52:58 +00:00
c16b05e67d
implement vector.ll:test_undef
...
llvm-svn: 26845
2006-03-19 00:20:20 +00:00
93640543a9
Fix the remaining bugs in the vector expansion rework I commited yesterday.
...
This fixes CodeGen/Generic/vector.ll
llvm-svn: 26843
2006-03-19 00:07:49 +00:00
32206f54c6
Change the structure of lowering vector stuff. Note: This breaks some
...
things.
llvm-svn: 26840
2006-03-18 01:44:44 +00:00
98931bc381
add a couple enum values
...
llvm-svn: 26830
2006-03-17 19:53:59 +00:00
bb01d4f272
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
7ececaad83
Fix a problem fully scalarizing values.
...
llvm-svn: 26811
2006-03-16 23:05:19 +00:00
8471b15706
Add support for CopyFromReg from vector values. Note: this doesn't support
...
illegal vector types yet!
llvm-svn: 26799
2006-03-16 19:57:50 +00:00
49409cb925
Teach CreateRegForValue how to handle vector types.
...
llvm-svn: 26798
2006-03-16 19:51:18 +00:00
4024c00ce7
add support for vector->vector casts
...
llvm-svn: 26788
2006-03-15 22:19:46 +00:00
cad70c3e46
Add a note, this code should be moved to the dag combiner.
...
llvm-svn: 26787
2006-03-15 22:19:18 +00:00
71050ba709
Expand subprogram and added block descriptor.
...
llvm-svn: 26782
2006-03-15 19:09:58 +00:00
b8e155567a
1. Use null for serialized empty strings.
...
2. Allow for user defined debug descriptors.
3. Allow for user augmented fields on debug descriptors.
llvm-svn: 26760
2006-03-14 18:37:57 +00:00
68ac09d5cb
make sure dead token factor nodes are removed by the dag combiner.
...
llvm-svn: 26731
2006-03-13 18:37:30 +00:00
acb6e34277
Handle the removal of the debug chain.
...
llvm-svn: 26729
2006-03-13 13:07:37 +00:00
d8c2a48d58
Fold X+Y -> X|Y when safe. This implements:
...
Regression/CodeGen/PowerPC/and_add.ll
a case that occurs with dynamic allocas of constant size.
llvm-svn: 26727
2006-03-13 06:51:27 +00:00
8bb6cb7d7b
add a couple of missing folds
...
llvm-svn: 26724
2006-03-13 06:26:26 +00:00
994d8e6bd4
For targets with FABS/FNEG support, lower copysign to an integer load,
...
a select and FABS/FNEG.
This speeds up a trivial (aka stupid) copysign benchmark I wrote from 6.73s
to 2.64s, woo.
llvm-svn: 26723
2006-03-13 06:08:38 +00:00
a767dbf197
Don't advance the hazard recognizer when there are no hazards and no instructions
...
to be emitted.
Don't add one to the latency of a completed instruction if the latency of the
op is 0.
llvm-svn: 26718
2006-03-12 09:01:41 +00:00
86a9b60a25
Chain operands aren't real uses: they don't require the full latency of the
...
predecessor to finish before they can start.
llvm-svn: 26717
2006-03-12 03:52:09 +00:00
572003ca15
As a pending queue data structure to keep track of instructions whose
...
operands have all issued, but whose results are not yet available. This
allows us to compile:
int G;
int test(int A, int B, int* P) {
return (G+A)*(B+1);
}
to:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
addi r4, r4, 1
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
instead of this, which has a stall between the lis/lwz:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
addi r4, r4, 1
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
llvm-svn: 26716
2006-03-12 00:38:57 +00:00
356183d91e
rename priorityqueue -> availablequeue. When a node is scheduled, remember
...
which cycle it lands on.
llvm-svn: 26714
2006-03-11 22:44:37 +00:00
063086b0f4
Make CurrCycle a local var instead of an instance var
...
llvm-svn: 26713
2006-03-11 22:34:41 +00:00
9995a0c019
Move some methods around so that BU specific code is together, TD specific code
...
is together, and direction independent code is together.
llvm-svn: 26712
2006-03-11 22:28:35 +00:00
578d8fcb59
merge preds/chainpreds -> preds set
...
merge succs/chainsuccs -> succs set
This has no functionality change, simplifies the code, and reduces the size
of sunits.
llvm-svn: 26711
2006-03-11 22:24:20 +00:00
38280c0020
Added a parameter to control whether Constant::getStringValue() would chop
...
off the result string at the first null terminator.
llvm-svn: 26704
2006-03-10 23:52:03 +00:00
d3ef6c290a
scrape out bits of llvm-db
...
llvm-svn: 26701
2006-03-10 22:48:19 +00:00
f918e15362
Move simple-selector-specific types to the simple selector.
...
llvm-svn: 26693
2006-03-10 07:51:18 +00:00
5255d04357
Simplify the interface to the schedulers, to not pass the selected heuristicin.
...
llvm-svn: 26692
2006-03-10 07:49:12 +00:00
a5b93b8c6d
Move some simple-sched-specific instance vars to the simple scheduler.
...
llvm-svn: 26690
2006-03-10 07:42:02 +00:00
e015178de1
prune #includes
...
llvm-svn: 26689
2006-03-10 07:37:35 +00:00
4b70ff7876
move some simple scheduler methods into the simple scheduler
...
llvm-svn: 26688
2006-03-10 07:35:21 +00:00
dc2f135f5c
Make EmitNode take a SDNode instead of a NodeInfo*
...
llvm-svn: 26687
2006-03-10 07:28:36 +00:00
b9d8fa0342
Move the VRBase field from NodeInfo to being a separate, explicit, map.
...
llvm-svn: 26686
2006-03-10 07:25:12 +00:00
c48cfba44b
no need to build groups anymore
...
llvm-svn: 26684
2006-03-10 07:15:58 +00:00
6f82fe8106
Create SUnits directly from the SelectionDAG.
...
llvm-svn: 26683
2006-03-10 07:13:32 +00:00
2f8c7c3d55
Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy
...
llvm-svn: 26682
2006-03-10 06:34:51 +00:00
349e9ddccc
Teach the latency scheduler some new tricks. In particular, to break ties,
...
keep track of a sense of "mobility", i.e. how many other nodes scheduling one
node will free up. For something like this:
float testadd(float *X, float *Y, float *Z, float *W, float *V) {
return (*X+*Y)*(*Z+*W)+*V;
}
For example, this makes us schedule *X then *Y, not *X then *Z. The former
allows us to issue the add, the later only lets us issue other loads.
This turns the above code from this:
_testadd:
lfs f0, 0(r3)
lfs f1, 0(r6)
lfs f2, 0(r4)
lfs f3, 0(r5)
fadds f0, f0, f2
fadds f1, f3, f1
lfs f2, 0(r7)
fmadds f1, f0, f1, f2
blr
into this:
_testadd:
lfs f0, 0(r6)
lfs f1, 0(r5)
fadds f0, f1, f0
lfs f1, 0(r4)
lfs f2, 0(r3)
fadds f1, f2, f1
lfs f2, 0(r7)
fmadds f1, f1, f0, f2
blr
llvm-svn: 26680
2006-03-10 05:51:05 +00:00
25e2556b71
add an aggregate method for reinserting scheduled nodes, add a callback for
...
priority impls that want to be notified when a node is scheduled
llvm-svn: 26678
2006-03-10 04:32:49 +00:00
6ce97687f7
Fix VC++ build breakage.
...
llvm-svn: 26676
2006-03-10 03:57:45 +00:00
213209a248
remove dbg_declare, it's not used yet.
...
llvm-svn: 26659
2006-03-09 20:02:42 +00:00
f0fc6bbaf3
back out my previous hack
...
llvm-svn: 26650
2006-03-09 17:48:46 +00:00
c6c9e65301
remove temporary option
...
llvm-svn: 26646
2006-03-09 17:31:22 +00:00
c44be2c4ef
temporary hack to get the build working again, apparently a header
...
commit was forgotten
llvm-svn: 26642
2006-03-09 17:11:08 +00:00
4b0e1d9e6c
Move bit field endianness to backend.
...
llvm-svn: 26639
2006-03-09 13:28:47 +00:00
d17d77aa1d
yes yes, enabled debug output is bad
...
llvm-svn: 26637
2006-03-09 07:39:25 +00:00
6398c13128
switch the t-d scheduler to use a really dumb and trivial critical path
...
latency priority function.
llvm-svn: 26636
2006-03-09 07:38:27 +00:00
d4130375c0
Pull latency information for target instructions out of the latency tables. :)
...
Only enable this with -use-sched-latencies, I'll enable it by default with a
clean nightly tester run tonight.
PPC is the only target that provides latency info currently.
llvm-svn: 26634
2006-03-09 07:15:18 +00:00
da6aafeef4
don't copy all itinerary data
...
llvm-svn: 26633
2006-03-09 07:13:00 +00:00
399bee27f0
PriorityQueue is an instance var, use it.
...
llvm-svn: 26632
2006-03-09 06:48:37 +00:00
9e95accf4e
add some comments
...
llvm-svn: 26631
2006-03-09 06:37:29 +00:00
9df647539d
Refactor the priority mechanism one step further: now that it is a separate
...
class, sever its implementation from the interface. Now we can provide new
implementations of the same interface (priority computation) without touching
the scheduler itself.
llvm-svn: 26630
2006-03-09 06:35:14 +00:00
2698f0de7a
Get rid of the multiple copies of getStringValue. Now a Constant:: method.
...
llvm-svn: 26616
2006-03-08 18:11:07 +00:00
fd22d42945
Split the priority function computation and priority queue management out
...
of the ScheduleDAGList class into a new SchedulingPriorityQueue class.
llvm-svn: 26613
2006-03-08 05:18:27 +00:00
42e2026cb0
switch from an explicitly managed list of SUnits to a simple vector of sunits
...
llvm-svn: 26612
2006-03-08 04:54:34 +00:00
12c6d89204
Shrinkify some fields, fit to 80 columns
...
llvm-svn: 26611
2006-03-08 04:41:06 +00:00
3fe975b846
revert the previous patch, didn't mean to check it in yet
...
llvm-svn: 26610
2006-03-08 04:39:05 +00:00
af5e26c980
remove "Slot", it is dead
...
llvm-svn: 26609
2006-03-08 04:37:58 +00:00
543832d39d
Change the interface for getting a target HazardRecognizer to be more clean.
...
llvm-svn: 26608
2006-03-08 04:25:59 +00:00
2370265550
libstdc++-v3 was failing to build. Needed to handle composite types with empty
...
members (running into a zero initializer.)
llvm-svn: 26607
2006-03-08 02:07:02 +00:00
313570fb17
Use "llvm.metadata" section for debug globals. Filter out these globals in the
...
asm printer.
llvm-svn: 26599
2006-03-07 22:00:35 +00:00
69effa2325
Switch to using a numeric id for anchors.
...
llvm-svn: 26598
2006-03-07 20:53:47 +00:00
3bad199894
Bitfield support.
...
llvm-svn: 26593
2006-03-07 15:51:33 +00:00
0c801bd1cf
Fix some formatting, when looking for hazards, prefer target nodes over
...
things like copyfromreg.
llvm-svn: 26586
2006-03-07 05:40:43 +00:00
01aa752a36
update file comment
...
llvm-svn: 26573
2006-03-06 17:58:04 +00:00
a00c61932d
Remove some code that doesn't make sense
...
llvm-svn: 26572
2006-03-06 07:31:44 +00:00
c5c0658aa6
Remove SUnit::Priority1: it is re-calculated on demand as number of live
...
range to be generated.
llvm-svn: 26570
2006-03-06 06:08:54 +00:00
47639dbb93
Hoist the HazardRecognizer out of the ScheduleDAGList.cpp file to where
...
targets can implement them. Make the top-down scheduler non-g5-specific.
Remove the old testing hazard recognizer.
llvm-svn: 26569
2006-03-06 00:22:00 +00:00
00b52ea8f9
Comment fixes
...
llvm-svn: 26567
2006-03-05 23:59:20 +00:00
80268aaeed
Don't depend on the C99 copysign function, implement it ourselves.
...
llvm-svn: 26566
2006-03-05 23:57:58 +00:00
Nate Begeman