a000002428
VNInfos don't need to be destructed anymore.
...
llvm-svn: 106943
2010-06-26 11:30:59 +00:00
e9afee2910
resort to ArgOperand API
...
llvm-svn: 106942
2010-06-26 09:35:09 +00:00
8cfa7713e9
Followup to r106770: actually generate SXTB and SXTH for sign-extensions.
...
llvm-svn: 106940
2010-06-26 04:36:50 +00:00
c72da6bb56
Clean up some problems with extra CFG edges being introduced during
...
if-conversion. The RemoveExtraEdges function doesn't work for blocks that
end with unanalyzable branches, so in those cases, the "extra" edges must
be explicitly removed. The CopyAndPredicateBlock and MergeBlocks methods
can also avoid copying successor edges due to branches that have already
been removed. The latter case is especially helpful when MergeBlocks is
called for handling "diamond" if-conversions, where otherwise you can end
up with some weird intermediate states in the CFG. Unfortunately I've
been unable to find cases where this cleanup actually makes a significant
difference in the code. There is one test where we manage to remove an
empty block at the end of a function. Radar 6911268.
llvm-svn: 106939
2010-06-26 04:27:33 +00:00
0248da9db4
Add support for encoding NEON VMOV (from scalar to core register) instructions.
...
llvm-svn: 106938
2010-06-26 04:07:15 +00:00
b71233f34d
It's now possible to run code placement pass for ARM.
...
llvm-svn: 106935
2010-06-26 01:52:05 +00:00
d7d0d4e882
When creating X86 MUL8 and DIV8 instructions, make sure we don't produce
...
CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.
Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).
This fixes PR7312.
llvm-svn: 106934
2010-06-26 00:39:23 +00:00
b4d39841e4
Renumber NEON instruction formats to be consecutive.
...
llvm-svn: 106927
2010-06-26 00:05:09 +00:00
cc386fb125
Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to
...
"N..." instead of "NEON..." for consistency with the other NEON format names.
llvm-svn: 106921
2010-06-25 23:56:05 +00:00
74d716b9cd
Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
...
llvm-svn: 106917
2010-06-25 23:47:23 +00:00
d66f66a5cf
Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.
...
Renumber MiscFrm to 25.
llvm-svn: 106916
2010-06-25 23:45:37 +00:00
83651094ad
Reapply r106896:
...
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
llvm-svn: 106912
2010-06-25 23:33:42 +00:00
acbdf53db4
Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was
...
introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.
llvm-svn: 106908
2010-06-25 23:14:54 +00:00
c34befc78f
make sure to handle dbg_value instructions in the middle of the block, not
...
just at the head, when doing diamond if-conversion. rdar://7797940
llvm-svn: 106907
2010-06-25 23:05:46 +00:00
4530fed87e
revert this now, it's using avx instead of sse :)
...
llvm-svn: 106906
2010-06-25 23:04:29 +00:00
55d738e2e1
Don't track kills in VNInfo. Use interval ends instead.
...
The VNInfo.kills vector was almost unused except for all the code keeping it
updated. The few places using it were easily rewritten to check for interval
ends instead.
The two new methods LiveInterval::killedAt and killedInRange are replacements.
This brings us down to 3 independent data structures tracking kills.
llvm-svn: 106905
2010-06-25 22:53:05 +00:00
02b184de5b
Change if-conversion block size limit checks to add some flexibility.
...
llvm-svn: 106901
2010-06-25 22:42:03 +00:00
2530ca0647
Add support for encoding 3-register NEON instructions, and fix
...
emitNEON2RegInstruction's handling of 2-address operands.
llvm-svn: 106900
2010-06-25 22:40:46 +00:00
fb9712bdae
In GenerateReassociations, don't bother thinking about individual
...
SCEVUnknown values which are loop-variant, as LSR can't do anything
interesting with these values in any case. This fixes very slow compile
times on loops which have large numbers of such values.
llvm-svn: 106897
2010-06-25 22:32:18 +00:00
a34d9b6d84
Add several AVX MOV flavors
...
Support VEX encoding for MRMDestReg
llvm-svn: 106896
2010-06-25 22:27:51 +00:00
5c0f85c7dd
Collect debug info for optimized variables of inlined functions.
...
llvm-svn: 106895
2010-06-25 22:07:34 +00:00
8a6deefec6
80 column and typo fix
...
llvm-svn: 106894
2010-06-25 22:02:28 +00:00
ce97d55ad9
The hasMemory argument is irrelevant to how the argument
...
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
llvm-svn: 106893
2010-06-25 21:55:36 +00:00
e70c8b150b
Add support for encoding 2-register NEON instructions.
...
llvm-svn: 106891
2010-06-25 21:17:19 +00:00
8de1fe3ccf
pcmpeqd and friends are Commutable.
...
llvm-svn: 106886
2010-06-25 21:05:35 +00:00
574f68f815
Fix indentation.
...
llvm-svn: 106881
2010-06-25 20:54:44 +00:00
e41e40f689
- Reapply r106066 now that the bzip2 build regression has been fixed.
...
- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.
llvm-svn: 106880
2010-06-25 20:48:10 +00:00
ef7acd9a24
We should remove the live range from the destination register only if *all* defs
...
are dead, not just the def of this register. I.e., a register could be dead, but
it's subreg isn't.
Testcase to follow with a subsequent patch.
llvm-svn: 106878
2010-06-25 20:42:55 +00:00
553fafc6ce
Move the last piece of SSE2 convert instructions to the Convert Instructions section
...
llvm-svn: 106877
2010-06-25 20:29:27 +00:00
62d1403a03
More SSE refactoring, this time with different types of MOVs
...
llvm-svn: 106876
2010-06-25 20:22:12 +00:00
89dd42af31
Eliminate a redundant FoldingSet lookup.
...
llvm-svn: 106872
2010-06-25 18:47:08 +00:00
ba3ece6f27
IT instructions are considered to be scheduling hazards, but are scheduled
...
with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.
Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.
llvm-svn: 106871
2010-06-25 18:43:14 +00:00
e76c0b13b9
Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders
...
llvm-svn: 106867
2010-06-25 18:06:22 +00:00
2ac3b9cbd4
Cosmetic.
...
llvm-svn: 106865
2010-06-25 17:41:07 +00:00
58e6c2eded
Rewrite MemoryBuffer::getSTDIN to use read(2) and a SmallVector buffer.
...
llvm-svn: 106856
2010-06-25 16:07:18 +00:00
2dc70bea54
Remove variables which are assigned to but for which the value
...
is not used. Spotted by gcc-4.6.
llvm-svn: 106854
2010-06-25 14:48:39 +00:00
948dd57945
Bring back the empty vector workaround I removed in r106839. Looks like MSVC needs it.
...
llvm-svn: 106841
2010-06-25 12:51:01 +00:00
ce2a92220f
Tweak MemoryBuffer to allocate the class itself, the name and possibly the
...
buffer in the same chunk of memory.
2 less mallocs for every uninitialized MemoryBuffer and 1 less malloc for every
MemoryBuffer pointing to a memory range translate into 20% less mallocs on
clang -cc1 -Eonly Cocoa_h.m.
llvm-svn: 106839
2010-06-25 11:50:40 +00:00
b890fc8023
use ArgOperand accessors
...
and CallInst for getting hold
of the intrinsic's arguments
simplify along the way (at least for me this is much more legible now)
Bill, Baldrick or Anton, please review\!
llvm-svn: 106838
2010-06-25 11:25:30 +00:00
7dd3afdff3
use ArgOperand API (the simple part)
...
llvm-svn: 106837
2010-06-25 09:44:37 +00:00
eba0be7dc9
use ArgOperand API
...
llvm-svn: 106836
2010-06-25 09:38:13 +00:00
41b81ee2fb
use ArgOperand API
...
llvm-svn: 106835
2010-06-25 09:36:23 +00:00
ed9ae7bf21
use ArgOperand API and CallSite to access arguments of CallInst
...
llvm-svn: 106833
2010-06-25 09:03:52 +00:00
b5874dea6e
use ArgOperand API and CallSite to access arguments of CallInst
...
llvm-svn: 106829
2010-06-25 08:48:19 +00:00
e4eed709d4
use ArgOperand API
...
llvm-svn: 106828
2010-06-25 08:24:59 +00:00
f6207e0a80
prune an include
...
llvm-svn: 106827
2010-06-25 08:16:50 +00:00
e3ba486c9f
use ArgOperand API (one more hunk I could split)
...
llvm-svn: 106825
2010-06-25 07:58:41 +00:00
5f3e656a1b
use ArgOperand API (some hunks I could split)
...
llvm-svn: 106824
2010-06-25 07:57:14 +00:00
07e9284c75
use ArgOperand API; tighten type of handleFreeWithNonTrivialDependency to be able to use isFreeCall whithout a cast or new overload
...
llvm-svn: 106823
2010-06-25 07:40:32 +00:00
07aead2f8d
Add missing ARM and Thumb data layout info for vector types.
...
Radar 8128745.
llvm-svn: 106820
2010-06-25 04:41:08 +00:00
eadbf9732f
Reduce indentation.
...
llvm-svn: 106819
2010-06-25 04:12:31 +00:00
e9eaaa91d8
Fix a case where an earlyclobber operand of an asm
...
is reused as an input. PR 4118. Testcase is too big,
as usual with bugs in this area, but there's one in
the PR.
llvm-svn: 106816
2010-06-25 00:49:43 +00:00
cbdcce6478
Add some AVX convert instructions
...
llvm-svn: 106815
2010-06-25 00:39:30 +00:00
889ab7d158
Make sure all eliminated kills are removed from VNInfo lists.
...
This fixes PR7479 and PR7485. The test cases from those PRs are big, so not
included. However, PR7485 comes from self hosting on FreeBSD, so we will surely
hear about any regression.
llvm-svn: 106811
2010-06-24 23:57:35 +00:00
5f0bf64c0c
Add some comments.
...
llvm-svn: 106809
2010-06-24 23:41:59 +00:00
447735aa98
Refactoring of SSE convert intrinsics
...
llvm-svn: 106808
2010-06-24 23:37:07 +00:00
9a2f0473b2
Teach EmitLiveInCopies to omit copies for unused virtual registers,
...
and to clean up unused incoming physregs from the live-in list.
llvm-svn: 106805
2010-06-24 22:23:02 +00:00
78827d1952
Refactoring of SSE conversion instructions
...
llvm-svn: 106804
2010-06-24 22:22:21 +00:00
6b6b605917
Refactor SSE cmp intrinsics and declare the same for AVX
...
llvm-svn: 106796
2010-06-24 22:04:40 +00:00
2d3c490026
It's possible that a flag is added to the SDNode that points back to the
...
original SDNode. This is badness. Also, this function allows one SDNode to point
multiple flags to another SDNode. Badness as well.
llvm-svn: 106793
2010-06-24 22:00:37 +00:00
c657c621b7
DBG_VALUE machine instruction pointing to undefined register for a variable justify a separate scope if the variable is inlined function's argument.
...
Radar 8122864.
llvm-svn: 106792
2010-06-24 21:51:19 +00:00
2b87d44c5d
Don't return a std::vector in the Spiller interface, but take a reference to a
...
vector instead. This avoids needless copying and allocation.
Add documentation.
llvm-svn: 106788
2010-06-24 20:54:29 +00:00
4398fd7b83
- Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}.
...
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.
llvm-svn: 106787
2010-06-24 20:48:23 +00:00
9b659142a6
Remove the now unused LiveIntervals::getVNInfoSourceReg().
...
This method was always a bit too simplistic for the real world. It didn't really
deal with subregisters and such.
llvm-svn: 106781
2010-06-24 20:18:15 +00:00
487ed997d0
Teach AdjustCopiesBackFrom to also use CoalescerPair to identify compatible copies.
...
llvm-svn: 106780
2010-06-24 20:16:00 +00:00
5ad5226c58
Disallow matching "i" constraint to symbol addresses when
...
address requires a register or secondary load to compute
(most PIC modes). This improves "g" constraint handling. 8015842.
The test from 2007 is attempting to test the fix for PR1761,
but since -relocation-model=static doesn't work on Darwin
x86-64, it was not testing what it was supposed to be testing
and was passing erroneously. Fixed to use Linux x86-64.
llvm-svn: 106779
2010-06-24 20:14:51 +00:00
7f894d8fdc
Remove the -fast-spill option.
...
This code path has never really been used, and we are going to be handling
spilling through the Spiller interface in the future.
llvm-svn: 106777
2010-06-24 19:56:08 +00:00
c26e2f4b70
Oops. IT block formation pass needs to be run at any optimization level.
...
llvm-svn: 106775
2010-06-24 19:10:14 +00:00
3f0e992af1
Loosen up the requirements in the Horrible Hack(tm) to include all selectors
...
which don't have a catch-all associated with them not just clean-ups. This fixes
the SingleSource/Benchmarks/Shootout-C++/except.cpp testcase that broke because
of my change r105902.
llvm-svn: 106772
2010-06-24 18:49:10 +00:00
246c41d93e
Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324.
...
llvm-svn: 106770
2010-06-24 18:20:04 +00:00
45230239e4
Replace a big gob of old coalescer logic with the new CoalescerPair class.
...
CoalescerPair can determine if a copy can be coalesced, and which register gets
merged away. The old logic in SimpleRegisterCoalescing had evolved into
something a bit too convoluted.
This second attempt fixes some crashes that only occurred Linux.
llvm-svn: 106769
2010-06-24 18:15:01 +00:00
4143e9deeb
Add an exports file for the Hello example plugin.
...
llvm-svn: 106768
2010-06-24 17:36:51 +00:00
a612d7c012
Print the LSBs of a SlotIndex symbolically using letters referring to the
...
[L]oad, [u]se, [d]ef, or [S]tore slots.
This makes it easier to see if two indices refer to the same instruction,
avoiding mental mod 4 calculations.
llvm-svn: 106766
2010-06-24 17:31:07 +00:00
8a84cd57ae
Simplify this code; switch lowering shouldn't produce cases
...
which trivially fold away.
llvm-svn: 106765
2010-06-24 17:08:31 +00:00
963b1c142e
A few minor micro-optimizations.
...
llvm-svn: 106764
2010-06-24 16:57:52 +00:00
47ddf76d89
Teach getExactSDiv to evaluate x/1 to x up front, as it's a common
...
enough special case, and it theoretically allows more folding because
it works even when x is unanalyzable.
llvm-svn: 106763
2010-06-24 16:51:25 +00:00
279e55fb2e
PR7458: Try commuting Thumb2 instruction operands to put them into 2-address
...
form so they can be narrowed to 16-bit instructions.
llvm-svn: 106762
2010-06-24 16:50:20 +00:00
5235cc2c25
Don't try to preserve pointer types in SCEVConstants; the old code
...
was over-complicated.
llvm-svn: 106760
2010-06-24 16:47:03 +00:00
ab5422200b
Fix copy+pasto issues in isMulSExtable.
...
llvm-svn: 106759
2010-06-24 16:45:11 +00:00
3ace9f4e3d
Make the trunc code consistent with the zext and sext code in its
...
handling of pointer types.
llvm-svn: 106757
2010-06-24 16:33:38 +00:00
b377e2828d
Add overloads for getFile and getFileOrSTDIN which take a const char *
...
instead of a StringRef, avoiding the need to copy the string in the
common case.
llvm-svn: 106754
2010-06-24 16:25:50 +00:00
3b2b46a700
Be more strict about subreg-to-subreg copies in CoalescerPair.
...
Also keep track of the original DstREg before subregister adjustments.
llvm-svn: 106753
2010-06-24 16:19:28 +00:00
7ccec09252
use ArgOperand API
...
llvm-svn: 106752
2010-06-24 16:11:44 +00:00
53ccab7d1c
Verify that VNI kills are pointing to existing instructions.
...
In this case it is essential that the kill is real because the spiller will
decide to omit a spill if it thinks there is a later kill.
llvm-svn: 106751
2010-06-24 15:56:59 +00:00
a6d75e2cf7
use (even more, still) ArgOperand API
...
llvm-svn: 106750
2010-06-24 15:51:11 +00:00
463f26b4be
Eliminate the other half of the BRCOND optimization, and update
...
as many tests as possible.
llvm-svn: 106749
2010-06-24 15:24:03 +00:00
df6b33e778
Eliminate the first have of the optimization which eliminates BRCOND
...
when the condition is constant. This optimization shouldn't be
necessary, because codegen shouldn't be able to find dead control
paths that the IR-level optimizer can't find. And it's undesirable,
because it encourages bugpoint to leave "br i1 false" branches
in its output. And it wasn't updating the CFG.
I updated all the tests I could, but some tests are too reduced
and I wasn't able to meaningfully preserve them.
llvm-svn: 106748
2010-06-24 15:04:11 +00:00
218f5541b2
use ArgOperand API and CallSite for arg range; add necessary casts and perform some cosmetics
...
llvm-svn: 106747
2010-06-24 14:42:01 +00:00
600f62b3ba
Reapply r106634, now that the bug it exposed is fixed.
...
llvm-svn: 106746
2010-06-24 14:30:44 +00:00
5aafdf1e43
use ArgOperand API and CallSite for arg range
...
llvm-svn: 106745
2010-06-24 14:13:36 +00:00
0a136c9b53
use (even more) ArgOperand API
...
llvm-svn: 106744
2010-06-24 13:54:33 +00:00
590d95ed18
use ArgOperand API
...
llvm-svn: 106743
2010-06-24 13:42:49 +00:00
589a0b950a
use ArgOperand API
...
llvm-svn: 106740
2010-06-24 12:58:35 +00:00
7943017490
use ArgOperand API
...
llvm-svn: 106737
2010-06-24 12:35:13 +00:00
75f6943c95
use ArgOperand API, also tighten the type of visitFree to make this work out smoothly
...
llvm-svn: 106736
2010-06-24 12:21:15 +00:00
91f9589057
use ArgOperand API; introduce downcasted pointers into scope to facilitate this
...
llvm-svn: 106734
2010-06-24 12:03:56 +00:00
e2f482ca0b
use ArgOperand API
...
llvm-svn: 106731
2010-06-24 10:42:46 +00:00
2d958d4db5
use ArgOperand API
...
llvm-svn: 106730
2010-06-24 10:17:17 +00:00
5bcaa55761
use callsite to obtain all arguments
...
llvm-svn: 106729
2010-06-24 10:04:07 +00:00
42f620cc55
use callsite to obtain all arguments
...
llvm-svn: 106728
2010-06-24 09:56:43 +00:00
8048662539
Teach the x86 mc assembler that %dr6 = %db6, this implements
...
rdar://8013734
llvm-svn: 106725
2010-06-24 07:29:18 +00:00
c4e84309c4
more cleanups
...
llvm-svn: 106724
2010-06-24 07:18:14 +00:00
056fd06c5f
reduce indentation
...
llvm-svn: 106723
2010-06-24 07:16:25 +00:00
cfed96a410
fix breakage from r98938 by correctly marking msp430 calls as variadic.
...
Patch by Ben Ransford!
llvm-svn: 106722
2010-06-24 06:46:50 +00:00
c3e291c560
Fix a bug in the code which determines when it's safe to use the
...
bt instruction, which was exposed by r106263.
llvm-svn: 106718
2010-06-24 02:07:59 +00:00
fa6ce139a9
Add a couple more quick comments.
...
llvm-svn: 106717
2010-06-24 02:07:57 +00:00
0695e09b09
Optimize the "bit test" code path for switch lowering in the
...
case where the bit mask has exactly one bit.
llvm-svn: 106716
2010-06-24 02:06:24 +00:00
dbb58d2974
Revert "Replace a big gob of old coalescer logic with the new CoalescerPair class."
...
Whiny buildbots.
llvm-svn: 106710
2010-06-24 00:52:22 +00:00
0f60709f0e
use getNumArgOperands
...
llvm-svn: 106709
2010-06-24 00:48:48 +00:00
4a39b84a9d
use ArgOperand API
...
llvm-svn: 106707
2010-06-24 00:44:01 +00:00
0dc3c2d37e
Use ValueMap instead of DenseMap.
...
The ValueMapper used by various cloning utility maps MDNodes also.
llvm-svn: 106706
2010-06-24 00:33:28 +00:00
191a1cd2bb
Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases
...
llvm-svn: 106705
2010-06-24 00:32:06 +00:00
6af02a6f69
Move SSE and AVX shuffle, unpack and compare code to more appropriate places
...
llvm-svn: 106702
2010-06-24 00:15:50 +00:00
f38e6720cc
Replace a big gob of old coalescer logic with the new CoalescerPair class.
...
CoalescerPair can determine if a copy can be coalesced, and which register gets
merged away. The old logic in SimpleRegisterCoalescing had evolved into
something a bit too convoluted.
llvm-svn: 106701
2010-06-24 00:12:39 +00:00
d8dedee96d
Use available typedef for " DenseMap<const Value*, Value*>".
...
llvm-svn: 106699
2010-06-24 00:00:42 +00:00
b8f11de105
Cosmetic change.
...
Do not use "ValueMap" as a name for a local variable or an argument.
llvm-svn: 106698
2010-06-23 23:55:51 +00:00
1abbde3103
use ArgOperand accessors
...
llvm-svn: 106697
2010-06-23 23:38:07 +00:00
f470747a36
We are missing opportunites to use ldm. Take code like this:
...
void t(int *cp0, int *cp1, int *dp, int fmd) {
int c0, c1, d0, d1, d2, d3;
c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
/* ... */
}
It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.
llvm-svn: 106693
2010-06-23 23:00:16 +00:00
253c6bf366
use the new isFreeCall API and ArgOperand accessors
...
llvm-svn: 106692
2010-06-23 22:48:06 +00:00
5f5a864539
minor enhancement to llvm::isFreeCall API: return CallInst; no functional change
...
llvm-svn: 106686
2010-06-23 21:51:12 +00:00
ad7884ad98
use ArgOperand getters
...
llvm-svn: 106685
2010-06-23 21:41:47 +00:00
05220c9a0d
Add AVX MOVMSK{PS,PD}rr instructions
...
llvm-svn: 106683
2010-06-23 21:30:27 +00:00
3183dd5692
Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction
...
llvm-svn: 106678
2010-06-23 21:10:57 +00:00
5fed9b7c6c
Update according to feedback.
...
llvm-svn: 106677
2010-06-23 20:49:35 +00:00
360d6fe299
Add AVX SHUF{PS,PD}{rr,rm} instructions
...
llvm-svn: 106672
2010-06-23 20:07:15 +00:00
337e8db712
Add support for the x86 instructions "pusha" and "popa".
...
llvm-svn: 106671
2010-06-23 20:00:58 +00:00
d24c66b4a3
Do not do tail calls to external symbols. If the
...
branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this. 8120438.
If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.
llvm-svn: 106662
2010-06-23 18:52:34 +00:00
a136521a17
MorphNodeTo doesn't preserve the memory operands. Because we're morphing a node
...
into the same node, but with different non-memory operands, we need to replace
the memory operands after it's finished morphing.
llvm-svn: 106643
2010-06-23 18:16:24 +00:00
4df321b7ad
Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
...
llvm-svn: 106634
2010-06-23 17:09:26 +00:00
6f71039fa4
The generic DAG combiner can now fold atomic fences when needed, so switch
...
to using that.
llvm-svn: 106633
2010-06-23 16:25:07 +00:00
a8ea498171
When using libcall expansions for the atomic intrinsics, the explicit
...
MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.
llvm-svn: 106631
2010-06-23 16:08:49 +00:00
b58c08b0ba
Some targets don't require the fencing MEMBARRIER instructions surrounding
...
atomic intrinsics, either because the use locking instructions for the
atomics, or because they perform the locking directly. Add support in the
DAG combiner to fold away the fences.
llvm-svn: 106630
2010-06-23 16:07:42 +00:00
731ea71f59
Add a few VNInfo data structure checks.
...
llvm-svn: 106627
2010-06-23 15:34:36 +00:00
4d18165f82
use ArgOperand accessors
...
llvm-svn: 106626
2010-06-23 13:56:57 +00:00
c9a9251844
use ArgOperand accessors
...
llvm-svn: 106623
2010-06-23 13:09:06 +00:00
e54065394e
use helper to neatly access arguments
...
llvm-svn: 106622
2010-06-23 08:45:32 +00:00
3d6e2c6335
Update uses, defs, and comments for darwin tls patterns.
...
llvm-svn: 106621
2010-06-23 08:01:49 +00:00
ef5a4383ad
Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang.
...
Conflicts:
lib/CodeGen/MachineSink.cpp
llvm-svn: 106614
2010-06-23 00:48:25 +00:00
7f85520644
Get the addend correct for i386 pic.
...
Thanks Daniel!
llvm-svn: 106608
2010-06-22 23:51:47 +00:00
75c6b0bb1f
Replace ScalarEvolution's private copy of getLoopPredecessor
...
with LoopInfo's public copy.
llvm-svn: 106603
2010-06-22 23:43:28 +00:00
1e13c17a55
Add AVX compare packed instructions
...
llvm-svn: 106600
2010-06-22 23:37:59 +00:00
9ad629367d
Revert 106592 for now. It causes clang-selfhost build failure.
...
llvm-svn: 106598
2010-06-22 23:29:55 +00:00
1081f1a0f5
Fix OptimizeMax to handle an odd case where one of the max operands
...
is another max which folds. This fixes PR7454.
llvm-svn: 106594
2010-06-22 23:07:13 +00:00
535aa8ea91
Reapply support for AVX unpack and interleave instructions, with
...
testcases this time.
llvm-svn: 106593
2010-06-22 23:02:38 +00:00
87f75f75be
If a metadata operand is seeded in value map and the metadata should also be seeded in value map. This is not limited to function local metadata.
...
Failure to seed metdata in such cases causes troubles when in a cloned module, metadata from a new module refers to values in old module. Usually this results in mysterious bugpoint crashes. For example,
Checking to see if we can delete global inits: Unknown constant!
UNREACHABLE executed at /d/g/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp:904!
llvm-svn: 106592
2010-06-22 22:53:21 +00:00
e43c6487da
While cloning a module, clone metadata attached with instructions.
...
llvm-svn: 106591
2010-06-22 22:50:42 +00:00
1a890f9dc0
Add AVX MOV{SS,SD}{rr,rm} instructions
...
llvm-svn: 106588
2010-06-22 22:38:56 +00:00
8ce69cd95a
Fix the formatting of the switch statement and add a missing break.
...
llvm-svn: 106586
2010-06-22 22:16:17 +00:00
1023f6bd98
Also convert SUBREG_TO_REG to a KILL when relevant, like the other subreg
...
instructions.
This does not affect codegen much because SUBREG_TO_REG is only used by X86 and
X86 does not use the register scavenger, but it prevents verifier errors.
llvm-svn: 106583
2010-06-22 22:11:07 +00:00
c5d712232d
Thumb1 functions using @llvm.returnaddress were not saving the incoming LR.
...
Radar 8031193.
llvm-svn: 106582
2010-06-22 22:04:24 +00:00
e9c1bb6cb1
Look for and use a different darwin crash reporter library.
...
llvm-svn: 106576
2010-06-22 21:01:04 +00:00
6c275bc5a2
fix typo
...
llvm-svn: 106574
2010-06-22 20:52:02 +00:00
c89d2aad4c
use high-level accessors
...
llvm-svn: 106573
2010-06-22 20:40:38 +00:00
b575cf69f4
warmup ritual: use high-level argument accessors
...
llvm-svn: 106563
2010-06-22 19:46:37 +00:00
e3fbbd19ed
Clone named metadata while cloning a module.
...
Reapply Bob's patch.
llvm-svn: 106560
2010-06-22 18:52:38 +00:00
3af915f84b
Reorganize logical and arithmetic SSE 1 & 2 instructions
...
llvm-svn: 106557
2010-06-22 18:17:40 +00:00
b91af24d3e
Reorganize SSE instructions, making easier to see oportunities for refactoring
...
llvm-svn: 106556
2010-06-22 18:09:32 +00:00
3570f81b1e
Move PHIElimination's SplitCriticalEdge for MachineBasicBlocks out
...
into a utility routine, teach it how to update MachineLoopInfo, and
make use of it in MachineLICM to split critical edges on demand.
llvm-svn: 106555
2010-06-22 17:25:57 +00:00
9c47dac677
Remove the SimpleJoin optimization from SimpleRegisterCoalescing.
...
Measurements show that it does not speed up coalescing, so there is no reason
the keep the added complexity around.
Also clean out some unused methods and static functions.
llvm-svn: 106548
2010-06-22 16:13:57 +00:00
d2d1ae105d
Use pre-increment instead of post-increment when the result is not used.
...
llvm-svn: 106542
2010-06-22 15:08:57 +00:00
2ceaa71bdb
Add an explicit keyword.
...
llvm-svn: 106538
2010-06-22 13:53:29 +00:00
f820bd327d
Allow "exhaustive" trip count evaluation on phi nodes with all
...
constant operands.
llvm-svn: 106537
2010-06-22 13:15:46 +00:00
f040dec68a
Revert 106528. It is causing self host failures.
...
llvm-svn: 106529
2010-06-22 06:14:09 +00:00
b195eb4acf
Do not rely on DenseMap slot which can be easily invalidated when DenseMap grows.
...
llvm-svn: 106528
2010-06-22 05:16:56 +00:00
6c1fc79cab
Revert my change to clone named metadata. Buildbots are complaining.
...
--- Reverse-merging r106508 into '.':
U lib/Transforms/Utils/CloneModule.cpp
llvm-svn: 106521
2010-06-22 02:08:51 +00:00
2370e2fe0f
When unfolding a load, avoid assuming which instruction that
...
kill and dead flags will end up on.
llvm-svn: 106520
2010-06-22 02:07:21 +00:00
b6e058da18
Use single interface, using twine, to get named metadata.
...
getNamedMetadata().
llvm-svn: 106518
2010-06-22 01:19:38 +00:00
37bb617f8a
Tail merging pass shall not break up IT blocks. rdar://8115404
...
llvm-svn: 106517
2010-06-22 01:18:16 +00:00
cbc6fd8493
Discard special LLVM prefix from linkage name.
...
llvm-svn: 106516
2010-06-22 01:06:05 +00:00
ad51735794
Do not rely on Twine temporaries to survive.
...
llvm-svn: 106515
2010-06-22 01:01:58 +00:00
60bb7c42a7
make sure to initialize indent_level
...
llvm-svn: 106513
2010-06-22 00:40:26 +00:00
851e478e6b
Fix the new load-unfolding code to update LiveVariable's dead flags,
...
in addition to the kill flags.
llvm-svn: 106512
2010-06-22 00:32:04 +00:00
5f9575c1cd
Include named metadata when cloning a module.
...
llvm-svn: 106508
2010-06-22 00:11:03 +00:00
64960f55fe
add some support for blockaddress. This isn't really enough to be useful,
...
but it will cover uses of blockaddress that are actually in a function.
llvm-svn: 106502
2010-06-21 23:19:36 +00:00
bb45b964f8
eliminate a mutable global variable, use raw_ostream::indent instead of
...
rolling our own.
llvm-svn: 106501
2010-06-21 23:14:47 +00:00
a0b8c90870
un-indent a huge amount of code out of an anonymous namespace.
...
llvm-svn: 106500
2010-06-21 23:12:56 +00:00
b7dadb0e95
revert r106482
...
llvm-svn: 106499
2010-06-21 22:59:03 +00:00
3c1b3c61e9
Teach two-address lowering how to unfold a load to open up commuting
...
opportunities. For example, this lets it emit this:
movq (%rax), %rcx
addq %rdx, %rcx
instead of this:
movq %rdx, %rcx
addq (%rax), %rcx
in the case where %rdx has subsequent uses. It's the same number
of instructions, and usually the same encoding size on x86, but
it appears faster, and in general, it may allow better scheduling
for the load.
llvm-svn: 106493
2010-06-21 22:17:20 +00:00
510d9a3404
change parameter name to avoid confusion with global definition
...
llvm-svn: 106486
2010-06-21 21:28:07 +00:00
72df24037e
sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM.
...
Radar 8104310.
llvm-svn: 106484
2010-06-21 21:27:34 +00:00
523e554afa
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
...
being moved around away from the jump table it references. rdar://8104340
llvm-svn: 106483
2010-06-21 21:27:27 +00:00
374b2195f6
Add unpack and interleave AVX instructions, encoding tests cooming soon
...
llvm-svn: 106482
2010-06-21 21:21:48 +00:00
1fb4de8ec5
Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.
...
llvm-svn: 106481
2010-06-21 21:21:14 +00:00
79d2075e4a
"This is just a cosmetic change in MCAsmStreamer.cpp/EmitSymbolAttribute: all attributes have now a \t before and after, as done for '.type'.
...
This makes the output look consistent, as well as help some third party assemblers expecting the attributes to be in the second column."
Patch by Arnaud de Grandmaison!
llvm-svn: 106469
2010-06-21 20:35:01 +00:00
6dd51a2bb6
Remove isTwoAddress from SystemZ.
...
llvm-svn: 106467
2010-06-21 20:25:57 +00:00
d7a7356be6
Remove isTwoAddress from Sparc.
...
llvm-svn: 106466
2010-06-21 20:22:35 +00:00
c7927f2013
Remove isTwoAddress from Mips.
...
llvm-svn: 106465
2010-06-21 20:19:21 +00:00
fb008dfa05
Remove isTwoAddress from Blackfin.
...
llvm-svn: 106457
2010-06-21 20:13:37 +00:00
fa1b54d26e
Remove isTwoAddress from MSP430.
...
llvm-svn: 106455
2010-06-21 20:07:30 +00:00
dd41bba517
Use A.append(...) instead of A.insert(A.end(), ...) when A is a
...
SmallVector, and other SmallVector simplifications.
llvm-svn: 106452
2010-06-21 19:47:52 +00:00
0ca648d758
Make 80-column.
...
llvm-svn: 106448
2010-06-21 18:56:55 +00:00
98392f69e3
Remove isTwoAddress from PIC16.
...
llvm-svn: 106447
2010-06-21 18:55:01 +00:00
2401271217
Remove isTwoAddress from XCore.
...
llvm-svn: 106446
2010-06-21 18:51:38 +00:00
e159407231
Remove isTwoAddress from Alpha.
...
llvm-svn: 106445
2010-06-21 18:48:55 +00:00
ffdee30e90
Move several non-performance-critical member functinos out of line.
...
llvm-svn: 106444
2010-06-21 18:46:45 +00:00
e80de80270
Do not directly use function names to construct new name for named metadata.
...
"llvm.dbg.lv.~A" is not a valid name.
llvm-svn: 106438
2010-06-21 18:36:58 +00:00
29a894dd64
Move part of SSE 1 & 2 compare, shuffle and unpack instructions closely. Preparing them for refactoring and to the addition of their AVX forms
...
llvm-svn: 106437
2010-06-21 18:36:04 +00:00
20de4258f8
Add AVX regular (non-aliased ones) and,or,xor,andn packed instructions. They are already tested in the MC framework, no test needed
...
llvm-svn: 106436
2010-06-21 18:22:54 +00:00
d5c58b76ab
Fix PR 7433. Silly typo in non-Darwin ARM tail call
...
handling, plus correct R9 handling in that mode.
llvm-svn: 106434
2010-06-21 18:21:49 +00:00
bf572c7cea
Add some codegen patterns for x86_64-linux-gnu tls codegen matching.
...
Based on a patch by Patrick Marlier!
llvm-svn: 106433
2010-06-21 18:21:27 +00:00
97c8a6a928
early exit for dbg_value instructions
...
llvm-svn: 106430
2010-06-21 17:49:23 +00:00
74b5e3e0ae
remove some dead variables reported by clang++
...
llvm-svn: 106428
2010-06-21 17:20:18 +00:00
bbc29ea821
Revert r106422, which is breaking the non-fast-isel path.
...
llvm-svn: 106423
2010-06-21 16:02:28 +00:00
f64fdd69d0
More changes for non-top-down fast-isel.
...
Split the code for materializing a value out of
SelectionDAGBuilder::getValue into a helper function, so that it can
be used in other ways. Add a new getNonRegisterValue function which
uses it, for use in code which doesn't want a CopyFromReg even
when FuncMap.ValueMap already has an entry for it.
llvm-svn: 106422
2010-06-21 15:13:54 +00:00
0ab5a02579
Mark the SPU 'lr' instruction to never have side effects.
...
This allows the fast regiser allocator to remove redundant
register moves.
Update a set of tests that depend on the register allocator
to be linear scan.
llvm-svn: 106420
2010-06-21 15:08:16 +00:00
d7f50c118a
Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats.
...
llvm-svn: 106419
2010-06-21 14:42:19 +00:00
f91aff5f13
Do one lookup instead of two.
...
llvm-svn: 106415
2010-06-21 14:21:47 +00:00
7c58cf75fa
Generalize this to look in the regular ValueMap in addition to
...
the LocalValueMap, to make it more flexible when fast-isel isn't
proceding straight top-down.
llvm-svn: 106414
2010-06-21 14:17:46 +00:00
1cae86f704
Fix an unintentional commit. I think I typed "git svn dcommit" in the wrong branch.
...
I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.
llvm-svn: 106413
2010-06-21 13:31:32 +00:00
6f58190f6f
Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithm
...
used to choke llc with the attached test.
llvm-svn: 106411
2010-06-21 10:17:36 +00:00
c596baa56d
wip
...
llvm-svn: 106408
2010-06-21 02:17:34 +00:00
dcc7b6dcb6
Fix warning in no-asserts build.
...
llvm-svn: 106405
2010-06-20 20:27:42 +00:00
884a8fe5fa
Fix a crash caused by dereference of MBB.end(). rdar://8110842
...
llvm-svn: 106399
2010-06-20 00:54:38 +00:00
c515ab1eb2
Restore a call to rememberInstruction which was accidentally dropped
...
in refactoring.
llvm-svn: 106398
2010-06-19 22:50:35 +00:00
32655906e4
Add a TODO comment.
...
llvm-svn: 106397
2010-06-19 21:30:18 +00:00
51d00092b6
Include the use kind along with the expression in the key of the
...
use sharing map. The reconcileNewOffset logic already forces a
separate use if the kinds differ, so incorporating the kind in the
key means we can track more sharing opportunities.
More sharing means fewer total uses to track, which means smaller
problem sizes, which means the conservative throttles don't kick
in as often.
llvm-svn: 106396
2010-06-19 21:29:59 +00:00
297fb8b9fc
Don't include things in anonymous namespaces that don't need it.
...
llvm-svn: 106395
2010-06-19 21:21:39 +00:00
bf5c3d42ba
Use calloc instead of new/memset, it is more efficient when the set is very large.
...
llvm-svn: 106390
2010-06-19 17:00:31 +00:00
866971ed3d
Fix ScalarEvolution's "exhaustive" trip count evaluation code to avoid
...
assuming that loops are in canonical form, as ScalarEvolution doesn't
depend on LoopSimplify itself. Also, with indirectbr not all loops can
be simplified. This fixes PR7416.
llvm-svn: 106389
2010-06-19 14:17:24 +00:00
d277246137
Factor out duplicated code for reusing and inserting casts into
...
a helper function.
llvm-svn: 106388
2010-06-19 13:25:23 +00:00
4581434c27
Tidy.
...
llvm-svn: 106383
2010-06-19 05:33:57 +00:00
6d12973143
Remove a fixme comment that is no longer relevant.
...
llvm-svn: 106382
2010-06-19 05:32:41 +00:00
0ae08935f6
Fix error message to match function name.
...
llvm-svn: 106381
2010-06-19 05:32:09 +00:00
b86a3abcc7
Refactoring of regular logical packed instructions to prepare for AVX ones.
...
llvm-svn: 106375
2010-06-19 04:09:22 +00:00
8737b7d73d
Refactor aliased packed logical instructions, also add
...
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.
llvm-svn: 106374
2010-06-19 02:44:01 +00:00
7079bf815d
Ignore dbg_value's.
...
llvm-svn: 106373
2010-06-19 02:36:21 +00:00
a588049ce9
Move new sse 1 & 2 generic classes to a more appropriate place
...
llvm-svn: 106372
2010-06-19 01:32:46 +00:00
2787efd961
Remove unnecessary arguments
...
llvm-svn: 106371
2010-06-19 01:22:34 +00:00
00ada89f95
Add AVX packed intrinsics for MIN, MAX
...
llvm-svn: 106370
2010-06-19 01:17:05 +00:00
f3c01f3ef6
Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
...
llvm-svn: 106368
2010-06-19 01:01:32 +00:00
42105b2976
Finish ripping isTwoAddress out of X86. Some mindless formatting
...
and operand renaming to help.
The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.
llvm-svn: 106367
2010-06-19 00:37:40 +00:00
1e205f6b1c
Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions
...
llvm-svn: 106366
2010-06-19 00:37:31 +00:00
c60cecd88b
rip out dead code.
...
llvm-svn: 106365
2010-06-19 00:34:14 +00:00
e808a78ac1
fix rdar://7873482 by teaching the instruction encoder to emit
...
segment prefixes. Daniel wrote most of this patch.
llvm-svn: 106364
2010-06-19 00:34:00 +00:00
e5fcd333da
Indentation and remove dead code.
...
llvm-svn: 106362
2010-06-19 00:11:54 +00:00
1888f11887
Clean up: remove now unnecessary Constraints
...
llvm-svn: 106361
2010-06-19 00:09:27 +00:00
5fc43eb186
Silence compiler warnings.
...
llvm-svn: 106360
2010-06-19 00:02:06 +00:00
502c4fe61c
more refactoring! yay! big win over the intrinsics
...
llvm-svn: 106359
2010-06-19 00:00:22 +00:00
6bdbdb5544
Remove isTwoAddress from here too.
...
llvm-svn: 106358
2010-06-18 23:56:07 +00:00
66d2d57d9b
Fix typo, SSE1 should be used by XS, not SSE2
...
llvm-svn: 106357
2010-06-18 23:53:27 +00:00
3577c1b811
Remove isTwoAddress from 64-bit files.
...
llvm-svn: 106356
2010-06-18 23:51:21 +00:00
119824ed4d
Move ARM if-conversion before post-ra scheduling.
...
llvm-svn: 106355
2010-06-18 23:32:07 +00:00
8693650422
Teach regular and fast isel to set dead flags on unused implicit defs
...
on calls and similar instructions.
llvm-svn: 106353
2010-06-18 23:28:01 +00:00
2bfad417a1
Apply some refactor to packed instructions
...
llvm-svn: 106349
2010-06-18 23:13:35 +00:00
4f0781c9b3
Update cmake list.
...
llvm-svn: 106348
2010-06-18 23:12:10 +00:00
285935939d
Thumb2 hazard recognizer.
...
llvm-svn: 106347
2010-06-18 23:11:35 +00:00
678927e0b1
Only run CoalesceExtSubRegs when we can expect LiveIntervalAnalysis to clean up
...
the inserted INSERT_SUBREGs after us.
llvm-svn: 106345
2010-06-18 23:10:20 +00:00
2d51c7c592
Allow ARM if-converter to be run after post allocation scheduling.
...
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
llvm-svn: 106344
2010-06-18 23:09:54 +00:00
a57c2885cf
back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)
...
llvm-svn: 106342
2010-06-18 23:03:10 +00:00
6860bb7796
Enable Expand handling of atomics for subtargets that can't do them inline.
...
llvm-svn: 106336
2010-06-18 22:35:32 +00:00
07f4fa8198
TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREG
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instructions, but it doesn't really understand live ranges, so the first
INSERT_SUBREG uses an implicitly defined register.
Fix it in LiveVariableAnalysis by adding the <undef> flag.
llvm-svn: 106333
2010-06-18 22:29:44 +00:00
cf9e8a987f
Fix an inverted condition.
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llvm-svn: 106330
2010-06-18 22:17:13 +00:00
871439abd2
Use the new 'defm' class inheritance in SSE
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llvm-svn: 106327
2010-06-18 22:10:11 +00:00
f5d62535a5
Fix cross initialization compilation error.
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llvm-svn: 106324
2010-06-18 22:01:37 +00:00
c0e0d85b18
Teach iff-converter to properly count # of dups. It was not skipping over dbg_value's which resulted in non-duplicated instructions being deleted. rdar://8104384.
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llvm-svn: 106323
2010-06-18 21:52:57 +00:00
d64dfc1568
Add Expand-to-libcall support for additional atomics. This covers the usual
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entries used by llvm-gcc. *_[U]MIN and such can be added later if needed.
This enables the front ends to simplify handling of the atomic intrinsics by
removing the target-specific decision about which targets can handle the
intrinsics.
llvm-svn: 106321
2010-06-18 21:43:38 +00:00
a92e41a50a
Rewrite chained if's as switches and replace assertions with llvm_unreachable
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(as suggested in radar 8104405).
llvm-svn: 106318
2010-06-18 21:32:42 +00:00
589ffb4902
Fix ARM/Thumb reversal in previous attempt.
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llvm-svn: 106314
2010-06-18 21:07:47 +00:00
22a212f97c
When using ADDri to get the address of a stack object, 255 is a conservative
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limit on the offset that can be materialized without using the register
scavenger.
llvm-svn: 106312
2010-06-18 20:59:25 +00:00
a46d607545
Make this comment less specific.
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llvm-svn: 106311
2010-06-18 20:45:41 +00:00
af4903d6ee
Fix X86FastISel's address-mode folding to stay within the
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original basic block. This avoids trouble with examining
instructions in other basic blocks which haven't been
assigned registers yet.
llvm-svn: 106310
2010-06-18 20:44:47 +00:00
a06c2f79fc
An attempt to fix the problem Anton reported with
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ARM tail calls. Don't know if it works, but it
doesn't break Darwin.
llvm-svn: 106309
2010-06-18 20:44:28 +00:00
24ceda8eb0
Revert r106304 (105548 and friends), which are the SCEVComplexityCompare
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optimizations. There is still some nondeterminism remaining.
llvm-svn: 106306
2010-06-18 19:54:20 +00:00
4c807fca97
Reapply 105540, 105542, and 105548, and revert r105732.
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llvm-svn: 106304
2010-06-18 19:26:04 +00:00
45073042eb
Reapply 105546.
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llvm-svn: 106302
2010-06-18 19:12:32 +00:00
9136d9fbf8
Reapply 105544.
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llvm-svn: 106301
2010-06-18 19:09:27 +00:00
c1570dda5c
Enable tail calls on ARM by default, with some
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basic tests.
This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
B.W <label in other function>
which it has not seen before, at least from llvm-based
compilers. I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.
llvm-svn: 106299
2010-06-18 19:00:18 +00:00
e5457c275d
Don't leak RegClass2VRegMap, which is now a new[] array instead of a
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std::vector.
llvm-svn: 106298
2010-06-18 18:54:05 +00:00
882bb2984e
Start TargetRegisterClass indices at 0 instead of 1, so that
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MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.
llvm-svn: 106296
2010-06-18 18:13:55 +00:00
3ac52b3e43
Last round of changes for ARM tail calls.
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Not turning them on yet.
llvm-svn: 106295
2010-06-18 18:13:11 +00:00
f82c8fcc58
Fix PR7372: Conditional branches (at least on ARM) are treated as predicated,
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so when IfConverter::CopyAndPredicateBlock checks to see if it should ignore
an instruction because it is a branch, it should not check if the branch is
predicated.
This case (when IgnoreBr is true) is only relevant from IfConvertTriangle,
where new branches are inserted after the block has been copied and predicated.
If the original branch is not removed, we end up with multiple conditional
branches (possibly conflicting) at the end of the block. Aside from any
immediate errors resulting from that, this confuses the AnalyzeBranch functions
so that the branches are not analyzable. That in turn causes the IfConverter to
think that the "Simple" pattern can be applied, and things go downhill fast
because the "Simple" pattern does _not_ apply if the block can fall through.
This is pretty fragile. If there are other degenerate cases where AnalyzeBranch
fails, but where the block may still fall through, the IfConverter should not
perform its "Simple" if-conversion. But, I don't know how to do that with the
current AnalyzeBranch interface, so for now, the best thing seems to be to
avoid creating branches that AnalyzeBranch cannot handle.
Evan, please review!
llvm-svn: 106291
2010-06-18 17:07:23 +00:00
b9f91667e1
Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
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does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.
llvm-svn: 106289
2010-06-18 16:49:33 +00:00
9f58b3e106
Don't bother calling releaseMemory before destroying the DominatorTreeBase.
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llvm-svn: 106287
2010-06-18 16:09:11 +00:00
7edb39cc6b
Minor code simplifications.
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llvm-svn: 106286
2010-06-18 16:00:29 +00:00
6e681a5fbe
Give NamedRegionTimer an Enabled flag, allowing all its clients to
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switch from this:
if (TimePassesIsEnabled) {
NamedRegionTimer T(Name, GroupName);
do_something();
} else {
do_something(); // duplicate the code, this time without a timer!
}
to this:
{
NamedRegionTimer T(Name, GroupName, TimePassesIsEnabled);
do_something();
}
llvm-svn: 106285
2010-06-18 15:56:31 +00:00
96ca25eba5
Don't replace the old Ordering object with a new one; just clear()
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the old one.
llvm-svn: 106284
2010-06-18 15:40:58 +00:00
a4f46b3ef8
Don't call clear() on DbgInfo when it's going to be deleted anyway.
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Don't replace the old DbgInfo with a new one when clear() on the
old one is sufficient.
llvm-svn: 106283
2010-06-18 15:36:18 +00:00
92c11acdb8
Change UpdateNodeOperands' operand and return value from SDValue to
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SDNode *, since it doesn't care about the ResNo value.
llvm-svn: 106282
2010-06-18 15:30:29 +00:00
3d8a9d7490
Remove getIntegerSCEV; it's redundant with getConstant, and getConstant
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is more consistent with the ConstantInt API.
llvm-svn: 106281
2010-06-18 14:33:50 +00:00
c3479f5342
Delete unused variables.
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llvm-svn: 106280
2010-06-18 14:32:32 +00:00
f1d8304fe3
Eliminate unnecessary uses of getZExtValue().
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llvm-svn: 106279
2010-06-18 14:22:04 +00:00
35b6f9a929
isValueValidForType can be a static member function.
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llvm-svn: 106278
2010-06-18 14:01:07 +00:00
67d25f91c5
Some assorted isTwoAddress -> Constraints cleanup.
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llvm-svn: 106273
2010-06-18 02:41:19 +00:00
c61056a421
Handle execution entrypoints with non-integer return types.
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Fix from Russel Power in PR7284.
llvm-svn: 106271
2010-06-18 02:01:10 +00:00
f3aea7aecf
Disable indvars on loops when LoopSimplify form is not available.
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This fixes PR7333.
llvm-svn: 106267
2010-06-18 01:35:11 +00:00
99ba4dac59
Don't maintain a set of deleted nodes; instead, use a HandleSDNode
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to track a node over CSE events. This fixes PR7368.
llvm-svn: 106266
2010-06-18 01:24:29 +00:00
2323168705
Add {mix,max}{ss,sd}{rr,rm} AVX forms.
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llvm-svn: 106264
2010-06-18 01:12:56 +00:00
b92156d5e4
Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,
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which is faster, simpler, and less surprising.
llvm-svn: 106263
2010-06-18 01:05:21 +00:00
8ba26b48bb
Fix a typo in a comment.
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llvm-svn: 106260
2010-06-18 00:53:08 +00:00
0883789ec4
Handle ext(ext(x)) -> ext(x) immediately, since it's simple.
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llvm-svn: 106256
2010-06-18 00:08:30 +00:00
8f5954f42c
Simplify this code.
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llvm-svn: 106254
2010-06-17 23:34:09 +00:00
6b98f7129f
Use new tablegen resources in SSE tablegen code. This will
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be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction
llvm-svn: 106251
2010-06-17 23:05:30 +00:00
0125b6410a
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
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addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
llvm-svn: 106243
2010-06-17 22:43:56 +00:00
0ed5b460dc
add missing break. inconsequential as the code shouldn't be reached, but
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for correctness' sake, it should be there.
llvm-svn: 106229
2010-06-17 17:58:54 +00:00
3aeae8aeeb
Add entries for Expanding atomic intrinsics to libcalls. Just a placeholder
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for the moment. The implementation of the libcall will follow.
Currently, the llvm-gcc knows when the intrinsics can be correctly handled by
the back end and only generates them in those cases, issuing libcalls directly
otherwise. That's too much coupling. The intrinsics should always be
generated and the back end decide how to handle them, be it with a libcall,
inline code, or whatever. This patch is a step in that direction.
rdar://8097623
llvm-svn: 106227
2010-06-17 17:50:54 +00:00
5712c77c89
Thumb1 and any pre-v6 ARM target should use the libcall expansion of
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ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.
llvm-svn: 106204
2010-06-17 02:02:03 +00:00
ba451e80dc
ISD::MEMBARRIER should lower to a libcall (__sync_synchronize) if the target
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sets the legalize action to Expand.
llvm-svn: 106203
2010-06-17 02:00:53 +00:00
6e758c97fd
simplify code a bit and add a more explanatory assert for cases that
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previously would result in 'cannot yet select' errors.
llvm-svn: 106199
2010-06-17 01:37:00 +00:00
dd6a4cabf6
Add the entire range of DW_OP_lit[0..31], DW_OP_reg[0..31], and
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DW_OP_breg[0..31] to Dwarf.h.
Add "DW_" prefix to the llvm::dwarf::*String methods which did not
already have them in Dwarf.cpp.
llvm-svn: 106197
2010-06-17 01:23:24 +00:00
29b58afdf1
Hack to let the move lowering handle dynamic-no-pic absolute moves of
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TLVP:
movl _a@TLVP, %eax
Daniel: Please review if you get a chance.
llvm-svn: 106194
2010-06-17 00:51:48 +00:00
Benjamin Kramer