5e88700f28
Move SSE3 Move patterns to a more appropriate section
...
Add AVX SSE3 packed horizontal and & sub instructions
llvm-svn: 107405
2010-07-01 17:35:02 +00:00
886ee33a38
Add AVX SSE3 packed addsub instructions
...
llvm-svn: 107404
2010-07-01 17:08:18 +00:00
d2965c10a1
Temporarily disable on-demand fast-isel.
...
llvm-svn: 107393
2010-07-01 12:15:30 +00:00
9dc154bcb4
reformulate CallSite::getCallee to adapt to CallInst::ArgOffset, and make it work even if CallInst::op_* are private
...
llvm-svn: 107390
2010-07-01 10:41:37 +00:00
42b7ee15f5
Use FuncInfo's isExportedInst accessor method instead of
...
doing the work manually.
llvm-svn: 107384
2010-07-01 03:57:05 +00:00
85e02e9340
Rename CreateRegForValue to CreateReg, and change its argument
...
from a Value to a Type, because it doesn't actually care about
the Value.
llvm-svn: 107383
2010-07-01 03:55:39 +00:00
4d29fd85f9
Fast isel no longer needs DeadMachineInstrElim to clean up after it.
...
llvm-svn: 107381
2010-07-01 03:49:59 +00:00
aef3d140b7
Teach fast-isel to avoid loading a value from memory when it's already
...
available in a register. This is pretty primitive, but it reduces the
number of instructions in common testcases by 4%.
llvm-svn: 107380
2010-07-01 03:49:38 +00:00
722f5fc567
Enable on-demand fast-isel.
...
llvm-svn: 107377
2010-07-01 02:58:57 +00:00
207624edb0
Fix X86FastISel's add folding to actually work, and not fall back
...
to SelectionDAG.
llvm-svn: 107376
2010-07-01 02:58:21 +00:00
a7a0c83563
Add AVX SSE3 replicate and convert instructions
...
llvm-svn: 107375
2010-07-01 02:33:39 +00:00
7937d5606d
Teach X86FastISel to fold constant offsets and scaled indices in
...
the same address.
llvm-svn: 107373
2010-07-01 02:27:15 +00:00
d432223163
Reapply r106422, splitting the code for materializing a value out of
...
SelectionDAGBuilder::getValue into a helper function, with fixes to
use DenseMaps safely.
llvm-svn: 107371
2010-07-01 01:59:43 +00:00
9576645a84
Don't use operator[] here, because it's not desirable to insert a default
...
value if the search fails.
llvm-svn: 107368
2010-07-01 01:33:21 +00:00
05166740eb
- Add AVX SSE2 Move doubleword and quadword instructions.
...
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
llvm-svn: 107365
2010-07-01 01:20:06 +00:00
22fa66cf2b
80-col violation.
...
llvm-svn: 107361
2010-07-01 01:00:27 +00:00
4721ad855e
Trailing whitespace.
...
llvm-svn: 107360
2010-07-01 01:00:22 +00:00
8656a4549a
Add memory operand folding support to InlineSpiller.
...
llvm-svn: 107355
2010-07-01 00:13:04 +00:00
bde96ad23e
Add support for rematerialization to InlineSpiller.
...
llvm-svn: 107351
2010-06-30 23:03:52 +00:00
e0dfb98ea0
Use the catch-all selectors we already found when converting them to use the
...
correct catch-all value. This saves having to iterate through all of the
selectors in the program again.
llvm-svn: 107345
2010-06-30 22:49:53 +00:00
e74c78d539
lowerinvoke needs to handle aggregate function args like sjlj eh does.
...
llvm-svn: 107335
2010-06-30 22:22:59 +00:00
e8c97a7cd7
Handle array and vector typed parameters in sjljehprepare like we do
...
structs. rdar://8145832
llvm-svn: 107332
2010-06-30 22:20:38 +00:00
db735cbbab
Remove all debug info related named mdnodes.
...
llvm-svn: 107323
2010-06-30 21:29:00 +00:00
caf9b3ab7d
grammar tweak in comment.
...
llvm-svn: 107321
2010-06-30 21:27:56 +00:00
f638f4ff84
In ScalarEvolution::forgetValue, eliminate any SCEVUnknown
...
entries associated with the value being erased in the
folding set map. These entries used to be harmless, because
a SCEVUnknown doesn't store any information about its Value*,
so having a new Value allocated at the old Value's address
wasn't a problem. But now that ScalarEvolution is storing more
information about values, this is no longer safe.
llvm-svn: 107316
2010-06-30 20:21:12 +00:00
d0eacf715f
Move MOVD/MODQ code around, creating sections for each of them
...
llvm-svn: 107308
2010-06-30 18:49:10 +00:00
59e1cae377
Some fool committed without testing (or even building) first.
...
llvm-svn: 107307
2010-06-30 18:41:20 +00:00
cbcebe2950
Add AVX SSE2 mask creation and conditional store instructions
...
llvm-svn: 107306
2010-06-30 18:38:10 +00:00
c39d3497c8
Remember to track spill slot uses in VirtRegMap when inserting loads and stores.
...
LocalRewriter::runOnMachineFunction uses this information to mark dead spill
slots.
This means that InlineSpiller now also works for functions that spill.
llvm-svn: 107302
2010-06-30 18:19:08 +00:00
5c768e4915
Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable
...
llvm-svn: 107300
2010-06-30 18:06:01 +00:00
c0cca7fdda
Revert the part of r107257 which introduced new logic for using
...
nsw and nuw flags from IR Instructions. On further consideration,
this isn't valid.
llvm-svn: 107298
2010-06-30 17:27:11 +00:00
945a347478
Remove an unused variable. The call to getRoot has side-effects, so
...
this could break something (but doesn't seem to).
llvm-svn: 107295
2010-06-30 17:22:28 +00:00
d079c91683
Add AVX SSE2 packed integer extract/insert instructions
...
llvm-svn: 107293
2010-06-30 17:03:03 +00:00
7b90966d4a
Rather than giving SmallPtrSetImpl a member field SmallArray which is magically
...
replaced by a bigger array in SmallPtrSet (by overridding it), instead just use a
pointer to the start of the storage, and have SmallPtrSet pass in the value to use.
This has the disadvantage that SmallPtrSet becomes bigger by one pointer. It has
the advantage that it no longer uses tricky C++ rules, and is clearly correct while
I'm not sure the previous version was. This was inspired by g++-4.6 pointing out
that SmallPtrSetImpl was writing off the end of SmallArray, which it was. Since
SmallArray is replaced with a bigger array in SmallPtrSet, the write was still to
valid memory. But it was writing off the end of the declared array type - sounds
kind of dubious to me, like it sounded dubious to g++-4.6. Maybe g++-4.6 is wrong
and this construct is perfectly valid and correctly compiled by all compilers, but
I think it is better to avoid the whole can of worms by avoiding this construct.
llvm-svn: 107285
2010-06-30 15:02:37 +00:00
647d9c9797
use ArgOperand API
...
llvm-svn: 107282
2010-06-30 13:45:50 +00:00
12ca3d9fac
use ArgOperand API
...
llvm-svn: 107280
2010-06-30 13:03:37 +00:00
f69acfe133
use ArgOperand API
...
llvm-svn: 107279
2010-06-30 12:55:46 +00:00
74470192d7
use ArgOperand API
...
llvm-svn: 107278
2010-06-30 12:42:43 +00:00
d50572802e
use ArgOperand API
...
llvm-svn: 107277
2010-06-30 12:40:35 +00:00
3390e746fa
use CallSite::arg_end instead of CallInst::op_end
...
llvm-svn: 107276
2010-06-30 12:39:23 +00:00
3abd881bea
use getArgOperand (corrected by CallInst::ArgOffset) instead of getOperand
...
llvm-svn: 107275
2010-06-30 12:38:26 +00:00
743b3fd196
use getArgOperand (corrected by CallInst::ArgOffset) instead of getOperand
...
llvm-svn: 107273
2010-06-30 09:19:23 +00:00
f628ecd15f
use getNumArgOperands instead of getNumOperands
...
llvm-svn: 107272
2010-06-30 09:17:53 +00:00
fe252e6fa0
use getArgOperand instead of getOperand
...
llvm-svn: 107271
2010-06-30 09:16:16 +00:00
8ae3095286
use getArgOperand instead of getOperand
...
llvm-svn: 107270
2010-06-30 09:15:28 +00:00
e9acc46f65
use getArgOperand instead of getOperand
...
llvm-svn: 107269
2010-06-30 09:14:26 +00:00
16206132b6
Improve ScalarEvolution's nsw and nuw preservation.
...
llvm-svn: 107257
2010-06-30 07:16:37 +00:00
9396b42ca4
When computing a new ConservativeResult, intersect it with
...
the old one instead of replacing it, to be more precise.
llvm-svn: 107256
2010-06-30 06:58:35 +00:00
0865966440
Rework scev-aa's basic computation so that it doesn't depend
...
on ScalarEvolution successfully folding and preserving
range information for both A-B and B-A. Now, if it gets
either one, it's sufficient.
llvm-svn: 107249
2010-06-30 06:12:16 +00:00
37f145c55b
Simplify.
...
llvm-svn: 107248
2010-06-30 06:09:46 +00:00
e82689fea2
Add AVX SSE2 integer unpack instructions
...
llvm-svn: 107246
2010-06-30 04:06:39 +00:00
ec0115c9b7
Add AVX SSE2 packed integer shuffle instructions
...
llvm-svn: 107245
2010-06-30 03:47:56 +00:00
5364655e02
Remove trailing whitespace, no functionality changes.
...
llvm-svn: 107244
2010-06-30 03:40:54 +00:00
51ceead19c
Small refactoring of SSE2 packed integer shuffle instructions
...
llvm-svn: 107243
2010-06-30 03:29:36 +00:00
be792feb8b
Add AVX SSE2 pack with saturation integer instructions
...
llvm-svn: 107241
2010-06-30 02:30:25 +00:00
2686ea4555
Add AVX SSE2 integer packed compare instructions
...
llvm-svn: 107240
2010-06-30 02:21:09 +00:00
2e2caefff9
- Add AVX form of all SSE2 logical instructions
...
- Add VEX encoding bits to x86 MRM0r-MRM7r
llvm-svn: 107238
2010-06-30 01:58:37 +00:00
c5b3109bec
Do not construct DIE for already processed MDNode.
...
llvm-svn: 107237
2010-06-30 01:40:11 +00:00
b3b89c3bc0
Use skipInstruction() as a simpler way of iterating over instructions using SrcReg
...
llvm-svn: 107234
2010-06-30 00:30:36 +00:00
08baf59da1
Use clEnumValN macro to work around keyword clash
...
llvm-svn: 107233
2010-06-30 00:24:51 +00:00
648df7bf64
Add variables into a scope before constructing scope DIE otherwise variables won't be included DIE tree.
...
llvm-svn: 107228
2010-06-30 00:11:08 +00:00
f888911932
Begin implementation of an inline spiller.
...
InlineSpiller inserts loads and spills immediately instead of deferring to
VirtRegMap. This is possible now because SlotIndexes allows instructions to be
inserted and renumbered.
This is work in progress, and is mostly a copy of TrivialSpiller so far. It
works very well for functions that don't require spilling.
llvm-svn: 107227
2010-06-29 23:58:39 +00:00
3f71ddfaad
Add *several* AVX integer packed binop instructions
...
llvm-svn: 107225
2010-06-29 23:47:49 +00:00
ae36b1ed42
Fix ScalarEvolution's tripcount computation for chains of loops
...
where each loop's induction variable's start value is the exit
value of a preceding loop.
llvm-svn: 107224
2010-06-29 23:43:06 +00:00
3632171750
Revert r107205 and r107207.
...
llvm-svn: 107215
2010-06-29 22:34:52 +00:00
be30551600
Print InlinedAt location.
...
llvm-svn: 107214
2010-06-29 22:29:15 +00:00
e34471bb31
Add another bswap idiom that isn't matched.
...
llvm-svn: 107213
2010-06-29 22:22:22 +00:00
7fee95a38e
Move SSE2 Packed Integer instructions around, and create specific sections for each of them
...
llvm-svn: 107211
2010-06-29 22:12:16 +00:00
c728518bfe
Print InlinedAt location.
...
llvm-svn: 107208
2010-06-29 21:51:32 +00:00
ba21eb8054
Add AVX Move Aligned/Unaligned packed integers
...
llvm-svn: 107206
2010-06-29 21:25:12 +00:00
1767723dbe
Introducing the "linker_weak" linkage type. This will be used for Objective-C
...
metadata types which should be marked as "weak", but which the linker will
remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is
defined like this:
.globl l_objc_msgSend_fixup_alloc
.weak_definition l_objc_msgSend_fixup_alloc
.section __DATA, __objc_msgrefs, coalesced
.align 3
l_objc_msgSend_fixup_alloc:
.quad _objc_msgSend_fixup
.quad L_OBJC_METH_VAR_NAME_1
This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".
llvm-svn: 107205
2010-06-29 21:24:00 +00:00
30689a3a7f
Add AVX ld/st XCSR register.
...
Add VEX encoding bits for MRMXm x86 form
llvm-svn: 107204
2010-06-29 20:35:48 +00:00
24bc1b5b2f
Do not hardcode DW_AT_stmt_list value.
...
Inspired by Artur Pietrek.
llvm-svn: 107202
2010-06-29 20:17:53 +00:00
be157b0ea8
Add support for encoding VDUP (ARM core register) instructions.
...
llvm-svn: 107201
2010-06-29 20:13:29 +00:00
dadea5b178
Fix the handling of partial redefines in the fast register allocator.
...
A partial redefine needs to be treated like a tied operand, and the register
must be reloaded while processing use operands.
This fixes a bug where partially redefined registers were processed as normal
defs with a reload added. The reload could clobber another use operand if it was
a kill that allowed register reuse.
llvm-svn: 107193
2010-06-29 19:15:30 +00:00
d91d5bfc95
Fix a register scavenger crash when dealing with undefined subregs.
...
The LowerSubregs pass needs to preserve implicit def operands attached to
EXTRACT_SUBREG instructions when it replaces those instructions with copies.
llvm-svn: 107189
2010-06-29 18:42:49 +00:00
a4575f5b31
Add AVX non-temporal stores
...
llvm-svn: 107178
2010-06-29 18:22:01 +00:00
1be9e7c0b6
Fix whitespace style.
...
llvm-svn: 107175
2010-06-29 18:12:34 +00:00
049f4ffab1
Move non-temporal movs to their own section
...
llvm-svn: 107168
2010-06-29 17:42:37 +00:00
ab0819e10d
Add support for encoding NEON VMOV (from core register to scalar) instructions.
...
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.
llvm-svn: 107167
2010-06-29 17:34:07 +00:00
21a9433e9e
Add sqrt, rsqrt and rcp AVX instructions
...
llvm-svn: 107166
2010-06-29 17:26:30 +00:00
5bee07ec68
skip dbg_value instructions
...
llvm-svn: 107154
2010-06-29 16:55:24 +00:00
83b993a977
The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add
...
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.
llvm-svn: 107147
2010-06-29 16:25:11 +00:00
eab748d409
use ArgOperand API
...
llvm-svn: 107145
2010-06-29 16:17:26 +00:00
17f1ca8793
Return Changed. This required setting Changed if dbg metadata
...
is stripped off. Currently set unconditionally, since the API
does not provide a way of working out if anything was actually
stripped off.
llvm-svn: 107142
2010-06-29 14:52:10 +00:00
83d1dd637a
It seems clear that this should return Changed.
...
llvm-svn: 107141
2010-06-29 14:49:35 +00:00
38a7d7cbc3
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
...
of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
llvm-svn: 107140
2010-06-29 14:02:34 +00:00
d34bb4e9b0
getMachineBasicBlockAddress returns a uintptr_t - don't truncate
...
to unsigned only to extend back to a pointer sized value on the
next line.
llvm-svn: 107139
2010-06-29 13:34:20 +00:00
a85a90773c
The variable ValueSize is set to 1 on both code paths, and then
...
ignored! Remove it.
llvm-svn: 107138
2010-06-29 13:30:08 +00:00
1245e4c07d
The variable "Value" is carefully set to Layout.getSymbolAddress,
...
but then not actually used - maybe a bug? Remove the variable.
llvm-svn: 107137
2010-06-29 13:26:33 +00:00
5667a08468
Remove unused calls to Lexer.getLoc and the pointless variable HasFillExpr.
...
llvm-svn: 107136
2010-06-29 13:24:40 +00:00
193bb1ee6a
Remove pointless variable LastDef.
...
llvm-svn: 107135
2010-06-29 13:23:22 +00:00
257eba4df7
Remove unused variable Loc and pointless variables unified_syntax
...
and thumb_mode.
llvm-svn: 107133
2010-06-29 13:04:35 +00:00
e73d64c2cf
use ArgOperand APIs
...
llvm-svn: 107132
2010-06-29 13:03:46 +00:00
78ad27ca2b
Remove an unused and a pointless variable.
...
llvm-svn: 107131
2010-06-29 13:00:29 +00:00
67bfa9d109
Remove pointless and unused variables.
...
llvm-svn: 107130
2010-06-29 12:48:49 +00:00
eec74583ca
encode operand initializations (at fixed index)
...
in terms of Op<> and ArgOffset. This works for
values of {0, 1} for ArgOffset.
Please note that ArgOffset will become 0 soon and
will go away eventually.
llvm-svn: 107129
2010-06-29 11:41:38 +00:00
67aa21d7b5
Remove a pointless variable.
...
llvm-svn: 107128
2010-06-29 11:39:45 +00:00
6d28e73acc
Remove initialized but otherwise unused variables.
...
llvm-svn: 107127
2010-06-29 11:22:26 +00:00
80b7bc042a
Use a more obvious way to avoid compiling functions which are only used when XDEBUG is enabled.
...
llvm-svn: 107125
2010-06-29 10:03:11 +00:00
b1adb88d05
Jump through some silly hoops to make GCC accept that a function may not always
...
be called.
llvm-svn: 107124
2010-06-29 06:46:00 +00:00
b59dd8f10a
PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.
...
llvm-svn: 107122
2010-06-29 05:38:36 +00:00
0c30739cbb
Change if-cvt options to something that actually as useable.
...
llvm-svn: 107121
2010-06-29 05:37:59 +00:00
907673c48d
When processing loops for scheduling latencies (used for live outs on loop
...
back-edges), make sure not to include dbg_value instructions in the count.
Closing in on the end of rdar://7797940
llvm-svn: 107119
2010-06-29 04:48:13 +00:00
90db61d638
Just as its not safe to blindly transfer the nsw bit from an add
...
instruction to an add scev, it's not safe to blindly transfer the
inbounds flag from a gep instruction to an nsw on the scev for the
gep.
llvm-svn: 107117
2010-06-29 01:41:41 +00:00
de736a6494
Refactoring of arithmetic instruction classes with unary operator
...
llvm-svn: 107116
2010-06-29 01:33:09 +00:00
c1eccbc468
When no memoperands are present, assume unaligned, volatile.
...
llvm-svn: 107114
2010-06-29 01:13:07 +00:00
1e5da550e5
Reapply my if-conversion cleanup from svn r106939 with fixes.
...
There are 2 changes relative to the previous version of the patch:
1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch. Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).
The change relative to the previous patch is:
@@ -1036,10 +1036,6 @@
IterIfcvt = false;
}
- // RemoveExtraEdges won't work if the block has an unanalyzable branch,
- // which is typically the case for IfConvertSimple, so explicitly remove
- // CvtBBI as a successor.
- BBI.BB->removeSuccessor(CvtBBI->BB);
RemoveExtraEdges(BBI);
// Update block info. BB can be iteratively if-converted.
2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised. The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond. I added the following change to check for
that:
@@ -1276,7 +1276,18 @@
// tail, add a unconditional branch to it.
if (TailBB) {
BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
- if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+ bool CanMergeTail = !TailBBI.HasFallThrough;
+ // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+ // check if there are any other predecessors besides those.
+ unsigned NumPreds = TailBB->pred_size();
+ if (NumPreds > 1)
+ CanMergeTail = false;
+ else if (NumPreds == 1 && CanMergeTail) {
+ MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+ if (*PI != BBI1->BB && *PI != BBI2->BB)
+ CanMergeTail = false;
+ }
+ if (CanMergeTail) {
MergeBlocks(BBI, TailBBI);
TailBBI.IsDone = true;
} else {
With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.
llvm-svn: 107110
2010-06-29 00:55:23 +00:00
0824affeff
Add an Intraprocedural form of BasicAliasAnalysis, which aims to
...
properly handles instructions and arguments defined in different
functions, or across recursive function iterations.
llvm-svn: 107109
2010-06-29 00:50:39 +00:00
d6a091a4d4
Described the missing AVX forms of SSE2 convert instructions
...
llvm-svn: 107108
2010-06-29 00:36:02 +00:00
3d12ff797b
Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is
...
the same as ARM except that the condition code field is always set to ARMCC::AL.
llvm-svn: 107107
2010-06-29 00:26:13 +00:00
269a89fd3a
Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they
...
can't be changed arbitrarily by the DAGCombiner without checking if it is
running after legalization.
llvm-svn: 107097
2010-06-28 23:40:25 +00:00
4469a892b4
Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead
...
of the Subtarget.
llvm-svn: 107086
2010-06-28 22:23:17 +00:00
1de21ec498
Use DW_FORM_addr for DW_AT_entry_pc.
...
llvm-svn: 107085
2010-06-28 22:22:47 +00:00
17feb07c53
In asm's, output operands with matching input constraints
...
have to be registers, per gcc documentation. This affects
the logic for determining what "g" should lower to. PR 7393.
A couple of existing testcases are affected.
llvm-svn: 107079
2010-06-28 22:09:45 +00:00
e233dda2e2
Added the darwin .secure_log_unique and .secure_log_reset directives.
...
llvm-svn: 107077
2010-06-28 21:45:58 +00:00
e697a6f24f
Constant fold x == undef to undef.
...
llvm-svn: 107074
2010-06-28 21:30:07 +00:00
f31c004666
tidy up style. no functional change.
...
llvm-svn: 107073
2010-06-28 21:29:17 +00:00
7c34ece501
Fix Value::stripPointerCasts and BasicAA to avoid trouble on
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code in unreachable blocks, which have have use-def cycles.
This fixes PR7514.
llvm-svn: 107071
2010-06-28 21:16:52 +00:00
544317dfda
Refactor encoding function for NEON 1-register with modified immediate format.
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llvm-svn: 107070
2010-06-28 21:16:30 +00:00
584387d5e3
Support Thumb mode encoding of NEON instructions.
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llvm-svn: 107068
2010-06-28 21:12:19 +00:00
0a5bb081cc
Reduce indentation via early exit. NFC.
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llvm-svn: 107067
2010-06-28 21:08:32 +00:00
d10b2af260
Include inlined function in list of processed subprograms.
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llvm-svn: 107065
2010-06-28 20:53:04 +00:00
ee6e29aa72
new, no longer brain-dead, r106907
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llvm-svn: 107060
2010-06-28 20:26:00 +00:00
ffd628ec0a
After physreg coalescing, physical registers might not have live ranges where
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you would expect.
Don't assert on that case, just give up.
This fixes PR7513.
llvm-svn: 107046
2010-06-28 19:39:57 +00:00
0d94d7af78
Add more special treatment for inline asm in RegAllocFast.
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When an instruction has tied operands and physreg defines, we must take extra
care that the tied operands conflict with neither physreg defs nor uses.
The special treatment is given to inline asm and instructions with tied operands
/ early clobbers and physreg defines.
This fixes PR7509.
llvm-svn: 107043
2010-06-28 18:34:34 +00:00
7f103a2653
Fix thinko.
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llvm-svn: 107042
2010-06-28 18:33:48 +00:00
51f2908328
Pull in the libCrashReporterClient.a information with a warning comment.
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Remove library check and regenerate configure.
llvm-svn: 107028
2010-06-28 18:25:51 +00:00
f3b2db68c6
Preserve deleted function's local variables' debug info.
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Radar 8122864.
llvm-svn: 107027
2010-06-28 18:25:03 +00:00
5b1370ee80
use ArgOperand API
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llvm-svn: 107017
2010-06-28 16:50:57 +00:00
e23efeef10
use ArgOperand API
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llvm-svn: 107016
2010-06-28 16:45:00 +00:00
18c5bae727
employ CallInst::ArgOffset (for now)
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llvm-svn: 107015
2010-06-28 16:43:57 +00:00
cd09869dfc
simplify: we have solid argument iterator range
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llvm-svn: 107014
2010-06-28 16:40:52 +00:00
875a296011
Generalize AAEval so that it can be used both per-function and
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interprocedurally. Note that as of this writing, existing alias
analysis passes are not prepared to be used interprocedurally.
llvm-svn: 107013
2010-06-28 16:01:37 +00:00
b8c058cbb0
Revert r106907, "make sure to handle dbg_value instructions in the middle of the
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block, not...", it caused a bunch of nightly test regressions.
llvm-svn: 107009
2010-06-28 15:47:17 +00:00
2dd4307e45
use setArgOperand
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llvm-svn: 107004
2010-06-28 12:31:35 +00:00
ec60adf161
use CallInst::ArgOffset
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llvm-svn: 107003
2010-06-28 12:30:07 +00:00
2de43a7c5c
use ArgOperand API and CallInst::ArgOffset
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llvm-svn: 107002
2010-06-28 12:29:20 +00:00
4300fc77ae
use cached value
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llvm-svn: 107000
2010-06-28 11:20:42 +00:00
fb6f22f010
Remove dead code.
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llvm-svn: 106990
2010-06-28 05:59:13 +00:00
f7869a4b81
Use named MDNode, llvm.dbg.sp, to collect subprogram info. This will be used to emit local variable's debug info of deleted functions.
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llvm-svn: 106989
2010-06-28 05:53:08 +00:00
7ea5fc0794
minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change.
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llvm-svn: 106988
2010-06-28 04:27:01 +00:00
81170d23de
Do not forget last element, function, while creating Subprogram definition MDNode from subprogram declare MDNode.
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llvm-svn: 106985
2010-06-27 21:04:31 +00:00
25a843fcd2
minor cleanup to SROA: when lowering type unsafe accesses to
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large integers, the first inserted value would always create
an 'or X, 0'. Even though this is trivially zapped by
instcombine, don't bother creating this pointless instruction.
llvm-svn: 106979
2010-06-27 07:58:26 +00:00
2041abd958
When splitting a VAARG, remember its alignment.
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This produces terrible but correct code.
llvm-svn: 106952
2010-06-26 18:22:20 +00:00
418e64a385
Revert my if-conversion cleanup since it caused a bunch of nightly test
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regressions.
--- Reverse-merging r106939 into '.':
U test/CodeGen/Thumb2/thumb2-ifcvt3.ll
U lib/CodeGen/IfConversion.cpp
llvm-svn: 106951
2010-06-26 17:47:06 +00:00
3a5cb69cb8
Fix PR7328: when turning a tail recursion into a loop, need to preserve
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the returned value after the tail call if it differs from other return
values. The optimal thing to do would be to introduce a phi node for
the return value, but for the moment just fix the miscompile.
llvm-svn: 106947
2010-06-26 12:53:31 +00:00
7d4038dd88
use ArgOperand API
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llvm-svn: 106946
2010-06-26 12:17:21 +00:00
c2ac8c4261
use ArgOperand API
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llvm-svn: 106945
2010-06-26 12:09:10 +00:00
83205af3fa
use ArgOperand API
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llvm-svn: 106944
2010-06-26 11:51:52 +00:00
Bruno Cardoso Lopes