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14541 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes 6d122aef97 Add AVX SSE4.2 instructions 
llvm-svn: 107752
 2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes 3df55b2d6f Use only one multiclass to pinsrq instructions 
llvm-svn: 107750
 2010-07-07 01:43:01 +00:00
Bruno Cardoso Lopes fd6c808154 Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes 
llvm-svn: 107749
 2010-07-07 01:33:38 +00:00
Bruno Cardoso Lopes 8f5472a8e8 Add AVX SSE4.1 insertps, ptest and movntdqa instructions 
llvm-svn: 107747
 2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes 6430c7350d Add AVX SSE4.1 extractps and pinsr instructions 
llvm-svn: 107746
 2010-07-07 01:01:13 +00:00
Bob Wilson 5bc8a79e7f Also use REG_SEQUENCE for VTBX instructions. 
llvm-svn: 107743
 2010-07-07 00:08:54 +00:00
Jim Grosbach 3198483851 Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where 
they've been tested to work.

llvm-svn: 107742
 2010-07-07 00:07:57 +00:00
Bruno Cardoso Lopes f3116ebe96 Add AVX SSE4.1 Extract Integer instructions 
llvm-svn: 107740
 2010-07-07 00:07:24 +00:00
Jim Grosbach dc0a0659be By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather 
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.

llvm-svn: 107734
 2010-07-06 23:44:52 +00:00
Bob Wilson 3ed511bc6b Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be 
allocated to consecutive registers.

llvm-svn: 107730
 2010-07-06 23:36:25 +00:00
Dale Johannesen ce65663330 Accept RIP-relative symbols with 'i' constraint, and 
print the (%rip) only if the 'a' modifier is present.
PR 7528.

llvm-svn: 107727
 2010-07-06 23:27:00 +00:00
Jakob Stoklund Olesen 48deb12593 Track defs for all aliases in NEONMoveFix. 
This means that an instruction defining an S register will affect the domain of
the parent D register.

llvm-svn: 107725
 2010-07-06 23:26:23 +00:00
Bruno Cardoso Lopes 1f9ad516c6 Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107723
 2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes 35702d27c4 Add part of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107720
 2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes 13f0260e76 Fix comment from previous patch 
llvm-svn: 107717
 2010-07-06 22:38:32 +00:00
Bruno Cardoso Lopes e2bd058d32 Add AVX vblendvpd, vblendvps and vpblendvb instructions 
Update VEX encoding to support those new instructions

llvm-svn: 107715
 2010-07-06 22:36:24 +00:00
Dan Gohman ee0cb70381 CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext. 
SelectBasicBlock doesn't needs its BasicBlock argument.

llvm-svn: 107712
 2010-07-06 22:19:37 +00:00
Devang Patel a3ca21b228 Propagate debug loc. 
llvm-svn: 107710
 2010-07-06 22:08:15 +00:00
Bob Wilson 4c1ca29039 Represent NEON load/store alignments in bytes, not bits. 
llvm-svn: 107701
 2010-07-06 21:26:18 +00:00
Dan Gohman 3439629239 Reapply r107655 with fixes; insert the pseudo instruction into 
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.

llvm-svn: 107691
 2010-07-06 20:24:04 +00:00
Devang Patel 23a7593534 Fix PR7545 crash. 
llvm-svn: 107678
 2010-07-06 18:18:32 +00:00
Rafael Espindola 7c510aa7bc Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion 
if profitable.

llvm-svn: 107673
 2010-07-06 16:24:34 +00:00
Dan Gohman f4f04107ef Revert r107655. 
llvm-svn: 107668
 2010-07-06 15:49:48 +00:00
Dan Gohman 2b2a1c3c86 Make getMinimalPhysRegClass' comment mention what makes it different 
from getPhysicalRegisterRegClass.

llvm-svn: 107660
 2010-07-06 15:31:55 +00:00
Dan Gohman 12205645a6 Fix a bunch of custom-inserter functions to handle the case where 
the pseudo instruction is not at the end of the block.

llvm-svn: 107655
 2010-07-06 15:18:19 +00:00
Eric Christopher 2ad0c779c3 Fix up -fstack-protector on linux to use the segment 
registers.  Split out testcases per architecture and os
now.

Patch from Nelson Elhage.

llvm-svn: 107640
 2010-07-06 05:18:56 +00:00
Eric Christopher d429846eca Have the X86 backend use Triple instead of a string and some enums. 
llvm-svn: 107625
 2010-07-05 19:26:33 +00:00
Kalle Raiskila d5ac287140 Remove some unused/redundant code. 
llvm-svn: 107622
 2010-07-05 18:40:09 +00:00
Chris Lattner c4a7073db3 more tidying. 
llvm-svn: 107615
 2010-07-05 05:53:14 +00:00
Chris Lattner 7b909ac785 some notes about suboptimal insertps's 
llvm-svn: 107613
 2010-07-05 05:48:41 +00:00
Chris Lattner 6d60a14251 rip out even more sporadic v2f32 support. 
llvm-svn: 107610
 2010-07-05 04:38:33 +00:00
Chris Lattner feb2467bf4 rip out the various v2f32 "mmx" handling logic, now that 
v2f32 is illegal on x86.

llvm-svn: 107609
 2010-07-05 04:36:27 +00:00
Chris Lattner 45cc4d74a3 Just rip v2f32 support completely out of the X86 backend. In 
the example in the testcase, we now generate:

_test1:                                 ## @test1
	movss	4(%esp), %xmm0
	addss	8(%esp), %xmm0
	movl	12(%esp), %eax
	movss	%xmm0, (%eax)
	ret

instead of:

_test1:                                                     ## @test1
	subl	$20, %esp
	movl	24(%esp), %eax
	movq	%mm0, (%esp)
	movq	%mm0, 8(%esp)
	movss	(%esp), %xmm0
	addss	12(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$20, %esp
	ret

v2f32 support did not work reliably because most of the X86
backend didn't know it was legal.  It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode.  If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32.  However,
we generally don't try very hard to be abi compatible on gcc
extended vectors. 

llvm-svn: 107601
 2010-07-04 23:07:25 +00:00
Chris Lattner 681b926d54 fix PR7518 - terrible codegen of <2 x float>, by only marking 
v2f32 as legal in 32-bit mode.  It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.

llvm-svn: 107600
 2010-07-04 22:57:10 +00:00
Chris Lattner cb948d3329 indentation 
llvm-svn: 107599
 2010-07-04 22:56:10 +00:00
Bill Wendling 199cacf179 Revert r107583. I no longer think that this is the way to solve the problem. 
llvm-svn: 107585
 2010-07-04 09:16:57 +00:00
Bill Wendling 701aa053b9 Mark sse_load_f32 and sse_load_f64 as having memory operands 
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.

llvm-svn: 107583
 2010-07-04 08:59:55 +00:00
Eli Friedman c8f595212f Minor amendment to switch-lowering improvement. 
llvm-svn: 107569
 2010-07-03 08:43:32 +00:00
Eli Friedman 836fdbc85b Note switch-lowering inefficiency. 
llvm-svn: 107565
 2010-07-03 07:38:12 +00:00
Bruno Cardoso Lopes ca99012ac0 Add AVX SSE4.1 blend, mpsadbw and vdp 
llvm-svn: 107560
 2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes bc75502f09 Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions 
llvm-svn: 107558
 2010-07-03 01:15:47 +00:00
Bruno Cardoso Lopes fc9cdc4d61 Add AVX SSE4.1 Horizontal Minimum and Position instruction 
llvm-svn: 107552
 2010-07-03 00:49:21 +00:00
Evan Cheng 0664a67fe1 Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false. 
llvm-svn: 107550
 2010-07-03 00:40:23 +00:00
Bruno Cardoso Lopes 621c85b038 Add AVX SSE4.1 round instructions 
llvm-svn: 107549
 2010-07-03 00:37:44 +00:00
Bruno Cardoso Lopes 5b59c1bf1f Simple refactoring of SSE4.1 instructions, making room for the AVX forms 
llvm-svn: 107540
 2010-07-02 23:27:59 +00:00
Bruno Cardoso Lopes c7111fd355 - Add support for the rest of AVX SSE3 instructions 
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode

llvm-svn: 107523
 2010-07-02 22:06:54 +00:00
Evan Cheng c3525dc0fd Remove early IT block formation. It's not used. 
llvm-svn: 107513
 2010-07-02 21:07:09 +00:00
Evan Cheng 0ce84486c3 - Two-address pass should not assume unfolding is always successful. 
- X86 unfolding should check if the instructions being unfolded has memoperands.
  If there is no memoperands, then it must assume conservative alignment. If this
  would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
  etc. should not unfold the instruction.

llvm-svn: 107509
 2010-07-02 20:36:18 +00:00
Gabor Greif 9da02a83e9 beautify output 
llvm-svn: 107500
 2010-07-02 19:26:28 +00:00
Gabor Greif e537ddbdb4 use ArgOperand API 
llvm-svn: 107498
 2010-07-02 19:08:46 +00:00