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39610 Commits

Author SHA1 Message Date
Gabor Greif a22e8148d4 conditionalize by CallInst::ArgOffset 
llvm-svn: 107767
 2010-07-07 10:34:03 +00:00
Duncan Sands 408bb192de Rename "Release" builds as "Release+Asserts"; rename "Release-Asserts" 
builds to "Release".  The default build is unchanged (optimization on,
assertions on), however it is now called Release+Asserts.  The intent
is that future LLVM releases released via llvm.org will be Release builds
in the new sense, i.e. will have assertions disabled (currently they have
assertions enabled, for a more than 20% slowdown).  This will bring them
in line with MacOS releases, which ship with assertions disabled.  It also
means that "Release" now means the same things in make and cmake builds:
cmake already disables assertions for "Release" builds AFAICS.

llvm-svn: 107758
 2010-07-07 07:48:00 +00:00
Bruno Cardoso Lopes 6d122aef97 Add AVX SSE4.2 instructions 
llvm-svn: 107752
 2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes 3df55b2d6f Use only one multiclass to pinsrq instructions 
llvm-svn: 107750
 2010-07-07 01:43:01 +00:00
Bruno Cardoso Lopes fd6c808154 Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes 
llvm-svn: 107749
 2010-07-07 01:33:38 +00:00
Bruno Cardoso Lopes 8f5472a8e8 Add AVX SSE4.1 insertps, ptest and movntdqa instructions 
llvm-svn: 107747
 2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes 6430c7350d Add AVX SSE4.1 extractps and pinsr instructions 
llvm-svn: 107746
 2010-07-07 01:01:13 +00:00
Jakob Stoklund Olesen f0e551d4f4 Revert "Remove references to INSERT_SUBREG after de-SSA" r107725. 
Buildbot breakage.

llvm-svn: 107744
 2010-07-07 00:32:25 +00:00
Bob Wilson 5bc8a79e7f Also use REG_SEQUENCE for VTBX instructions. 
llvm-svn: 107743
 2010-07-07 00:08:54 +00:00
Jim Grosbach 3198483851 Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where 
they've been tested to work.

llvm-svn: 107742
 2010-07-07 00:07:57 +00:00
Bruno Cardoso Lopes f3116ebe96 Add AVX SSE4.1 Extract Integer instructions 
llvm-svn: 107740
 2010-07-07 00:07:24 +00:00
Jim Grosbach dc0a0659be By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather 
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.

llvm-svn: 107734
 2010-07-06 23:44:52 +00:00
Jakob Stoklund Olesen e2d3067f6b Remove references to INSERT_SUBREG after de-SSA 
llvm-svn: 107732
 2010-07-06 23:40:35 +00:00
Bob Wilson 3ed511bc6b Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be 
allocated to consecutive registers.

llvm-svn: 107730
 2010-07-06 23:36:25 +00:00
Dale Johannesen ce65663330 Accept RIP-relative symbols with 'i' constraint, and 
print the (%rip) only if the 'a' modifier is present.
PR 7528.

llvm-svn: 107727
 2010-07-06 23:27:00 +00:00
Jakob Stoklund Olesen 70ee3ecd33 Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass. 
INSERT_SUBREG will now only appear in SSA machine instructions.

Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant
since partial redef COPY instructions appear.

llvm-svn: 107726
 2010-07-06 23:26:25 +00:00
Jakob Stoklund Olesen 48deb12593 Track defs for all aliases in NEONMoveFix. 
This means that an instruction defining an S register will affect the domain of
the parent D register.

llvm-svn: 107725
 2010-07-06 23:26:23 +00:00
Bruno Cardoso Lopes 1f9ad516c6 Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107723
 2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes 35702d27c4 Add part of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107720
 2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes 13f0260e76 Fix comment from previous patch 
llvm-svn: 107717
 2010-07-06 22:38:32 +00:00
Bruno Cardoso Lopes e2bd058d32 Add AVX vblendvpd, vblendvps and vpblendvb instructions 
Update VEX encoding to support those new instructions

llvm-svn: 107715
 2010-07-06 22:36:24 +00:00
Dan Gohman ee0cb70381 CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext. 
SelectBasicBlock doesn't needs its BasicBlock argument.

llvm-svn: 107712
 2010-07-06 22:19:37 +00:00
Devang Patel a3ca21b228 Propagate debug loc. 
llvm-svn: 107710
 2010-07-06 22:08:15 +00:00
Bob Wilson 4c1ca29039 Represent NEON load/store alignments in bytes, not bits. 
llvm-svn: 107701
 2010-07-06 21:26:18 +00:00
Jakob Stoklund Olesen 15fed3bd30 One more case assuming that subregs have live ranges. 
llvm-svn: 107700
 2010-07-06 21:13:03 +00:00
Jakob Stoklund Olesen bcf3409107 Fix buildbot breakage where a def is missing. 
llvm-svn: 107698
 2010-07-06 21:06:39 +00:00
Devang Patel b36df17b08 Add fixme. 
llvm-svn: 107697
 2010-07-06 21:05:17 +00:00
Jakob Stoklund Olesen a64c0a3d22 Be more forgiving when calculating alias interference for physreg coalescing. 
It is OK for an alias live range to overlap if there is a copy to or from the
physical register. CoalescerPair can work out if the copy is coalescable
independently of the alias.

This means that we can join with the actual destination interval instead of
using the getOrigDstReg() hack. It is no longer necessary to merge clobber
ranges into subregisters.

llvm-svn: 107695
 2010-07-06 20:31:51 +00:00
Dan Gohman 3439629239 Reapply r107655 with fixes; insert the pseudo instruction into 
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.

llvm-svn: 107691
 2010-07-06 20:24:04 +00:00
Eric Christopher dfc8b745a2 Fix to 80-col. 
llvm-svn: 107684
 2010-07-06 18:35:20 +00:00
Devang Patel 23a7593534 Fix PR7545 crash. 
llvm-svn: 107678
 2010-07-06 18:18:32 +00:00
Rafael Espindola 7c510aa7bc Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion 
if profitable.

llvm-svn: 107673
 2010-07-06 16:24:34 +00:00
Chris Lattner dde2ba0b60 tighten up this code. 
llvm-svn: 107670
 2010-07-06 15:59:27 +00:00
Dan Gohman f4f04107ef Revert r107655. 
llvm-svn: 107668
 2010-07-06 15:49:48 +00:00
Dan Gohman 4e49b59dad Add versions of OutputArgReg, AnalyzeReturn, and AnalyzeCallOperands 
which do not depend on SelectionDAG.

llvm-svn: 107666
 2010-07-06 15:39:54 +00:00
Dan Gohman 2b2a1c3c86 Make getMinimalPhysRegClass' comment mention what makes it different 
from getPhysicalRegisterRegClass.

llvm-svn: 107660
 2010-07-06 15:31:55 +00:00
Anton Korobeynikov e415230477 Fix a major regression on COFF targets introduced by r103267: 'discardable' section means that it is used only during the program load and can be discarded afterwards. 
This way *only* debug sections can be discarded, but not the opposite. Seems like the copy-and-pasto from ELF code, since there it contains the reverse flag ('alloc').

llvm-svn: 107658
 2010-07-06 15:24:56 +00:00
Dan Gohman 1e33b18e28 Add some more TODO comments. 
llvm-svn: 107657
 2010-07-06 15:23:00 +00:00
Dan Gohman f855b39edd Add a comment. 
llvm-svn: 107656
 2010-07-06 15:21:57 +00:00
Dan Gohman 12205645a6 Fix a bunch of custom-inserter functions to handle the case where 
the pseudo instruction is not at the end of the block.

llvm-svn: 107655
 2010-07-06 15:18:19 +00:00
Eric Christopher 2ad0c779c3 Fix up -fstack-protector on linux to use the segment 
registers.  Split out testcases per architecture and os
now.

Patch from Nelson Elhage.

llvm-svn: 107640
 2010-07-06 05:18:56 +00:00
Nick Lewycky dace239949 Detabify this file. 
llvm-svn: 107637
 2010-07-06 03:53:43 +00:00
Eric Christopher d429846eca Have the X86 backend use Triple instead of a string and some enums. 
llvm-svn: 107625
 2010-07-05 19:26:33 +00:00
Kalle Raiskila d5ac287140 Remove some unused/redundant code. 
llvm-svn: 107622
 2010-07-05 18:40:09 +00:00
Chris Lattner c4a7073db3 more tidying. 
llvm-svn: 107615
 2010-07-05 05:53:14 +00:00
Chris Lattner 7b909ac785 some notes about suboptimal insertps's 
llvm-svn: 107613
 2010-07-05 05:48:41 +00:00
Chris Lattner 2c0315a0f3 random tidying 
llvm-svn: 107612
 2010-07-05 05:36:21 +00:00
Chris Lattner 6d60a14251 rip out even more sporadic v2f32 support. 
llvm-svn: 107610
 2010-07-05 04:38:33 +00:00
Chris Lattner feb2467bf4 rip out the various v2f32 "mmx" handling logic, now that 
v2f32 is illegal on x86.

llvm-svn: 107609
 2010-07-05 04:36:27 +00:00
Jakob Stoklund Olesen ac0a210789 Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG. 
llvm-svn: 107602
 2010-07-04 23:24:23 +00:00