c6078c87d1
Fixes a rewriter bug rewriting call to a byref
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block pointer nested inside a block. // rdar:// 9204669
llvm-svn: 128747
2011-04-01 23:08:13 +00:00
1e1010f56f
Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that
...
all the instruction have:
let Inst{31-27} = 0b1110; // non-predicated
Before, the ARM decoder was confusing:
> 0x40 0xf3 0xb8 0x80
as:
Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcs pc, r8, r0, asr #6
since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.
Now, the AR decoder behaves correctly:
> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt
Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcshi pc, r8, r0, asr #6
>
rdar://problem/9223094
llvm-svn: 128746
2011-04-01 22:32:51 +00:00
8b94c295c3
Fix comment.
...
llvm-svn: 128745
2011-04-01 22:29:18 +00:00
5cad45307e
Tweaks to the icmp+sext-to-shifts optimization to address Frits' comments:
...
- Localize the check if an icmp has one use to a place where we know we're
introducing something that's likely more expensive than a sext from i1.
- Add an assert to make sure a case that would lead to a miscompilation is
folded away earlier.
- Fix a typo.
llvm-svn: 128744
2011-04-01 22:22:11 +00:00
88530e6568
Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009
...
llvm-svn: 128743
2011-04-01 22:09:28 +00:00
3d9df607ba
Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed.
...
llvm-svn: 128742
2011-04-01 21:56:02 +00:00
56d9ef53a2
Simplifies logic for printing target flags.
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llvm-svn: 128741
2011-04-01 21:41:06 +00:00
25ec0d38e1
CMake: remove debug code from previous commit.
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llvm-svn: 128740
2011-04-01 21:39:38 +00:00
975ddf8035
When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately.
...
llvm-svn: 128739
2011-04-01 21:07:39 +00:00
16d970950f
Driver/Darwin: Tweak simulator link logic a bit more to be closer to GCC.
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llvm-svn: 128738
2011-04-01 21:02:42 +00:00
360c369967
LDRD/STRD instructions should print both Rt and Rt2 in the asm string.
...
llvm-svn: 128736
2011-04-01 20:26:57 +00:00
5f74b39764
tlbgen/MC: StringRef's to temporary objects considered harmful.
...
llvm-svn: 128735
2011-04-01 20:23:52 +00:00
3dfb80afbf
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
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as invalid.
llvm-svn: 128734
2011-04-01 20:21:38 +00:00
ac2d5657a6
Fix build.
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llvm-svn: 128733
2011-04-01 20:15:16 +00:00
d121765e64
InstCombine: Turn icmp + sext into bitwise/integer ops when the input has only one unknown bit.
...
int test1(unsigned x) { return (x&8) ? 0 : -1; }
int test3(unsigned x) { return (x&8) ? -1 : 0; }
before (x86_64):
_test1:
andl $8, %edi
cmpl $1, %edi
sbbl %eax, %eax
ret
_test3:
andl $8, %edi
cmpl $1, %edi
sbbl %eax, %eax
notl %eax
ret
after:
_test1:
shrl $3, %edi
andl $1, %edi
leal -1(%rdi), %eax
ret
_test3:
shll $28, %edi
movl %edi, %eax
sarl $31, %eax
ret
llvm-svn: 128732
2011-04-01 20:09:10 +00:00
398b8c5faf
InstCombine: Move (sext icmp) transforms into their own method. No intended functionality change.
...
llvm-svn: 128731
2011-04-01 20:09:03 +00:00
8b1bca1998
Add comments.
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llvm-svn: 128730
2011-04-01 19:57:01 +00:00
8d68ebd42a
Assign node order numbers to results of call instruction lowering. This should improve src line debug info when sdisel is used. rdar://9199118
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llvm-svn: 128728
2011-04-01 19:42:22 +00:00
cde00a55c8
Fix assignment of -fPIC to CMAKE_C_FLAGS. Configure llvm-config.in.in
...
with the contents of CMAKE_C(XX)_FLAGS too, else `llvm-config
--c(xx)flags' doesn't tell the absolute truth.
This comes from PR9603 and is based on a patch by Ryuta Suzuki!
llvm-svn: 128727
2011-04-01 19:36:06 +00:00
5bba75f1a7
ANother rewrite bug, rewriting a call of
...
__byref block. // rdar://9204669
llvm-svn: 128726
2011-04-01 19:19:28 +00:00
1ffe23464a
Do not try calculate the size of forward-declared template type array.
...
llvm-svn: 128725
2011-04-01 19:02:33 +00:00
e625ba46b7
Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly.
...
llvm-svn: 128724
2011-04-01 18:57:38 +00:00
c8e6f5110c
Don't store reports when scan-build's build command matches /autogen/ (same as configure).
...
llvm-svn: 128723
2011-04-01 18:47:06 +00:00
fe6fba3fe6
Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
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rdar://problem/9219356
llvm-svn: 128722
2011-04-01 18:26:38 +00:00
2b4d9b7f11
Some OpenBSD patches from Amit Kulkarni.
...
llvm-svn: 128721
2011-04-01 18:18:34 +00:00
ac4827fe05
Get rid of LONG_LONG_MAX and ULONG_LONG_MAX, and use LLONG_MAX and ULLONG_MAX
...
respectively.
llvm-svn: 128720
2011-04-01 18:14:08 +00:00
22430f4141
Update CMakeLists.txt
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Patch by arrowdoger.
llvm-svn: 128719
2011-04-01 18:03:58 +00:00
93f898f643
Add code for analyzing FP branches. Clean up branch Analysis functions.
...
llvm-svn: 128718
2011-04-01 17:39:08 +00:00
bb21fac250
Initialize HasVMLxForwarding.
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llvm-svn: 128709
2011-04-01 09:20:31 +00:00
e98f29df8b
Various Instructions' resizeOperands() methods are only used to grow the
...
list of operands. Simplify and rename them accordingly.
llvm-svn: 128708
2011-04-01 08:00:58 +00:00
a6a992a662
Add test case.
...
llvm-svn: 128707
2011-04-01 06:27:25 +00:00
0f86d6de50
FileCheck'ify test.
...
llvm-svn: 128706
2011-04-01 03:36:33 +00:00
2d3cdd686b
While testing dragonegg I noticed that isCastable and getCastOpcode
...
had gotten out of sync: isCastable didn't think it was possible to
cast the x86_mmx type to anything, while it did think it possible
to cast an i64 to x86_mmx.
llvm-svn: 128705
2011-04-01 03:34:54 +00:00
8a05f66139
Add annotations to tablegen-generated processor itineraries, or replace them with something meaningful. I want to be able to read and debug the generated tables.
...
llvm-svn: 128703
2011-04-01 02:22:47 +00:00
3d7e3daaa6
Fix an error in TreeTransform where we failed to copy the TemplateName's
...
location into a TemplateSpecializationTypeLoc. These were found using
a hand-written program to inspect every source location in
TemplateSpecializationTypeLocs and Valgrind. I don't know of any way to
test them in Clang's existing test suite sadly.
Example code that triggers the ElaboratedType case:
template <typename T> struct X1 {
template <typename U> struct X1_1 {
int x;
};
};
template <typename T, typename U> struct X2 {
typename X1<T>::template X1_1<U> B;
};
X2<char, int> x2;
The other fix was simply spotted by inspection. I audited all constructions of
[Dependent]TemplateSpecializationTypeLocs in TreeTransform.h, and the rest set
the TemplateNameLoc properly.
llvm-svn: 128702
2011-04-01 02:03:23 +00:00
db6ed64529
whitespace
...
llvm-svn: 128701
2011-04-01 01:56:55 +00:00
826342774e
IRgen: Reapply r128691 with a fix to ensure we don't increase alignment past
...
that of the array element type.
llvm-svn: 128698
2011-04-01 00:49:43 +00:00
7d90b1f883
Modify test_process_list()'s expect sub-strings to be up-to-date.
...
llvm-svn: 128697
2011-04-01 00:48:40 +00:00
bd76679700
Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.
...
rdar://8911343
llvm-svn: 128696
2011-04-01 00:42:02 +00:00
df2963ed46
Add TestSymbolAPI.py to test the newly added SBSymbol and SBAddress APIs:
...
lldb::SymbolType SBSymbol::GetType();
lldb::SectionType SBAddress::GetSectionType ();
lldb::SBModule SBAddress::GetModule ();
Also add an lldb::SBModule::GetUUIDString() API which is easier for Python
to work with in the test script.
llvm-svn: 128695
2011-04-01 00:35:55 +00:00
95bf0fd3ab
Added the ability to get a broadcaster event name for a given broadcaster
...
event.
Modified the ProcessInfo structure to contain all process arguments. Using the
new function calls on MacOSX allows us to see the full process name, not just
the first 16 characters.
Added a new platform command: "platform process info <pid> [<pid> <pid> ...]"
that can be used to get detailed information for a process including all
arguments, user and group info and more.
llvm-svn: 128694
2011-04-01 00:29:43 +00:00
ea6b81a2ad
Revert r128691, "IRgen: Improve GCC compatibility when dealing with packed
...
arrays by propagating", it's breaking test in ways I don't understand yet.
llvm-svn: 128693
2011-04-01 00:13:33 +00:00
d911f92c46
Remove unused variables
...
llvm-svn: 128692
2011-04-01 00:06:01 +00:00
417bf0f147
IRgen: Improve GCC compatibility when dealing with packed arrays by propagating
...
the array alignment to the array access.
- This is more or less the best we can do without having alignment present in
the type system, but is a long way from truly matching how GCC handles this.
llvm-svn: 128691
2011-03-31 23:32:15 +00:00
100f53fd25
Fix Thumb and Thumb2 tests to be register allocator independent.
...
llvm-svn: 128690
2011-03-31 23:31:50 +00:00
ab8305063b
Apply again changes to support ARM memory asm parsing. I removed
...
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
llvm-svn: 128689
2011-03-31 23:26:08 +00:00
6e597dc8e7
The basic register allocator must also use the inline spiller.
...
It is using a trivial rewriter that doesn't know how to insert spill code
requested by the standard spiller.
llvm-svn: 128688
2011-03-31 23:02:17 +00:00
0709342652
Provide a legal pointer register class when targeting thumb1.
...
The LocalStackSlotAllocation pass was creating illegal registers.
llvm-svn: 128687
2011-03-31 23:02:15 +00:00
903baeac27
Fix SystemZ tests
...
llvm-svn: 128686
2011-03-31 23:02:12 +00:00
8d543de400
Remove unneeded ExecutionContextScope variables.
...
llvm-svn: 128685
2011-03-31 23:01:21 +00:00
Fariborz Jahanian