ab0139cb90
Use reserve() to avoid vector reallocation.
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llvm-svn: 167991
2012-11-14 22:42:17 +00:00
62fc067518
Make sure to not get AVX code on an AVX-capable host. Revealed in r167967.
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llvm-svn: 167989
2012-11-14 22:24:01 +00:00
a54c14a922
test/CodeGen/Hexagon/postinc-load.ll: Suppress it for now. It triggered the failure on i686 hosts.
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llvm-svn: 167988
2012-11-14 22:22:37 +00:00
e373e82a5b
Few more small CellSPU removals.
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llvm-svn: 167987
2012-11-14 22:13:56 +00:00
aa3d19e782
Fix CMake build.
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llvm-svn: 167986
2012-11-14 22:10:47 +00:00
950d8703b1
Remove the CellSPU port.
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Approved by Chris Lattner.
llvm-svn: 167984
2012-11-14 22:09:20 +00:00
a89edf6a61
docs: Sphinxify TestingGuide
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llvm-svn: 167979
2012-11-14 21:09:30 +00:00
92987fb311
Support for [[ @LINE ]], [[@LINE+<offset>]], [[@LINE-<offset>]] expressions in
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FileCheck.
llvm-svn: 167978
2012-11-14 21:07:37 +00:00
d17df318c0
Fix invalid asserts, use llvm_unreachable instead.
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llvm-svn: 167976
2012-11-14 21:03:40 +00:00
902b137133
llvm/test/CodeGen/X86/memset.ll: FileCheck-ize, and add another case on +avx.
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llvm-svn: 167975
2012-11-14 21:01:40 +00:00
6649360860
Added multiclass for post-increment load instructions.
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llvm-svn: 167974
2012-11-14 20:38:48 +00:00
d71fb86aed
Force CPU in test so we don't accidentally get AVX code on an AVX-capable host.
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llvm-svn: 167973
2012-11-14 20:31:42 +00:00
542db4a0bc
canJoinPhys method doesn't modify CoalescerPair. Make it const.
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llvm-svn: 167972
2012-11-14 20:31:04 +00:00
317adfc8b7
Added %(line), %(line+<number>), %(line-<number>) substitutions to lit
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llvm-svn: 167971
2012-11-14 20:26:19 +00:00
e18e4add6c
Remove dead code.
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llvm-svn: 167970
2012-11-14 20:25:37 +00:00
2d92d8af25
Fix comment.
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llvm-svn: 167969
2012-11-14 20:21:29 +00:00
0c4468b5e6
Remove DOS line endings.
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llvm-svn: 167968
2012-11-14 20:18:34 +00:00
6293429b51
X86: Enable SSE memory intrinsics even when stack alignment is less than 16 bytes.
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The stack realignment code was fixed to work when there is stack realignment and
a dynamic alloca is present so this shouldn't cause correctness issues anymore.
Note that this also enables generation of AVX instructions for memset
under the assumptions:
- Unaligned loads/stores are always fast on CPUs supporting AVX
- AVX is not slower than SSE
We may need some tweaked heuristics if one of those assumptions turns out not to
be true.
Effectively reverts r58317. Part of PR2962.
llvm-svn: 167967
2012-11-14 20:08:40 +00:00
e9740a4692
Replace std::vector -> SmallVector in BBVectorize
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For now, this uses 8 on-stack elements. I'll need to do some profiling
to see if this is the best number.
Pointed out by Jakob in post-commit review.
llvm-svn: 167966
2012-11-14 19:53:27 +00:00
c17537e8f6
Update my email address and update the code ownership
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llvm-svn: 167965
2012-11-14 19:47:48 +00:00
a72e9f0140
FileCheck.rst: change formatting of code-like constructs to use a monospaced
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font. These were formatted in bold, but that's not correct.
llvm-svn: 167964
2012-11-14 19:42:32 +00:00
9f567c62f2
The code pattern "imm0_255_neg" is used for checking if an immediate value is a small negative number.
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This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of
a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag.
rdar://12028498
llvm-svn: 167963
2012-11-14 19:39:15 +00:00
6854008737
Add myself as code owner for NVPTX target
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llvm-svn: 167962
2012-11-14 19:36:27 +00:00
6468f0a9ef
docs: nuke GCCFEBuildInstrs.html
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llvm-svn: 167961
2012-11-14 19:34:48 +00:00
c6462aacd5
[NVPTX] Implement custom lowering of loads/stores for i1
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Loads from i1 become loads from i8 followed by trunc
Stores to i1 become zext to i8 followed by store to i8
Fixes PR13291
llvm-svn: 167948
2012-11-14 19:19:16 +00:00
a506f5b0fd
Fix comment
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llvm-svn: 167947
2012-11-14 19:17:44 +00:00
b619a4138d
Fix really stupid ARM EHABI info generation bug: we should not emit
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eh table and handler data if there are no landing pads in the function.
Patch by Logan Chien with some cleanups from me.
llvm-svn: 167945
2012-11-14 19:13:30 +00:00
754e396c65
Claim ownership.
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llvm-svn: 167943
2012-11-14 18:43:21 +00:00
1b7f0aba48
Fix the largest offender of determinism in BBVectorize
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Iterating over the children of each node in the potential vectorization
plan must happen in a deterministic order (because it affects which children
are erased when two children conflict). There was no need for this data
structure to be a map in the first place, so replacing it with a vector
is a small change.
I believe that this was the last remaining instance if iterating over the
elements of a Dense* container where the iteration order could matter.
There are some remaining iterations over std::*map containers where the order
might matter, but so long as the Value* for instructions in a block increase
with the order of the instructions in the block (or decrease) monotonically,
then this will appear to be deterministic.
llvm-svn: 167942
2012-11-14 18:38:11 +00:00
0c5a621b87
Sort the code owner list alphabetically. Add myself as lib/DebugInfo owner.
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llvm-svn: 167940
2012-11-14 18:17:45 +00:00
6f1f41b1ae
X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.
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When an instruction as written requires 32-bit mode and we're assembling
in 64-bit mode, or vice-versa, issue a more specific diagnostic about
what's wrong.
rdar://12700702
llvm-svn: 167937
2012-11-14 18:04:47 +00:00
1fc2002c93
s/assert/llvm_unreachable/
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llvm-svn: 167936
2012-11-14 17:58:11 +00:00
94b180fa52
Grab debug information for code ownership.
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llvm-svn: 167933
2012-11-14 17:33:40 +00:00
2b27170fdc
[TSan] fix indentation
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llvm-svn: 167928
2012-11-14 14:33:59 +00:00
00fd5257a2
Emit relocations from .debug_aranges to .debug_info for asm files
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llvm-svn: 167926
2012-11-14 09:55:38 +00:00
01860a620f
Revert some redundant parts of r142605.
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This seems like redundant leftovers from r142288 - exposing
TargetData::parseSpecifier to LLParser - which got reverted. Removes
redunant td != NULL checks in parseSpecifier, and simplifies the
interface to parseSpecifier and init.
llvm-svn: 167924
2012-11-14 09:04:56 +00:00
c4343f2c45
Set FFLOOR of vectors to expand to keep intruction selection from failing.
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llvm-svn: 167922
2012-11-14 08:11:25 +00:00
61b9e57c1e
Mark myself as owner of BBVectorize and PowerPC
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llvm-svn: 167921
2012-11-14 07:59:10 +00:00
ae1d30047c
Accepting ownership of scheduling.
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llvm-svn: 167917
2012-11-14 07:04:23 +00:00
a7f489d1ab
Factor out an overly replicated typecast. No functional change.
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llvm-svn: 167916
2012-11-14 06:41:09 +00:00
54c45ab570
Set FFLOOR for vectors to expand on CellSPU to keep instruction selection from failing on llvm.floor of a vector.
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llvm-svn: 167914
2012-11-14 05:56:30 +00:00
04a5cc39f4
Add newlines to end of debug messages.
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llvm-svn: 167913
2012-11-14 05:20:09 +00:00
c79532d101
Handle DAG CSE adding new uses during ReplaceAllUsesWith. Fixes PR14333.
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llvm-svn: 167912
2012-11-14 05:08:56 +00:00
5f265fb124
docs: Fix Sphinx toctree warning.
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llvm-svn: 167905
2012-11-14 01:49:23 +00:00
e42af3699b
Use TARGET2 relocation for TType references on ARM.
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Do some cleanup of the code while here.
Inspired by patch by Logan Chien!
llvm-svn: 167904
2012-11-14 01:47:00 +00:00
6c440b932e
docs: chmod -x HowToUseInstrMappings.rst
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llvm-svn: 167903
2012-11-14 01:41:58 +00:00
68e0b6afa8
Fix broken asserts. Also, spell 'indices' correctly.
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llvm-svn: 167894
2012-11-14 00:21:27 +00:00
4e92d5b9ff
[Object] Fix endianess bug by refactoring Archive::Symbol::getMember.
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llvm-svn: 167893
2012-11-14 00:04:13 +00:00
a43bcddc8d
use the getSplat API. Patch by Paul Redmond.
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llvm-svn: 167892
2012-11-14 00:02:13 +00:00
0f23b82147
Revert "Use the 'count' attribute instead of the 'upper_bound' attribute."
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temporarily as it is breaking the gdb bots.
This reverts commit r167806/e7ff4c14b157746b3e0228d2dce9f70712d1c126.
llvm-svn: 167886
2012-11-13 23:30:43 +00:00
Jakub Staszak