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6 Commits

Author SHA1 Message Date
Jim Grosbach 6600f520b0 ARM optional destination operand variants for VEXT instructions. 
llvm-svn: 146114
 2011-12-08 00:43:47 +00:00
Jim Grosbach 5ff64c7141 Tidy up. 
llvm-svn: 146113
 2011-12-08 00:41:54 +00:00
Jim Grosbach 131b45e632 ARM alternate size suffices for VTRN instructions. 
rdar://10435076

llvm-svn: 144694
 2011-11-15 20:49:46 +00:00
Bob Wilson c3ff538dcf Fix misspelled target triples in MC/ARM test commands. 
llvm-svn: 121901
 2010-12-15 22:14:01 +00:00
Owen Anderson bb81f80af6 Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead, 
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.

llvm-svn: 118183
 2010-11-03 18:16:27 +00:00
Owen Anderson e5271a935a Covert this test to .s form. 
llvm-svn: 117937
 2010-11-01 18:13:11 +00:00