Commit Graph

2533 Commits

Author SHA1 Message Date
Dan Gohman 1cbdcac409 Remove a redundant newline in the asm output for ELF .rodata sections.
llvm-svn: 37756
2007-06-27 15:09:47 +00:00
Dan Gohman e8c1e428f2 Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Dan Gohman a866514528 Generalize MVT::ValueType and associated functions to be able to represent
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.

llvm-svn: 37719
2007-06-25 16:23:39 +00:00
Dan Gohman 2e84e3f7b7 Make minor adjustments to whitespace and comments to reduce differences
between SSE1 instructions and their respective SSE2 analogues.

llvm-svn: 37718
2007-06-25 15:44:19 +00:00
Dan Gohman 33209bd6b8 Fix loadv2i32 to be loadv4i32, though it isn't actually used anywhere yet.
llvm-svn: 37717
2007-06-25 15:19:03 +00:00
Dan Gohman e33c4b739b Say AT&T instead of Intel in the comments for AT&T support.
llvm-svn: 37716
2007-06-25 15:11:25 +00:00
Dan Gohman 309d3d51b3 Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704
2007-06-22 14:59:07 +00:00
Dale Johannesen 485531ea9b Quote complex names for Darwin X86 and ARM.
llvm-svn: 37700
2007-06-22 00:54:56 +00:00
Dan Gohman 9e82064924 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Chris Lattner 944200be45 If a function is vararg, never pass inreg arguments in registers. Thanks to
Anton for half of this patch.

llvm-svn: 37641
2007-06-19 00:13:10 +00:00
Evan Cheng cea02ffd05 Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This can happen before DAGCombiner catches it.
llvm-svn: 37636
2007-06-19 00:02:56 +00:00
Dan Gohman c98815ba32 Define the pushq instruction for x86-64.
llvm-svn: 37625
2007-06-18 14:12:56 +00:00
Bill Wendling 094a4e813a Revert patch. It regresses:
define double @test2(i64 %A) {
   %B = bitcast i64 %A to double
   ret double %B
}

$ llvm-as < t.ll | llc -march=x86-64

before:

         .align  4
         .globl  _test2
_test2:
         movd %rdi, %xmm0
         ret

after:

_test2:
         subq $8, %rsp
         movq %rdi, (%rsp)
         movsd (%rsp), %xmm0
         addq $8, %rsp
         ret

llvm-svn: 37617
2007-06-16 23:57:15 +00:00
Bill Wendling cd9673e565 Fix a failure to bit_convert from integer GPR to MMX register.
llvm-svn: 37611
2007-06-16 06:17:31 +00:00
Dan Gohman 5c4413120f Rename MVT::getVectorBaseType to MVT::getVectorElementType.
llvm-svn: 37579
2007-06-14 22:58:02 +00:00
Dale Johannesen 616627b002 Do not treat FP_REG_KILL as terminator in branch analysis (X86).
llvm-svn: 37578
2007-06-14 22:03:45 +00:00
Dan Gohman 4a4a8eb00e Add a target hook to allow loads from constant pools to be rematerialized, and an
implementation for x86.

llvm-svn: 37576
2007-06-14 20:50:44 +00:00
Dan Gohman 3a8e2a8b2f Eliminate some redundant newlines in asm output.
llvm-svn: 37574
2007-06-14 15:00:27 +00:00
Dale Johannesen c68554683d Handle blocks with 2 unconditional branches in AnalyzeBranch.
llvm-svn: 37571
2007-06-13 17:59:52 +00:00
Chris Lattner 75372ad603 fix x86-64 mmx calling convention for real, which passes in integer gprs.
llvm-svn: 37534
2007-06-09 05:08:10 +00:00
Chris Lattner a4a49e37ab fix mmx handling bug
llvm-svn: 37533
2007-06-09 05:01:50 +00:00
Evan Cheng 5514bbef46 Add a utility routine to check for unpredicated terminator instruction.
llvm-svn: 37528
2007-06-08 21:59:56 +00:00
Evan Cheng 59ca6a846f Misuse of hasExternalLinkage(), should be checking isDeclaration().
llvm-svn: 37419
2007-06-04 18:54:57 +00:00
Dan Gohman 703e0f8608 Add explicit qualification for namespace MVT members.
llvm-svn: 37320
2007-05-24 14:33:05 +00:00
Bill Wendling 3fb7fdfded We only need to specify the most-implied feature for an architecture.
llvm-svn: 37275
2007-05-22 05:15:37 +00:00
Evan Cheng fc94eb66d2 BlockHasNoFallThrough() now returns true if block ends with a return instruction.
llvm-svn: 37266
2007-05-21 18:44:17 +00:00
Chris Lattner 7ea2df6e2a add a note
llvm-svn: 37239
2007-05-18 20:18:14 +00:00
Dan Gohman eefa83e67b Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE.
llvm-svn: 37234
2007-05-18 18:44:07 +00:00
Evan Cheng e20dd92792 RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
llvm-svn: 37193
2007-05-18 00:18:17 +00:00
Evan Cheng afa1cb6da3 Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector.
llvm-svn: 37173
2007-05-17 18:45:50 +00:00
Evan Cheng 632c3f01ed Added missing patterns for UNPCKH* and PUNPCKH*.
llvm-svn: 37172
2007-05-17 18:44:37 +00:00
Chris Lattner dade607f19 This is the correct fix for PR1427. This fixes mmx-shuffle.ll and doesn't
cause other regressions.

llvm-svn: 37160
2007-05-17 17:13:13 +00:00
Anton Korobeynikov 1ad4618715 Revert patch for PR1427. It breaks almost all vector tests.
llvm-svn: 37159
2007-05-17 07:50:14 +00:00
Chris Lattner 13f4bf5c5e add support for 128-bit integer add/sub
llvm-svn: 37154
2007-05-17 06:35:11 +00:00
Chris Lattner 6a5a46322f Fix PR1427 and test/CodeGen/X86/mmx-shuffle.ll
llvm-svn: 37141
2007-05-17 03:29:42 +00:00
Chris Lattner 888653cdba implement the missing maskmovq mmx intrinsic that akor hit.
llvm-svn: 37100
2007-05-16 06:08:17 +00:00
Chris Lattner c8798d085c fix subtle bugs in inline asm operand selection
llvm-svn: 37065
2007-05-15 01:28:08 +00:00
Anton Korobeynikov 13da17843c More DWARF-related things cleanup:
1. Fix PR1380
2. Apply Duncan's patch from PR1410
3. Insert workaround for "one personality function per module" as noted in PR1414
4. Emit correct debug frames for x86/linux. This partly fixes DebugInfo/2006-11-06-StackTrace.cpp: stack trace is
shown correctly, but arguments for function on top of stack are displayed incorrectly.

llvm-svn: 37015
2007-05-12 22:36:25 +00:00
Chris Lattner 623c738fe9 add some notes
llvm-svn: 36965
2007-05-10 00:08:04 +00:00
Bill Wendling f985c492e1 3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX.
llvm-svn: 36860
2007-05-06 07:56:19 +00:00
Nate Begeman 4060c7ac63 Reference correct header
llvm-svn: 36834
2007-05-06 04:00:55 +00:00
Chris Lattner be8f99ecbb move CodeGen/X86/overlap-add.ll here.
llvm-svn: 36799
2007-05-05 22:10:24 +00:00
Anton Korobeynikov 4db0090339 Emit sections/directives in the proper order. This fixes PR1376. Also,
some small cleanup was made.

llvm-svn: 36780
2007-05-05 09:04:50 +00:00
Bill Wendling e6182267d7 Add an "implies" field to features. This indicates that, if the current
feature is set, then the features in the implied list should be set also.
The opposite is also enforced: if a feature in the implied list isn't set,
then the feature that owns that implies list shouldn't be set either.

llvm-svn: 36756
2007-05-04 20:38:40 +00:00
Chris Lattner 83df45a959 Fix two classes of bugs:
1. x86 backend rejected (&gv+c) for the 'i' constraint when in static mode.
  2. the matcher didn't correctly reject and accept some global addresses.
     the right predicate is GVRequiresExtraLoad, not "relomodel = pic".

llvm-svn: 36670
2007-05-03 16:52:29 +00:00
Dan Gohman e27e6e6fa8 Sets the section names for fixed-size constants and use the mergeable
flag for ELF on x86 so that duplicate constants can be eliminated by
the linker. This matches what GCC does with its -fmerge-constants
option, which is enabled at most -O levels.

llvm-svn: 36666
2007-05-03 16:38:57 +00:00
Devang Patel 8c78a0bff0 Drop 'const'
llvm-svn: 36662
2007-05-03 01:11:54 +00:00
Bill Wendling b5ce7c5466 Non-algorithmic change. Moved definitions around into separate sections
for SSE1, SSE2, SSE3, and SSSE3.

llvm-svn: 36656
2007-05-02 23:11:52 +00:00
Bill Wendling ba3b7ee030 Update.
llvm-svn: 36653
2007-05-02 21:42:20 +00:00
Devang Patel e95c6ad802 Use 'static const char' instead of 'static const int'.
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.

llvm-svn: 36652
2007-05-02 21:39:20 +00:00