ec68866f55
Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch.
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llvm-svn: 200520
2014-01-31 07:00:55 +00:00
9bbf7ca13d
]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)
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llvm-svn: 199806
2014-01-22 15:08:36 +00:00
b33c2ef215
[x86] Allow address-size overrides for STOS[BWLQ] (PR9385)
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llvm-svn: 199804
2014-01-22 15:08:21 +00:00
2ef8d9c05c
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)
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llvm-svn: 199803
2014-01-22 15:08:08 +00:00
caaa2850c0
[x86] Fix disassembly of MOV16ao16 et al.
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The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.
llvm-svn: 199654
2014-01-20 12:02:53 +00:00
35da3d190a
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962.
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llvm-svn: 199364
2014-01-16 07:36:58 +00:00
b7c7f38918
Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions.
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llvm-svn: 199295
2014-01-15 05:02:02 +00:00
ad60708a72
Remove stray comma in enum to satisfy -Wpedantic.
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llvm-svn: 199194
2014-01-14 08:07:10 +00:00
ae11aed9d7
Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode.
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This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.
llvm-svn: 199193
2014-01-14 07:41:20 +00:00
32da3c8f3b
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand
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It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.
Hm, perhaps we do need an AdSize16 bit after all?
llvm-svn: 198759
2014-01-08 12:58:24 +00:00
2ea87dad77
The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being used.
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llvm-svn: 198589
2014-01-06 06:57:27 +00:00
d9e1669d1c
Use patterns to remove some duplicate instructions.
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llvm-svn: 198550
2014-01-05 06:55:48 +00:00
34db6523f3
Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.
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llvm-svn: 198547
2014-01-05 05:46:38 +00:00
c0107977d9
Remove no longer needed x86 disassembler hack.
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llvm-svn: 198546
2014-01-05 05:10:07 +00:00
0550ce7ac1
Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches.
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llvm-svn: 198545
2014-01-05 04:55:55 +00:00
5165cf78b0
Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack.
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llvm-svn: 198544
2014-01-05 04:32:42 +00:00
3484fc2161
Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions.
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llvm-svn: 198543
2014-01-05 04:17:28 +00:00
5999d47538
Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.
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llvm-svn: 198530
2014-01-05 01:35:51 +00:00
bc281ad8c1
Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack.
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llvm-svn: 198515
2014-01-04 22:29:41 +00:00
1da8582322
Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator.
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llvm-svn: 198475
2014-01-04 05:09:27 +00:00
66c20f344e
Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.
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llvm-svn: 198336
2014-01-02 19:12:10 +00:00
fae226c67e
Remove unused HasFROperands field from disassembler.
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llvm-svn: 198332
2014-01-02 18:44:21 +00:00
eabdbcb8a9
Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder.
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llvm-svn: 198327
2014-01-02 18:20:48 +00:00
a941d2b08e
Remove unnecessary stirng comparison from disassembler.
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llvm-svn: 198325
2014-01-02 17:41:40 +00:00
9dd48c8ed4
Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them.
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llvm-svn: 198323
2014-01-02 17:28:14 +00:00
83b7e24b76
Remove unused function argument.
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llvm-svn: 198291
2014-01-02 03:58:45 +00:00
3321c99a06
Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables.
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llvm-svn: 198284
2014-01-01 21:52:57 +00:00
9155118602
Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.
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llvm-svn: 198278
2014-01-01 15:29:32 +00:00
de3f751baf
AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp
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Printing rounding control.
Enncoding for EVEX_RC (rounding control).
llvm-svn: 198277
2014-01-01 15:12:34 +00:00
623b0d64b3
Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
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llvm-svn: 198276
2014-01-01 14:22:37 +00:00
e98c8cb9f0
Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.
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llvm-svn: 198265
2013-12-31 17:21:44 +00:00
0e21bca6dd
Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
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llvm-svn: 198238
2013-12-30 19:16:48 +00:00
6d776e2660
Remove EscapeFilter. It's funcionality can be covered by correctly using ExtendedFilter and ExactFilter. No functional change.
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llvm-svn: 198226
2013-12-30 17:37:10 +00:00
c0a5aaeab0
[x86] Rename In32BitMode predicate to Not64BitMode
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That's what it actually means, and with 16-bit support it's going to be
a little more relevant since in a few corner cases we may actually want
to distinguish between 16-bit and 32-bit mode (for example the bare 'push'
aliases to pushw/pushl etc.)
Patch by David Woodhouse
llvm-svn: 197768
2013-12-20 02:04:49 +00:00
47fc44e52e
AVX-512: Added legal type MVT::i1 and VK1 register for it.
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Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.
llvm-svn: 197384
2013-12-16 13:52:35 +00:00
dacddb0bab
AVX-512: added VPCONFLICT instruction and intrinsics,
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added EVEX_KZ to tablegen
llvm-svn: 193959
2013-11-03 13:46:31 +00:00
a422b09ae3
Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
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llvm-svn: 192567
2013-10-14 04:55:01 +00:00
88adf2a49c
Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly.
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llvm-svn: 192525
2013-10-12 05:41:08 +00:00
aab53e7785
Mark some more instructions as CodeGenOnly. Remove filters from the disassembler.
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llvm-svn: 192522
2013-10-12 04:46:18 +00:00
81034928c6
Remove another unnecessary filter from the disassembler.
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llvm-svn: 192425
2013-10-11 06:59:57 +00:00
e1ceeb40c1
Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables.
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llvm-svn: 192339
2013-10-10 04:26:52 +00:00
2d0d180ab4
More x86 disassembler filtering cleanup.
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llvm-svn: 192279
2013-10-09 06:12:53 +00:00
043d749ba3
Remove some old filters from the x86 disassembler table builder.
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llvm-svn: 192275
2013-10-09 05:02:29 +00:00
a984729f8a
Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building.
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llvm-svn: 192175
2013-10-08 06:30:39 +00:00
72c8cd7bc3
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.
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llvm-svn: 192171
2013-10-08 05:53:50 +00:00
07ad1b23bb
Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.
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llvm-svn: 192090
2013-10-07 07:19:47 +00:00
2658d89728
Add disassembler support for long encodings for INC/DEC in 32-bit mode.
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llvm-svn: 192086
2013-10-07 04:28:06 +00:00
9e3e38ae3f
Add XOP disassembler support. Fixes PR13933.
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llvm-svn: 191874
2013-10-03 05:17:48 +00:00
c35219e3ee
AVX-512: Added masked SHIFT commands, more encoding tests
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llvm-svn: 189005
2013-08-22 12:18:28 +00:00
9469e906a5
Remove use of sprintf added to X86 disassembler tablegen code. Send message with instruction name to errs() instead and use a generic message for the llvm_unreachable. Consistent with other places in this file.
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llvm-svn: 187333
2013-07-28 21:28:02 +00:00
Craig Topper