3b245876c0
When the scheduler unfold a load folding instruction it move some of the predecessors to the unfolded load. It decides what gets moved to the load by checking whether the new load is using the predecessor as an operand. The check neglects the cases whether the predecessor is a flagged scheduling unit.
...
rdar://7604000
llvm-svn: 95339
2010-02-05 01:27:11 +00:00
6510dc8dc3
An empty global constant (one of size 0) may have a section immediately
...
following it. However, the EmitGlobalConstant method wasn't emitting a body for
the constant. The assembler doesn't like that. Before, we were generating this:
.zerofill __DATA, __common, __cmd, 1, 3
This fix puts us back to that semantic.
llvm-svn: 95336
2010-02-05 00:17:02 +00:00
c7c89b8325
Fix small bug in handling instructions with more than one implicitly defined operand.
...
ProcessImplicitDefs would only mark one operand per instruction with <undef>.
This fixed PR6086.
llvm-svn: 95319
2010-02-04 18:46:28 +00:00
aeba2250a5
Re-enable x86 tail call optimization.
...
llvm-svn: 95295
2010-02-04 06:47:24 +00:00
8228b11abc
add support for the sparcv9-*-* target triple to turn on
...
64-bit sparc codegen. Patch by Nathan Keynes!
llvm-svn: 95293
2010-02-04 06:34:01 +00:00
f4139067ee
Speculatively disable x86 automatic tail call optimization while we track down a self-hosting issue.
...
llvm-svn: 95259
2010-02-03 21:40:40 +00:00
112a871fe2
Make test less fragile
...
llvm-svn: 95258
2010-02-03 21:39:04 +00:00
27a41d5473
Revert 94937 and move the noreturn check to codegen.
...
llvm-svn: 95198
2010-02-03 03:55:59 +00:00
40905b4302
Allow all types of callee's to be tail called. But avoid automatic tailcall if the callee is a result of bitcast to avoid losing necessary zext / sext etc.
...
llvm-svn: 95195
2010-02-03 03:28:02 +00:00
a466692552
Reapply 95050 with a tweak to check the register class.
...
llvm-svn: 95183
2010-02-03 01:40:33 +00:00
dee74e2805
make these less sensitive to asm verbose changes by disabling it for them.
...
llvm-svn: 95175
2010-02-03 00:48:53 +00:00
da431c76fb
Test revert 95050; there's a good chance it's causing
...
buildbot failure.
llvm-svn: 95103
2010-02-02 18:52:56 +00:00
55afd2564c
Perform sibcall in some cases when arguments are passes memory. Look for cases
...
where callee's arguments are already in the caller's own caller's stack and
they line up perfectly. e.g.
extern int foo(int a, int b, int c);
int bar(int a, int b, int c) {
return foo(a, b, c);
}
llvm-svn: 95053
2010-02-02 02:22:50 +00:00
c84816a62e
Make local RA smarter about reusing input register of a copy
...
as output. Needed for (functional) correctness in inline asm,
and should be generally beneficial. 7361612.
llvm-svn: 95050
2010-02-02 02:08:02 +00:00
a49d8e6d38
Fix PR6196. GV callee may not be a function.
...
llvm-svn: 95017
2010-02-01 22:40:09 +00:00
36bca4e4ba
Update this test for a trivial register allocation difference.
...
llvm-svn: 94989
2010-02-01 19:00:32 +00:00
ed8ca56eeb
Undo r94946 now all the tests are passing again.
...
llvm-svn: 94970
2010-02-01 02:13:39 +00:00
7f62def0f9
Avoid recursive sibcall's.
...
llvm-svn: 94946
2010-01-31 06:44:49 +00:00
25df248382
Fix a gross typo: ARMv6+ may or may not support unaligned memory operations.
...
Even if they are suported by the core, they can be disabled
(this is just a configuration bit inside some register).
Allow unaligned memops on darwin and conservatively disallow them otherwise.
llvm-svn: 94889
2010-01-30 14:08:12 +00:00
70f714fdbe
Allow more tailcall optimization: calls with inputs that are all passed in registers.
...
llvm-svn: 94873
2010-01-30 01:22:00 +00:00
297a494f55
Catch more trivial tail call opportunities: no inputs and output types match.
...
llvm-svn: 94804
2010-01-29 06:45:59 +00:00
cc9a6f0580
convert the last 3 targets to use EmitFunctionBody() now that
...
it has before/end body hooks.
lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp | 49 ++-----------
lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp | 87 ++++++------------------
lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp | 56 +++------------
test/CodeGen/XCore/ashr.ll | 2
4 files changed, 48 insertions(+), 146 deletions(-)
llvm-svn: 94741
2010-01-28 06:22:43 +00:00
346af88396
Fix a bug introduced by r94490 where it created a X86ISD::CMP whose output type is different from its inputs.
...
This fixes PR6146.
llvm-svn: 94731
2010-01-28 01:57:22 +00:00
73de5fbfc3
Give AsmPrinter the most common expected implementation of
...
runOnMachineFunction, and switch PPC to use EmitFunctionBody.
The two ppc asmprinters now don't heave to define
runOnMachineFunction.
llvm-svn: 94722
2010-01-28 01:28:58 +00:00
565896b9eb
emit a 0 byte instead of a noop if a function is empty on darwin.
...
"0" is nice and target independent.
llvm-svn: 94718
2010-01-28 01:06:32 +00:00
4fe7a3bc08
Quick fix to a test that is currently failing on every Linux build bot. No idea
...
if this is the "correct" fix, but it seems a strict improvement.
llvm-svn: 94675
2010-01-27 10:36:15 +00:00
85476f304c
Perform trivial tail call optimization for callees with "C" ABI. These are done
...
even when -tailcallopt is not specified and it does not require changing ABI.
First case is the most trivial one. Perform tail call optimization when both
the caller and callee do not return values and when the callee does not take
any input arguments.
llvm-svn: 94664
2010-01-27 06:25:16 +00:00
b657c4cdc3
emit jump table an alias ".set" directives through MCStreamer as
...
assignments.
.set x, a-b
is the same as:
x = a-b
llvm-svn: 94596
2010-01-26 21:53:08 +00:00
dcb03f0f6b
Emit .comm alignment in bytes but .align in powers of 2 for ARM ELF.
...
Original patch by Sandeep Patel and updated by me.
llvm-svn: 94582
2010-01-26 20:21:43 +00:00
3dd38a8112
eliminate MCAsmInfo::NeedsSet: we now just use .set on any platform
...
that has it.
llvm-svn: 94581
2010-01-26 20:20:43 +00:00
555f61bf58
Implement cond ? -1 : 0 with sbb.
...
llvm-svn: 94490
2010-01-26 02:00:44 +00:00
4cb52db485
Update test for darwin.
...
llvm-svn: 94421
2010-01-25 15:32:10 +00:00
9b83727cfe
we removed support for darwin8 tools.
...
llvm-svn: 94414
2010-01-25 07:43:40 +00:00
a1141dd6ab
Fix PR6134.
...
We are not emitting alignments on Darwin for "bar". Not sure what is the
correct way to do it.
llvm-svn: 94400
2010-01-25 02:27:39 +00:00
75652a6f2b
Attempt to unbreak test on Linux. Chris, please check.
...
llvm-svn: 94399
2010-01-25 00:54:13 +00:00
45dd2327cb
just remove this test, it is not reduced, is not clear what its testing for and
...
it is dying due to fragility in the asmprinter .s comments.
llvm-svn: 94372
2010-01-24 19:23:09 +00:00
4f45512c23
It seems better to scalarize vectors of size 1 instead of widening them.
...
Add support to widen SETCC.
llvm-svn: 94342
2010-01-24 00:24:43 +00:00
586d997e98
Improved widening loads by adding support for wider loads if
...
the alignment allows. Fixed a bug where we didn't use a
vector load/store for PR5626.
llvm-svn: 94338
2010-01-24 00:05:03 +00:00
d1acffc845
Change constantexpr global variable initializers to convert the constants
...
to MCExpr then emit them through MCStreamer with EmitValue. I think all
global variable initializers are now going through mcstreamer.
llvm-svn: 94293
2010-01-23 06:17:14 +00:00
c1451d764f
Don't lower splat vector load to relative to the esp if the
...
stack may be misaligned.
Update test accordingly.
Patch by Evan Cheng!
llvm-svn: 94291
2010-01-23 06:02:43 +00:00
82b86b0fce
stop testing for invalid output.
...
llvm-svn: 94288
2010-01-23 05:45:28 +00:00
68eeb5ec9c
emit .ascii and .asciz through MCStreamer.
...
llvm-svn: 94282
2010-01-23 04:54:10 +00:00
cabb6ff64d
remove this test.
...
llvm-svn: 94276
2010-01-23 03:11:10 +00:00
8204911e1d
Fix test.
...
llvm-svn: 94272
2010-01-23 01:21:27 +00:00
e1b8b5a01b
Fix tests.
...
llvm-svn: 94271
2010-01-23 01:19:28 +00:00
88b8b1b419
make this less constrained, we want blank lines between globals.
...
llvm-svn: 94201
2010-01-22 19:51:08 +00:00
045f81981a
Revert LoopStrengthReduce.cpp to pre-r94061 for now.
...
llvm-svn: 94123
2010-01-22 00:46:49 +00:00
1526375827
testcase for r94095
...
llvm-svn: 94096
2010-01-21 20:01:04 +00:00
51ad99d2c5
Re-implement the main strength-reduction portion of LoopStrengthReduction.
...
This new version is much more aggressive about doing "full" reduction in
cases where it reduces register pressure, and also more aggressive about
rewriting induction variables to count down (or up) to zero when doing so
reduces register pressure.
It currently uses fairly simplistic algorithms for finding reuse
opportunities, but it introduces a new framework allows it to combine
multiple strategies at once to form hybrid solutions, instead of doing
all full-reduction or all base+index.
llvm-svn: 94061
2010-01-21 02:09:26 +00:00
f8dcf784a7
emit basic block labels with mcstreamer.
...
llvm-svn: 93993
2010-01-20 07:24:05 +00:00
4c8b1824f0
emit integer and fp zeros as (e.g.) .byte 0 instead of .space 1,
...
for tidiness.
llvm-svn: 93992
2010-01-20 07:19:19 +00:00
03cb2a3035
signficant cleanups to EmitGlobalConstant (including streamerization
...
of int initializers), change some methods to be static functions,
use raw_ostream::write_hex instead of a smallstring dance with
APValue::toStringUnsigned(S, 16).
llvm-svn: 93991
2010-01-20 07:11:32 +00:00
954f49014d
Fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)), to simplify some code
...
that SCEVExpander can produce when running on behalf of LSR.
llvm-svn: 93949
2010-01-19 23:30:49 +00:00
221708d826
Make SCEVAddRecExpr's getType return a pointer type when the add
...
has a pointer member. This helps reduce unnecessary bitcasting
and uglygeps.
llvm-svn: 93939
2010-01-19 22:53:50 +00:00
fb9bea7150
Add nounwinds.
...
llvm-svn: 93919
2010-01-19 21:51:51 +00:00
bdc17f6840
Remove predicates when changing an add into an unpredicable mov.
...
Since the mov is executed unconditionally, make sure that the add didn't have
any predicate.
llvm-svn: 93909
2010-01-19 21:08:28 +00:00
bf43525a29
Do not extend extension results beyond the use of a PHI instruction at the start of a use block. A PHI use is expected to kill its source values.
...
llvm-svn: 93895
2010-01-19 19:45:51 +00:00
a6368219ac
don't let asm-verbose break the check-next lines in these tests.
...
llvm-svn: 93869
2010-01-19 06:39:54 +00:00
c7a062d187
Now that we have everything nicely factored (e.g. asmprinter is not
...
doing global variable classification anymore) and hookized, sink almost
all target targets global variable emission code into AsmPrinter and out
of each target.
Some notes:
1. PIC16 does completely custom and crazy stuff, so it is not changed.
2. XCore has some custom handling for extra directives. I'll look at it next.
3. This switches linux/ppc to use .globl instead of .global. If .globl is
actually wrong, let me know and I'll fix it.
4. This makes linux/ppc get a lot of random cases right which were obviously
wrong before, it is probably now a bit healthier.
5. Blackfin will probably start getting .comm and other things that it didn't
before. If this is undesirable, it should explicitly opt out of these
things by clearing the relevant fields of MCAsmInfo.
This leads to a nice diffstat:
14 files changed, 127 insertions(+), 830 deletions(-)
llvm-svn: 93858
2010-01-19 05:38:33 +00:00
a986aa33eb
fix a significant difference between llvm and gcc on ELF systems:
...
GCC would put weak zero initialized mutable data in the .bss section,
we would put it into a crasy '.gnu.linkonce.b.test,"aw",@nobits'
section. Fixing this will allow simplifications next up.
llvm-svn: 93844
2010-01-19 03:06:01 +00:00
024734e0f0
there is no need to emit a .section above .comm on linux.
...
llvm-svn: 93842
2010-01-19 02:46:56 +00:00
4668a3b935
Test case for r93758.
...
llvm-svn: 93824
2010-01-19 00:35:20 +00:00
88b65bc835
Canonicalize -1 - x to ~x.
...
Instcombine does this but apparently there are situations where this pattern will escape the optimizer and / or created by isel. Here is a case that's seen in JavaScriptCore:
%t1 = sub i32 0, %a
%t2 = add i32 %t1, -1
The dag combiner pattern: ((c1-A)+c2) -> (c1+c2)-A
will fold it to -1 - %a.
llvm-svn: 93773
2010-01-18 21:38:44 +00:00
387c6b20cd
reduce this test and convert to filecheck, hopefully the linux buildbot
...
will tell me something more useful.
llvm-svn: 93688
2010-01-17 19:09:12 +00:00
9349437c65
The Neon "vtst" instruction takes a suffix that is the element size alone --
...
adding an "i" to the suffix, indicating that the elements are integers, is
accepted but not part of the standard syntax. This helps us pass a few more
of the Neon tests from gcc.
llvm-svn: 93677
2010-01-17 06:35:17 +00:00
dd6ddd1aeb
When checking for sret-demotion, it needs to use legal types. When using the return value of an sret-demoted call, it needs to use possibly illegal types that match the declared Type of the callee.
...
llvm-svn: 93667
2010-01-16 23:37:33 +00:00
08eff61eeb
this teestcase takes a long time to crash, remove it. If someone cares about this, they should file a bug, it's not doing any good as an xfail.
...
llvm-svn: 93604
2010-01-16 00:53:22 +00:00
298cdac99c
Run the pre-register allocation tail duplication pass by default. Remove
...
the -pre-regalloc-taildup command-line option, and add a new
-disable-early-taildup option.
llvm-svn: 93597
2010-01-16 00:29:50 +00:00
b0c0e6433f
Fix PR6019. A load has more than one use if it feeds a bitconvert that
...
has more than one use.
llvm-svn: 93576
2010-01-15 23:23:41 +00:00
fd850837a3
add testcase for r93564
...
llvm-svn: 93567
2010-01-15 22:27:37 +00:00
07e8171fcb
Reenable tests
...
llvm-svn: 93555
2010-01-15 21:19:26 +00:00
3a0b066d24
Temporary disable tests
...
llvm-svn: 93501
2010-01-15 02:09:27 +00:00
fdf7031a1a
Add variable-width shifts for MSP430
...
llvm-svn: 93468
2010-01-14 22:09:38 +00:00
dd5286dc63
Fix a codegen abort seen in 483.xalancbmk.
...
llvm-svn: 93417
2010-01-14 03:08:49 +00:00
fb40a8e5f1
this test requires SSE, thanks to jyasskin for pointing this out.
...
llvm-svn: 93360
2010-01-13 21:51:41 +00:00
af0ad65ff2
Commit some changes I had managed to lose last night while refactoring the code. Avoid change use of PHI instructions because it's not legal to insert any instructions before them.
...
This fixes PR6027.
llvm-svn: 93335
2010-01-13 19:16:39 +00:00
b5499d09d1
Re-enable extension optimization pass.
...
llvm-svn: 93313
2010-01-13 08:45:40 +00:00
25d8ed3773
remove uses of deprecated functions, this generates slightly
...
different BlockAddress labels, but nothing semantically important.
Add a FIXME that BlockAddress codegen is broken if the LLVM BB has
an empty name (e.g. strip was run).
llvm-svn: 93303
2010-01-13 07:30:49 +00:00
d7d8f6d000
Disable opt-ext pass to unbreak the build for now.
...
llvm-svn: 93286
2010-01-13 01:51:43 +00:00
0ad23efb0f
Try to fix the ARM and PPC buildbots. The -mattr=vector-unaligned-mem
...
flag doesn't exist there, and this is an x86 test.
llvm-svn: 93279
2010-01-13 00:31:43 +00:00
30bebff456
Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg.
...
For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used.
llvm-svn: 93278
2010-01-13 00:30:23 +00:00
0e9189371f
Add nounwind.
...
llvm-svn: 93244
2010-01-12 18:29:23 +00:00
b7168c270e
Revert commit 93204, since it causes the assembler to barf
...
on x86-64 linux with messages like this:
Error: Incorrect register `%r14' used with `l' suffix
llvm-svn: 93242
2010-01-12 17:46:16 +00:00
9059833de6
Make several tests less fragile.
...
llvm-svn: 93230
2010-01-12 04:52:47 +00:00
c119580307
Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS.
...
llvm-svn: 93229
2010-01-12 04:42:54 +00:00
42b07e9600
Add manual ISD::OR fastisel selection routines. TableGen is no longer autogen them after 93152 and 93191.
...
llvm-svn: 93204
2010-01-11 22:59:27 +00:00
99789a7a76
Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead.
...
llvm-svn: 93191
2010-01-11 22:03:29 +00:00
f0d26d4b74
reduce this to a sensible testcase.
...
llvm-svn: 93189
2010-01-11 21:58:19 +00:00
eb103c404b
Shorten up this testcase.
...
llvm-svn: 93187
2010-01-11 21:50:35 +00:00
7bdf339602
Revert 93158. It's breaking quite a few x86_64 tests.
...
llvm-svn: 93185
2010-01-11 21:13:41 +00:00
d2a1bee2d4
Avoid adding PHI arguments for a predecessor that has gone away when a BRCOND was constant folded.
...
This fixes PR5980.
llvm-svn: 93184
2010-01-11 21:02:33 +00:00
e99a3c191e
Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
...
has an immediate with at least 32 bits of leading zeros, to avoid needing to
materialize that immediate in a register first.
FileCheckize, tidy, and extend a testcase to cover this case.
This fixes rdar://7527390.
llvm-svn: 93160
2010-01-11 17:58:34 +00:00
3a55686345
Re-instate MOV64r0 and MOV16r0, with adjustments to work with the
...
new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.
llvm-svn: 93158
2010-01-11 17:37:57 +00:00
31e8637ac2
Generalize this check to avoid depending on a specific register assignment.
...
llvm-svn: 93157
2010-01-11 17:24:27 +00:00
355ebc7f58
Make this test less trivial, to avoid spurious failures.
...
llvm-svn: 93156
2010-01-11 17:23:56 +00:00
64d9f40557
Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed.
...
llvm-svn: 93152
2010-01-11 17:03:47 +00:00
206351a1ff
Implement a feature (-vector-unaligned-mem) to allow targets to
...
ignore alignment requirements for SIMD memory operands. This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.
llvm-svn: 93151
2010-01-11 16:29:42 +00:00
bb857e5d68
Fix http://llvm.org/PR5729 : x86-64 tail calls were putting their targets into
...
R11, and then asserting that the target was in R9. Since R9 isn't reserved for
the target anymore, and is used as an argument, this patch changes the
assertion.
llvm-svn: 93065
2010-01-09 18:56:43 +00:00
6bd3ef82ff
Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNode
...
really does need to be a vector type, because
TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type,
and it needs to be able to distinguish between vectors and scalars.
Also, fix some more issues with legalization of vector casts.
llvm-svn: 93043
2010-01-09 02:13:55 +00:00
cc6d56bd3b
Fix a critical bug in 64-bit atomic operation lowering for 32-bit. The results of the cmpxchg8b instructions are being thrown away when it branches back to the top of the checking loop. This means the loop always compares against the old value and this can result in a dead lock.
...
llvm-svn: 93028
2010-01-08 23:41:50 +00:00
58ec4fec88
ReplaceAllUsesOfValueWith may delete other nodes that the one being replaced. Do not delete dead nodes again.
...
llvm-svn: 92988
2010-01-08 02:36:12 +00:00
dab2cd543f
Fix rdar://7517201, a regression introduced by r92849.
...
When folding a and(any_ext(load)) both the any_ext and the
load have to have only a single use.
This removes the anyext-uses.ll testcase which started failing
because it is unreduced and unclear what it is testing.
llvm-svn: 92950
2010-01-07 21:59:23 +00:00
16b75ce19c
APInt'fy TargetLowering::SimplifySetCC to fix PR5963.
...
llvm-svn: 92943
2010-01-07 20:58:44 +00:00
90dc43fcf5
Fix a minor regression from my dag combiner changes. One more place which needs to look pass truncates.
...
llvm-svn: 92885
2010-01-07 00:54:06 +00:00
f1522d612f
Add comments.
...
llvm-svn: 92883
2010-01-07 00:51:04 +00:00
29a64c9575
Add Target hook to duplicate machine instructions.
...
Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.
llvm-svn: 92873
2010-01-06 23:47:07 +00:00
166a4e6caa
Teach dag combine to fold the following transformation more aggressively:
...
(OP (trunc x), (trunc y)) -> (trunc (OP x, y))
Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.
This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.
llvm-svn: 92849
2010-01-06 19:38:29 +00:00
f34b289057
Move this test from test/Transforms/IndVarSimplify to
...
test/CodeGen/X86, as doesn't use -indvars, and it does use
llc -march=x86-64.
llvm-svn: 92799
2010-01-05 22:52:54 +00:00
03f0af372c
Don't assign the shift the same type as the variable being shifted. This could
...
result in illegal types for the SHL operator.
llvm-svn: 92797
2010-01-05 22:39:10 +00:00
fb4193625a
Delete useless trailing semicolons.
...
llvm-svn: 92740
2010-01-05 17:55:26 +00:00
8c63ee7e28
Make this test more portable.
...
llvm-svn: 92514
2010-01-04 21:23:34 +00:00
52183c3cc9
Add some tests and update an existing test to reflect recent
...
x86 isel peeps.
llvm-svn: 92509
2010-01-04 20:53:54 +00:00
d91a14dba5
Fix invalid chain folding for memory variant of sdiv / udiv
...
llvm-svn: 92472
2010-01-04 10:31:54 +00:00
1dae8766b1
fix PR5930, allowing the asmprinter to emit difference between
...
two labels as a truncate.
llvm-svn: 92455
2010-01-03 18:33:18 +00:00
f6a585fc2f
add PR#
...
llvm-svn: 92451
2010-01-03 18:10:58 +00:00
a7cfc43af8
differences between two blockaddress's don't cause a
...
global variable initializer to require relocations.
llvm-svn: 92450
2010-01-03 18:09:40 +00:00
909c71c96a
allow this to work on linux hosts.
...
llvm-svn: 92407
2010-01-02 00:22:15 +00:00
1eea3b0ada
Teach codegen to handle:
...
(X != null) | (Y != null) --> (X|Y) != 0
(X == null) & (Y == null) --> (X|Y) == 0
so that instcombine can stop doing this for pointers. This is part of PR3351,
which is a case where instcombine doing this for pointers (inserting ptrtoint)
is pessimizing code.
llvm-svn: 92406
2010-01-02 00:00:03 +00:00
6eef072eb6
rename file.
...
llvm-svn: 92405
2010-01-01 23:55:04 +00:00
39f18e545e
Teach codegen to lower llvm.powi to an efficient (but not optimal)
...
multiply sequence when the power is a constant integer. Before, our
codegen for std::pow(.., int) always turned into a libcall, which was
really inefficient.
This should also make many gfortran programs happier I'd imagine.
llvm-svn: 92388
2010-01-01 03:32:16 +00:00
5967840a5f
Make this more likely to generate a libcall.
...
llvm-svn: 92387
2010-01-01 03:26:51 +00:00
015215ca86
Extern declaration for unordered.f32 libcall was not being emitted. Fixed that.
...
llvm-svn: 92242
2009-12-29 03:24:34 +00:00
1ecffe13b2
Fixed llc crash for zext (i1 -> i8) loads.
...
llvm-svn: 92201
2009-12-28 04:53:24 +00:00
f5e3ed64d5
handle equality memcmp of 8 bytes on x86-64 with two unaligned loads and a
...
compare. On other targets we end up with a call to memcmp because we don't
want 16 individual byte loads. We should be able to use movups as well, but
we're failing to select the generated icmp.
llvm-svn: 92107
2009-12-24 01:07:17 +00:00
1a32ede6fd
move an optimization for memcmp out of simplifylibcalls and into
...
SDISel. This optimization was causing simplifylibcalls to
introduce type-unsafe nastiness. This is the first step, I'll be
expanding the memcmp optimizations shortly, covering things that
we really really wouldn't want simplifylibcalls to do.
llvm-svn: 92098
2009-12-24 00:37:38 +00:00
cd419eebce
Reapply 91904.
...
llvm-svn: 91996
2009-12-23 11:19:09 +00:00
6920c17f1f
deleting empty file.
...
llvm-svn: 91994
2009-12-23 10:35:24 +00:00
f7b4f89588
Reverting back 91904.
...
llvm-svn: 91993
2009-12-23 09:46:01 +00:00
a864a67185
Use more sensible type for flags in asms. PR 5570.
...
Patch by Sylve`re Teissier (sorry, ASCII only).
llvm-svn: 91988
2009-12-23 07:32:51 +00:00
fdb33458fc
Update objectsize intrinsic and associated dependencies. Fix
...
lowering code and update testcases.
llvm-svn: 91979
2009-12-23 02:51:48 +00:00
ef3fdc1cbd
Add testcase for PR5703
...
llvm-svn: 91931
2009-12-22 22:37:23 +00:00
71d7eaa87e
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
...
llvm-svn: 91910
2009-12-22 17:47:23 +00:00
8c5f05fcee
While converting one of the operands to a memory operand, we need to check if it is Legal and does not result into a cyclic dep.
...
llvm-svn: 91904
2009-12-22 14:25:37 +00:00
8ac077df57
Emit direction operand in binary insns that stores in memory.
...
llvm-svn: 91777
2009-12-19 13:52:01 +00:00
bda8002e7f
Test cases for changes done in 91768.
...
llvm-svn: 91773
2009-12-19 11:38:14 +00:00
b175de6356
Increase opportunities to optimize (brcond (srl (and c1), c2)).
...
llvm-svn: 91717
2009-12-18 21:31:31 +00:00
4cf30b72bf
On recent Intel u-arch's, folding loads into some unary SSE instructions can
...
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.
movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
instead of
cvtss2sd (%rdi), %xmm0
An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0
llvm-svn: 91672
2009-12-18 07:40:29 +00:00
51fbfb726f
Tidy up this testcase and add test for tailcall optimization
...
with unreachable.
llvm-svn: 91650
2009-12-18 01:05:06 +00:00
3152b0471b
Handle ARM inline asm "w" constraints with 64-bit ("d") registers.
...
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types. Radar 7457110.
llvm-svn: 91649
2009-12-18 01:03:29 +00:00
7f4326f8b6
Remove "tail" keywords. These calls are not intended to be tail calls.
...
This protects this test from depending on codegen not performing the
tail call optimization by default.
llvm-svn: 91648
2009-12-18 01:02:18 +00:00
78c5919b14
Add test case for the phi reuse patch.
...
llvm-svn: 91642
2009-12-18 00:11:44 +00:00
04d8cb74f3
Instruction fixes, added instructions, and AsmString changes in the
...
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
llvm-svn: 91638
2009-12-18 00:01:26 +00:00
aadf060b92
Revert this dag combine change:
...
Fold (zext (and x, cst)) -> (and (zext x), cst)
DAG combiner likes to optimize expression in the other way so this would end up cause an infinite looping.
llvm-svn: 91574
2009-12-17 00:40:05 +00:00
23fbd54cfe
Make this test pass on Linux.
...
llvm-svn: 91521
2009-12-16 07:35:25 +00:00
1be6286028
Re-enable 91381 with fixes.
...
llvm-svn: 91489
2009-12-16 00:53:11 +00:00
56f041406d
Do better with physical reg operands (typically, from inline asm)
...
in local register allocator. If a reg-reg copy has a phys reg
input and a virt reg output, and this is the last use of the phys
reg, assign the phys reg to the virt reg. If a reg-reg copy has
a phys reg output and we need to reload its spilled input, reload
it directly into the phys reg than passing it through another reg.
Following 76208, there is sometimes no dependency between the def of
a phys reg and its use; this creates a window where that phys reg
can be used for spilling (this is true in linear scan also). This
is bad and needs to be fixed a better way, although 76208 works too
well in practice to be reverted. However, there should normally be
no spilling within inline asm blocks. The patch here goes a long way
towards making this actually be true.
llvm-svn: 91485
2009-12-16 00:29:41 +00:00
792f0913ee
For fastcc on x86, let ECX be used as a return register after EAX and EDX
...
llvm-svn: 91410
2009-12-15 03:27:52 +00:00
fcb5453dc7
Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp.
...
llvm-svn: 91405
2009-12-15 03:07:11 +00:00
852c486946
Make 91378 more conservative.
...
1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest.
2. If the shift is a left shift, make sure the original shift cannot shift out bits.
llvm-svn: 91399
2009-12-15 03:00:32 +00:00
0e8b9e32d1
Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's.
...
llvm-svn: 91381
2009-12-15 00:53:42 +00:00
d1521ef40c
Fold (zext (and x, cst)) -> (and (zext x), cst).
...
llvm-svn: 91380
2009-12-15 00:52:11 +00:00
ca7c690d3b
Propagate zest through logical shift.
...
llvm-svn: 91378
2009-12-15 00:41:36 +00:00
cecad35728
Fix integer cast code to handle vector types.
...
llvm-svn: 91362
2009-12-14 23:40:38 +00:00
26fdd7265b
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit.
...
llvm-svn: 91223
2009-12-12 20:03:14 +00:00
e27e028cdd
Lower setcc branchless, if this is profitable.
...
Based on the patch by Brian Lucas!
llvm-svn: 91175
2009-12-11 23:01:29 +00:00
1d459e4937
Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.
...
llvm-svn: 91158
2009-12-11 21:31:27 +00:00
bffa061e02
Change this to the correct PR number.
...
llvm-svn: 91148
2009-12-11 20:09:21 +00:00
6d306bb32b
Fix the result type of SELECT nodes lowered from Select instructions with
...
aggregate return values. This fixes PR5754.
llvm-svn: 91145
2009-12-11 19:50:50 +00:00
fc51282cbe
Honour setHasCalls() set from isel.
...
This is used in some weird cases like general dynamic TLS model.
This fixes PR5723
llvm-svn: 91144
2009-12-11 19:39:55 +00:00
ff2ac71b25
Tests for 91103 and 91104.
...
llvm-svn: 91105
2009-12-11 06:02:21 +00:00
4986588ddb
It's not safe to coalesce a move where src and dst registers have different subregister indices. e.g.:
...
%reg16404:1<def> = MOV8rr %reg16412:2<kill>
llvm-svn: 91061
2009-12-10 20:59:45 +00:00
2262909b20
Fix test.
...
llvm-svn: 90988
2009-12-09 22:24:42 +00:00
493b882f80
Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g.
...
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>
iff ptr is 16-byte aligned (or can be made into 16-byte aligned).
llvm-svn: 90984
2009-12-09 21:00:30 +00:00
d938faff4b
Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code.
...
llvm-svn: 90925
2009-12-09 01:53:58 +00:00
0c2544fd6b
- Support inline asm 'w' constraint for 128-bit vector types.
...
- Also support the 'q' NEON registers asm code.
llvm-svn: 90894
2009-12-08 23:06:22 +00:00
dd2b2f8cba
Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra instruction. Patch inspired by Brian Lucas!
...
llvm-svn: 90819
2009-12-08 01:03:04 +00:00
76a7edc36d
Use FileCheck and set nounwind on calls.
...
llvm-svn: 90790
2009-12-07 19:40:26 +00:00
9528ccdd77
Don't enable the post-RA scheduler on x86 except at -O3. In its
...
current form, it is too expensive in compile time.
llvm-svn: 90781
2009-12-07 19:04:31 +00:00
75dfed4fa5
Dynamic stack realignment use of sp register as source/dest register
...
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4
llvm-svn: 90724
2009-12-06 22:39:50 +00:00
f89986235d
Temporarily revert r90502. It was causing the llvm-gcc bootstrap on PPC to fail.
...
llvm-svn: 90653
2009-12-05 07:30:23 +00:00
ca9cf65455
Also attempt trivial coalescing for live intervals that end in a copy.
...
The coalescer is supposed to clean these up, but when setting up parameters
for a function call, there may be copies to physregs. If the defining
instruction has been LICM'ed far away, the coalescer won't touch it.
The register allocation hint does not always work - when the register
allocator is backtracking, it clears the hints.
This patch takes care of a few more cases that r90163 missed.
llvm-svn: 90502
2009-12-04 00:16:04 +00:00
9655f84662
Don't pull vector sext through both hands of a logical operation, since doing so prevents the fusion of vector sext and setcc into vsetcc.
...
Add a testcase for the above transformation.
Fix a bogus use of APInt noticed while tracking this down.
llvm-svn: 90423
2009-12-03 07:11:29 +00:00
0bbd3077ce
Recognize canonical forms of vector shuffles where the same vector is used for
...
both source operands. In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand. Radar 7434842.
llvm-svn: 90417
2009-12-03 06:40:55 +00:00
76bf386af0
Remove unnecessary check.
...
llvm-svn: 90352
2009-12-02 22:02:20 +00:00
732351f732
Fix PR5391: support early clobber physical register def tied with a use (ewwww)
...
- A valno should be set HasRedefByEC if there is an early clobber def in the middle of its live ranges. It should not be set if the def of the valno is defined by an early clobber.
- If a physical register def is tied to an use and it's an early clobber, it just means the HasRedefByEC is set since it's still one continuous live range.
- Add a couple of missing checks for HasRedefByEC in the coalescer. In general, it should not coalesce a vr with a physical register if the physical register has a early clobber def somewhere. This is overly conservative but that's the price for using such a nasty inline asm "feature".
llvm-svn: 90269
2009-12-01 22:25:00 +00:00
8a8ba87ac8
test case for IV-Users simplification loop improvement
...
llvm-svn: 90260
2009-12-01 21:53:51 +00:00
26667abbd3
Use CFG connectedness as a secondary sort key when deciding the order of copy coalescing.
...
This means that well connected blocks are copy coalesced before the less connected blocks. Connected blocks are more difficult to
coalesce because intervals are more complicated, so handling them first gives a greater chance of success.
llvm-svn: 90194
2009-12-01 03:03:00 +00:00
1d31fc9123
Fix PR5614: parts of a physical register def may be killed the rest.
...
llvm-svn: 90180
2009-12-01 00:44:45 +00:00
020d8d4c63
New virtual registers created for spill intervals should inherit allocation hints from the original register.
...
This helps us avoid silly copies when rematting values that are copied to a physical register:
leaq _.str44(%rip), %rcx
movq %rcx, %rsi
call _strcmp
becomes:
leaq _.str44(%rip), %rsi
call _strcmp
The coalescer will not touch the movq because that would tie down the physical register.
llvm-svn: 90163
2009-11-30 22:55:54 +00:00
031cb00246
Add test case for r90108
...
llvm-svn: 90109
2009-11-30 02:42:27 +00:00
b56334b4f2
While this test is testing a problem in the generic part of codegen,
...
the problem only shows for msp430 and pic16 which is why it specifies
them using -march. But it is wrong to put such tests in CodeGen/Generic,
since not everyone builds these targets. Put a copy of the test in each
of the target test directories.
llvm-svn: 90005
2009-11-27 16:04:14 +00:00
a4c986cbdd
Test for 89905.
...
llvm-svn: 89906
2009-11-26 00:35:01 +00:00
44df27e964
ProcessImplicitDefs should watch out for invalidated iterator and extra implicit operands on copies.
...
llvm-svn: 89880
2009-11-25 21:13:39 +00:00
2db07581b7
Support PIC loading of constant pool entries
...
llvm-svn: 89863
2009-11-25 12:17:58 +00:00
5ece8f0a20
Do not store R31 into the caller's link area on PPC.
...
This violates the ABI (that area is "reserved"), and
while it is safe if all code is generated with current
compilers, there is some very old code around that uses
that slot for something else, and breaks if it is stored
into. Adjust testcases looking for current behavior.
I've verified that the stack frame size is right in all
testcases, whether it changed or not. 7311323.
llvm-svn: 89811
2009-11-24 22:59:02 +00:00
184ec26fcd
Enable predication of NEON instructions in Thumb2 mode.
...
llvm-svn: 89748
2009-11-24 08:06:15 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
...
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
dbb4140f37
move fconst[sd] to UAL. <rdar://7414913>
...
llvm-svn: 89700
2009-11-23 21:08:25 +00:00
50b293d65e
update test for 89694
...
llvm-svn: 89695
2009-11-23 20:39:53 +00:00
f161e97a9e
Miss two, PR5307.
...
llvm-svn: 89596
2009-11-22 15:35:28 +00:00
cc856372b0
Convert Thumb2 tests to FileCheck for PR5307.
...
llvm-svn: 89595
2009-11-22 15:18:27 +00:00
a9268a4525
Turns out stuff gets allocated to different registers depending on the subtarget.
...
llvm-svn: 89594
2009-11-22 15:15:52 +00:00
21d7e8aeb1
Convert ARM tests to FileCheck for PR5307.
...
llvm-svn: 89593
2009-11-22 14:23:33 +00:00
2e245f4e18
Convert test to FileCheck.
...
llvm-svn: 89589
2009-11-22 13:16:36 +00:00
8966897524
Forgot to alter RUN line when converting to FileCheck.
...
llvm-svn: 89588
2009-11-22 13:09:48 +00:00
7150767800
Fix for bad FileCheck converts in revision 89584.
...
llvm-svn: 89586
2009-11-22 12:50:05 +00:00
15dd46215e
Convert a few tests to FileCheck for PR5307.
...
llvm-svn: 89584
2009-11-22 11:45:44 +00:00
e09e95b35c
Revert 89562. We're being sneakier than I was giving us credit for, and this
...
isn't necessary.
llvm-svn: 89568
2009-11-21 23:34:09 +00:00
43fd822249
Darwin requires a frame pointer for all non-leaf functions to support correct
...
backtraces.
llvm-svn: 89562
2009-11-21 21:40:08 +00:00
4c83e2c253
Don't leave temporary files in the test directory.
...
llvm-svn: 89531
2009-11-21 02:05:31 +00:00
b91eba382d
When generating a vector the really slow way, via loads
...
and stores, handle the case where the element size is not
a valid target type correctly (PPC).
llvm-svn: 89521
2009-11-21 00:53:23 +00:00
73f9a9e2c8
Enable hoisting load from constant memories.
...
llvm-svn: 89510
2009-11-20 23:31:34 +00:00
c1f532e930
Recommitting PALIGNR shift width fixes.
...
Thanks to Daniel Dunbar for fixing clang intrinsics:
http://llvm.org/viewvc/llvm-project?view=rev&revision=89499
llvm-svn: 89500
2009-11-20 22:28:42 +00:00
8495a506eb
Remove an incorrect overaggressive optimization
...
(PPC specific).
llvm-svn: 89496
2009-11-20 22:16:40 +00:00
19d92728d0
Reverting PALIGNR fix until I figure out how this
...
broke the Clang testsuite.
llvm-svn: 89495
2009-11-20 22:09:28 +00:00
fbed130173
Fixed PALIGNR to take 8-bit rotations in all cases.
...
Also fixed the corresponding testcase, and the PALIGNR
intrinsic (tested for correctness with llvm-gcc).
llvm-svn: 89491
2009-11-20 21:40:28 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
...
llvm-svn: 89478
2009-11-20 19:57:15 +00:00
cc0a0cb4b7
Fix PR5558, which was caused by a wrong fix for PR3393 (see commit 63048),
...
which was an expensive checks failure due to a bug in the checking. This
patch in essence reverts the original fix for PR3393, and refixes it by a
tweak to the way expensive checking is done.
llvm-svn: 89454
2009-11-20 10:45:10 +00:00
20c8ab655e
Fix fast-isel to avoid selecting the return instruction if a
...
tail call has been encountered.
llvm-svn: 89444
2009-11-20 02:51:26 +00:00
bbd50b0f78
Also CSE non-pic load from constant pools.
...
llvm-svn: 89440
2009-11-20 02:10:27 +00:00
81a2851bcb
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
...
llvm-svn: 89423
2009-11-20 00:54:03 +00:00
0b2099ad5f
Unbreak test, Bruno please check.
...
llvm-svn: 89329
2009-11-19 07:18:49 +00:00
b18525937c
More consistent thumb1 asm printing.
...
llvm-svn: 89328
2009-11-19 06:57:41 +00:00
2a6c92fcb6
Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.
...
llvm-svn: 89326
2009-11-19 06:32:27 +00:00
4713b282ce
- Add sugregister logic to handle f64=(f32,f32).
...
- Support mips1 like load/store of doubles:
Instead of:
sdc $f0, X($3)
Generate:
swc $f0, X($3)
swc $f1, X+4($3)
llvm-svn: 89322
2009-11-19 06:06:13 +00:00
77f0ea6b93
Test from Dhrystone to make sure that we're not emitting an aligned load for a
...
string that's aligned at 8-bytes instead of 16-bytes.
llvm-svn: 89295
2009-11-19 01:33:57 +00:00
6456fb94f5
Fix buildbots.
...
llvm-svn: 89274
2009-11-18 23:30:38 +00:00
3bd09434a6
Add XCore support for indirectbr / blockaddress.
...
llvm-svn: 89273
2009-11-18 23:20:42 +00:00
108aadf972
Tail duplication still needs to iterate. Duplicating new instructions onto
...
the tail of a block may make that block a new candidate for duplication.
llvm-svn: 89264
2009-11-18 22:52:37 +00:00
575c3f3d72
Fix PR5300.
...
When TwoAddressInstructionPass deletes a dead instruction, make sure that all
register kills are accounted for. The 2-addr register does not get special
treatment.
llvm-svn: 89246
2009-11-18 21:33:35 +00:00
4797e58d6b
Fix inverted test and add testcase from failing self-host.
...
llvm-svn: 89167
2009-11-18 00:02:18 +00:00
50ee5e7ddb
Remove fragile test.
...
llvm-svn: 89150
2009-11-17 21:52:40 +00:00
cdde77c6a3
Enable arm jumpt table adjustment.
...
llvm-svn: 89143
2009-11-17 21:24:11 +00:00
a2873f4d59
Forgot to commit test fixes
...
llvm-svn: 89138
2009-11-17 20:38:36 +00:00
fffff88a3c
Enable -split-phi-edges by default, except when -regalloc=local.
...
The local register allocator doesn't like it when LiveVariables is run.
We should also disable edge splitting under -O0, but that has to wait a bit.
llvm-svn: 89125
2009-11-17 19:15:50 +00:00
84efacfaad
Revert 89021. It's miscompiling llvm-gcc driver driver at -O0.
...
llvm-svn: 89082
2009-11-17 09:55:52 +00:00
9f0d55d8d8
Enable -split-phi-edges by default
...
llvm-svn: 89021
2009-11-17 01:07:22 +00:00
d33400e636
MOV64rm should be marked isReMaterializable.
...
llvm-svn: 89019
2009-11-17 00:55:55 +00:00
0ad7efbace
Convert to FileCheck
...
llvm-svn: 89007
2009-11-17 00:20:26 +00:00
4781c3caf8
Convert to FileCheck
...
llvm-svn: 89002
2009-11-17 00:03:38 +00:00
805d195649
Cleanup. Missed removing these when converting. Oops.
...
llvm-svn: 89001
2009-11-17 00:00:33 +00:00
b43e1ff236
Fix this test - there don't appear to be any actual Reload Reuses
...
in this testcase.
llvm-svn: 88998
2009-11-16 23:49:55 +00:00
9dede3b383
Revert r87049, which was the workaround for the regression triggered
...
by the recent FixedStackPseudoSourceValue-related changes, now that
the specific bug that affected it is fixed, in r88954.
llvm-svn: 88997
2009-11-16 23:43:42 +00:00
1deb0b9f53
Convert to FileCheck
...
llvm-svn: 88991
2009-11-16 23:19:29 +00:00
f25ef4ffb0
- Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots.
...
- Mark MOVUPSrm re-materializable.
llvm-svn: 88974
2009-11-16 21:56:03 +00:00
9b32e22ad1
Convert to FileCheck
...
llvm-svn: 88947
2009-11-16 20:04:15 +00:00
16f6b3e607
Added a testcase for PR5495.
...
llvm-svn: 88946
2009-11-16 20:03:13 +00:00
980d94164d
Convert to FileCheck
...
llvm-svn: 88942
2009-11-16 19:46:46 +00:00
c670bdc311
tbb opt off by default
...
llvm-svn: 88921
2009-11-16 17:24:45 +00:00
25905c8336
Support spill comments.
...
Have the asm printer emit a comment if an instruction is a spill or
reload and have the spiller mark copies it introdues so the asm printer
can also annotate those.
llvm-svn: 88911
2009-11-16 15:12:23 +00:00
597f7b6ee3
Check if subreg index is zero.
...
llvm-svn: 88899
2009-11-16 06:31:49 +00:00
11bf4493d4
For some targets, a copy can use a register multiple times, e.g. ppc.
...
llvm-svn: 88895
2009-11-16 05:52:06 +00:00
8ca5d4b9ad
xfail for now. It has been failing.
...
llvm-svn: 88892
2009-11-16 05:44:04 +00:00
537e409c58
- Fix a small bug while handling target constant pools (one param was missing).
...
- Add a smarter constant pool loading, instead of:
lui $2, %hi($CPI1_0)
addiu $2, $2, %lo($CPI1_0)
lwc1 $f0, 0($2)
Generate:
lui $2, %hi($CPI1_0)
lwc1 $f0, %lo($CPI1_0)($2)
llvm-svn: 88886
2009-11-16 04:33:42 +00:00
01c1cae34d
Detect need for autoalignment of the stack earlier to catch spills more
...
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
llvm-svn: 88874
2009-11-15 21:45:34 +00:00
f16a3b7a9f
remove xfail
...
llvm-svn: 88817
2009-11-14 21:57:35 +00:00
d5f2745965
Add XCore support for arbitrary-sized aggregate returns.
...
llvm-svn: 88802
2009-11-14 19:33:35 +00:00
16797a1f55
Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to replace broken code in VirtRegRewriter.
...
llvm-svn: 88753
2009-11-14 03:42:17 +00:00
6ad7da96fe
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
...
- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
llvm-svn: 88745
2009-11-14 02:55:43 +00:00
e3b312fec9
Add radar number.
...
llvm-svn: 88739
2009-11-14 02:11:32 +00:00
d2c10508cd
Fix PR5412: Fix an inverted check and another missing sub-register check.
...
llvm-svn: 88738
2009-11-14 02:09:09 +00:00
a627e26d39
Enable the tail call optimization when the caller returns undef.
...
llvm-svn: 88737
2009-11-14 02:06:30 +00:00
66401c90da
When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
...
llvm-svn: 88734
2009-11-14 01:50:00 +00:00
78fa302e7d
Fix PR5411. Bug in UpdateKills. A reg def partially define its super-registers.
...
llvm-svn: 88719
2009-11-13 23:16:41 +00:00
225fa59cac
When optimizing for size, don't tail-merge unless it's likely to be a
...
code-size win, and not when it's only likely to be code-size neutral,
such as when only a single instruction would be eliminated and a new
branch would be required.
This fixes rdar://7392894.
llvm-svn: 88692
2009-11-13 21:02:15 +00:00
d190b8216f
Fix PR5410: LiveVariables lost subreg def:
...
D0<def,dead> = ...
...
= S0<use, kill>
S0<def> = ...
...
D0<def> =
The first D0 def is correctly marked dead, however, livevariables should have
added an implicit def of S0 or we end up with a use without a def.
llvm-svn: 88690
2009-11-13 20:36:40 +00:00
f80dc08059
Don't let a noalias difference disrupt the tailcall optimization.
...
llvm-svn: 88672
2009-11-13 18:49:38 +00:00
5f4eecf961
Adjust isConstantSplat to allow for big-endian targets.
...
PPC is such a target; make it work.
llvm-svn: 87060
2009-11-13 01:45:18 +00:00
3f75f5ddcb
Update test.
...
llvm-svn: 87049
2009-11-13 01:01:58 +00:00
1025a4998b
Clean up testcase a bit. Simplify case blocks and adjust switch instruction to not take an undefined value as input.
...
llvm-svn: 86997
2009-11-12 17:19:09 +00:00
5218176bc6
Fix typo in run line.
...
llvm-svn: 86984
2009-11-12 12:35:27 +00:00
5d85a46f76
RegScavenger::enterBasicBlock should always reset register state.
...
llvm-svn: 86972
2009-11-12 07:49:10 +00:00
85a9f430e9
- Teach LSR to avoid changing cmp iv stride if it will create an immediate that
...
cannot be folded into target cmp instruction.
- Avoid a phase ordering issue where early cmp optimization would prevent the
later count-to-zero optimization.
- Add missing checks which could cause LSR to reuse stride that does not have
users.
- Fix a bug in count-to-zero optimization code which failed to find the pre-inc
iv's phi node.
- Remove, tighten, loosen some incorrect checks disable valid transformations.
- Quite a bit of code clean up.
llvm-svn: 86969
2009-11-12 07:35:05 +00:00
09478e975d
Tail merge at any size when there are two potentials blocks and one
...
can be made to fall through into the other.
llvm-svn: 86909
2009-11-12 00:39:10 +00:00
9f34406a90
x86 users can now return arbitrary sized structs. Structs too large to fit in return registers will be returned through a hidden sret parameter introduced during SelectionDAG construction.
...
llvm-svn: 86876
2009-11-11 19:59:24 +00:00
64b5d0f468
Add support for tail duplication to BranchFolding, and extend
...
tail merging support to handle more cases.
- Recognize several cases where tail merging is beneficial even when
the tail size is smaller than the generic threshold.
- Make use of MachineInstrDesc::isBarrier to help detect
non-fallthrough blocks.
- Check for and avoid disrupting fall-through edges in more cases.
llvm-svn: 86871
2009-11-11 19:48:59 +00:00
7e5e40c75e
Add nounwind.
...
llvm-svn: 86814
2009-11-11 07:11:02 +00:00
d656f8ec4c
Fix test to work on every platform.
...
llvm-svn: 86786
2009-11-11 01:44:22 +00:00
5831283cb5
Fix test to work on every platform.
...
llvm-svn: 86785
2009-11-11 01:41:32 +00:00
676f44062e
Make sure that the exception handling data has the same visibility as the
...
function it's generated for.
llvm-svn: 86779
2009-11-11 01:24:59 +00:00
47739b20fd
Test this on Darwin only.
...
llvm-svn: 86752
2009-11-10 23:18:33 +00:00
6f7d5b22bb
Emit correct code when making a ConstantPool entry for a vector
...
constant whose component type is not a legal type for the target.
(If the target ConstantPool cannot handle this type either, it has
an opportunity to merge elements. In practice any target with
8-bit bytes must support i8 *as data*). 7320806 (partial).
llvm-svn: 86751
2009-11-10 23:16:41 +00:00
fc9469f311
Modify how the prologue encoded the "move" information for the FDE. GCC
...
generates a sequence similar to this:
__Z4funci:
LFB2:
mflr r0
LCFI0:
stmw r30,-8(r1)
LCFI1:
stw r0,8(r1)
LCFI2:
stwu r1,-80(r1)
LCFI3:
mr r30,r1
LCFI4:
where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other
things are. We generated something more like this:
Leh_func_begin1:
mflr r0
stw r31, 20(r1)
stw r0, 8(r1)
Llabel1:
stwu r1, -80(r1)
Llabel2:
mr r31, r1
Note that we are missing the "mr" instruction. This patch makes it more like the
GCC output.
llvm-svn: 86729
2009-11-10 22:14:04 +00:00
f8a74fc4a5
Add testcase for recent checkin.
...
llvm-svn: 86620
2009-11-09 23:10:49 +00:00
47e3bcf180
Update test
...
llvm-svn: 86614
2009-11-09 22:59:01 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
...
llvm-svn: 86494
2009-11-09 00:11:35 +00:00
700c4ab3f9
Add and-not (bic) patterns. Based heavily on patch by Brian Lucas!
...
llvm-svn: 86471
2009-11-08 15:33:12 +00:00
4ca8d3a6a6
Fix invalid operand updates & implement post-inc memory operands
...
llvm-svn: 86466
2009-11-08 14:27:38 +00:00
dc2beaa05e
It is invalid to infer the value type from the result #0 of the node
...
since the instruction might use the other result of different type.
llvm-svn: 86462
2009-11-08 12:14:54 +00:00
3a313df69b
x86 vector shuffle cleanup/fixes:
...
1. rename the movhp patfrag to movlhps, since thats what it actually matches
2. eliminate the bogus movhps load and store patterns, they were incorrect. The load transforms are already handled (correctly) by shufps/unpack.
3. revert a recent test change to its correct form.
llvm-svn: 86415
2009-11-07 23:17:15 +00:00
d3c8319f48
Add some dummy support for post-incremented loads
...
llvm-svn: 86385
2009-11-07 17:15:06 +00:00
f93bb39b03
Add 8 bit libcalls and make use of them for msp430
...
llvm-svn: 86384
2009-11-07 17:14:39 +00:00
2a88785685
Initial support for addrmode handling. Tests by Brian Lucas!
...
llvm-svn: 86382
2009-11-07 17:13:35 +00:00
226467d6a6
It turns out that the testcase in question uncovered subreg-handling bug.
...
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.
llvm-svn: 86375
2009-11-07 15:20:32 +00:00
bd05185ef1
Fix a couple of shuffle patterns to use movhlps instead
...
of movhps as the constraint. Changes optimizations so
update testcases as appropriate as well.
llvm-svn: 86360
2009-11-07 08:45:53 +00:00
8e1d7222a7
Fix PR5421 by APInt'izing switch lowering.
...
llvm-svn: 86354
2009-11-07 07:50:34 +00:00
74ab6efbe8
merge cmp1 into cmp0 and filecheckize.
...
llvm-svn: 86345
2009-11-07 06:19:20 +00:00
a8e8a7c976
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
...
llvm-svn: 86330
2009-11-07 04:04:34 +00:00
7ff831962a
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
...
except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
llvm-svn: 86328
2009-11-07 03:52:02 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
...
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
9df3acf486
Honour subreg machine operands during asmprinting
...
llvm-svn: 86303
2009-11-06 23:45:15 +00:00
d95ccd6c4d
Print VMOV (immediate) operands as hexadecimal values. Apple's assembler
...
will not accept negative values for these. LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates. Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.
llvm-svn: 86301
2009-11-06 23:33:28 +00:00
db42ca663b
Fix a broken test.
...
llvm-svn: 86298
2009-11-06 23:06:42 +00:00
408aa56fb5
Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead.
...
llvm-svn: 86294
2009-11-06 22:24:13 +00:00
80f04dc67d
Fix PR5315, original patch by Nicolas Capens!
...
llvm-svn: 86203
2009-11-06 00:11:57 +00:00
98693a3ac2
Update these tests for the new label names.
...
llvm-svn: 86192
2009-11-05 23:31:40 +00:00
45119d8850
Add -mtriple to llc commands, attempting to fix buildbot failures.
...
llvm-svn: 86086
2009-11-05 00:51:31 +00:00
90d0b82e12
Attempt again to fix buildbot failures: make expected output less specific
...
and compile with -mtriple to specify *-apple-darwin targets.
llvm-svn: 86081
2009-11-05 00:30:35 +00:00
f84f7105f7
Add PowerPC codegen for indirect branches.
...
llvm-svn: 86050
2009-11-04 21:31:18 +00:00
e8ca96cf24
Fix broken test.
...
llvm-svn: 86045
2009-11-04 20:04:11 +00:00
16f60b9216
Add test for ARM indirectbr codegen.
...
llvm-svn: 86042
2009-11-04 19:25:34 +00:00
95bdc5d899
RangeIsDefinedByCopyFromReg() should check for subreg_to_reg, insert_subreg,
...
and extract_subreg as a "copy" that defines a valno.
Also fixes a typo. These two issues prevent a simple subreg coalescing from
happening before.
llvm-svn: 86022
2009-11-04 08:33:14 +00:00
8f4e3d99c9
Fix test.
...
llvm-svn: 85986
2009-11-04 00:42:33 +00:00
0410bced1c
fconsts / fconstd immediate should be proceeded with #.
...
llvm-svn: 85952
2009-11-03 21:59:33 +00:00
f42b5af549
Re-apply 85799. It turns out my code isn't buggy.
...
llvm-svn: 85947
2009-11-03 21:40:02 +00:00
90fedc6ef9
Make opt default to not adding a target data string and update tests that depend on target data to supply it within the test
...
llvm-svn: 85900
2009-11-03 15:29:06 +00:00
8d681f0471
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
...
llvm-svn: 85871
2009-11-03 05:52:54 +00:00
a21bc75d78
Declare sin & cos as readonly so they match the code in SelectionDAGBuild
...
llvm-svn: 85853
2009-11-03 02:19:31 +00:00
2c2dc9f64f
Temporary xfail until PR5367 will be resolved
...
llvm-svn: 85848
2009-11-03 00:37:36 +00:00
fbe0256b23
Revert r85049, it is causing PR5367
...
llvm-svn: 85847
2009-11-03 00:24:48 +00:00
a8a58efc03
Revert 85799 for now. It might be breaking llvm-gcc driver.
...
llvm-svn: 85827
2009-11-02 21:49:14 +00:00
2729543984
Initilize the machine LICM CSE map upon the first time an instruction is hoisted to
...
the loop preheader. Add instructions which are already in the preheader block that
may be common expressions of those that are hoisted out. These does get a few more
instructions CSE'ed.
llvm-svn: 85799
2009-11-02 08:09:49 +00:00
fb2d385221
Remove an irrelevant and poorly reduced test case.
...
llvm-svn: 85794
2009-11-02 07:11:54 +00:00
1708b06c0e
Unbreak ARMBaseRegisterInfo::copyRegToReg.
...
llvm-svn: 85787
2009-11-02 04:44:55 +00:00
4d23754b14
Handle splats of undefs properly. This includes the testcase for PR5364 as well.
...
llvm-svn: 85767
2009-11-02 00:12:06 +00:00
8cce1eb6aa
64-bit FP loads & stores operate on both NEON and VFP pipelines.
...
llvm-svn: 85765
2009-11-02 00:11:06 +00:00
43219997b6
Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
...
llvm-svn: 85743
2009-11-01 21:12:51 +00:00
50bc004b67
Fix tests.
...
llvm-svn: 85723
2009-11-01 18:13:29 +00:00
50ba5c3dc2
improve x86 codegen support for blockaddress. We now compile
...
the testcase into:
_test1: ## @test1
## BB#0: ## %entry
leaq L_test1_bb6(%rip), %rax
jmpq *%rax
L_test1_bb: ## Address Taken
LBB1_1: ## %bb
movb $1, %al
ret
L_test1_bb6: ## Address Taken
LBB1_2: ## %bb6
movb $2, %al
ret
Note, it is very very strange that BlockAddressSDNode doesn't carry
around TargetFlags. Dan, please fix this.
llvm-svn: 85703
2009-11-01 03:25:03 +00:00
6f29ad9170
Use cbz and cbnz instructions.
...
llvm-svn: 85698
2009-10-31 23:46:45 +00:00
5cba8de2c8
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
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them for scalar floating point operations for now.
llvm-svn: 85697
2009-10-31 22:57:36 +00:00
403202aef1
Consolidate test files
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llvm-svn: 85696
2009-10-31 22:20:56 +00:00
c79fb530d4
Change to use FileCheck
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llvm-svn: 85695
2009-10-31 22:16:14 +00:00
69f364babc
Make tests more explicit about which instructions are expected.
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llvm-svn: 85694
2009-10-31 22:14:17 +00:00
259c37cc55
Grammar tweak to comments
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llvm-svn: 85693
2009-10-31 22:12:44 +00:00
2c3e618a06
Update test to be more explicit about what instruction sequences are expected for each operation.
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llvm-svn: 85691
2009-10-31 22:10:38 +00:00
0de95af62d
Update test to be more explicit about what instruction sequences are expected for each operation.
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llvm-svn: 85689
2009-10-31 21:52:58 +00:00
8fe6fd702d
Expand 64-bit logical shift right inline
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llvm-svn: 85687
2009-10-31 21:42:19 +00:00
624fcb286e
Expand 64-bit arithmetic shift right inline
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llvm-svn: 85685
2009-10-31 21:00:56 +00:00
6ef6fe1c31
Force triple; darwin's ASM syntax differs from linux's.
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llvm-svn: 85676
2009-10-31 19:54:06 +00:00
5d994048dd
Expand 64 bit left shift inline rather than using the libcall. For now, this
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is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.
llvm-svn: 85675
2009-10-31 19:38:01 +00:00
7e06083a3a
Add missing colons for FileCheck.
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llvm-svn: 85674
2009-10-31 19:22:24 +00:00
bf1cb1343f
Convert to FileCheck
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llvm-svn: 85673
2009-10-31 19:06:53 +00:00
cdbb70c065
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
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llvm-svn: 85643
2009-10-31 03:39:36 +00:00
ea88910dbf
Add a target triple so that this test behaves consistently across hosts.
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llvm-svn: 85640
2009-10-31 00:15:28 +00:00
10eed3788d
Fix the -mattr line for this test so that it passes on hosts that lack SSSE3.
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llvm-svn: 85637
2009-10-30 23:18:27 +00:00
49fa51d936
Fix MachineLICM to use the correct virtual register class when
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unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.
llvm-svn: 85622
2009-10-30 22:18:41 +00:00
28f052fc89
I forgot to commit this test.
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llvm-svn: 85608
2009-10-30 20:03:40 +00:00
ab7c709f43
This fixes functions like
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void f (int a1, int a2, int a3, int a4, int a5,...)
In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.
llvm-svn: 85590
2009-10-30 14:33:14 +00:00
3ab552ec74
Reimplement BranchFolding change to avoid tail merging for a 1 instruction
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common tail, except when the OptimizeForSize function attribute is present.
Radar 7338114.
llvm-svn: 85441
2009-10-28 22:10:20 +00:00
1b44f10ff4
Teach MachineLICM to unfold loads from constant memory from
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otherwise unhoistable instructions in order to allow the loads
to be hoisted.
llvm-svn: 85364
2009-10-28 03:21:57 +00:00
4a609f3cef
Use fconsts and fconstd to materialize small fp constants.
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llvm-svn: 85362
2009-10-28 01:44:26 +00:00
4b46cbfc23
Mark dead physregdefs dead immediately. This helps MachineSink and
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MachineLICM and other things which run before LiveVariables is run.
llvm-svn: 85360
2009-10-28 01:13:53 +00:00
75d6a4afd2
Allow constants of different types to share constant pool entries
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if they have compatible encodings.
llvm-svn: 85359
2009-10-28 01:12:16 +00:00
d92a3633e1
Add missing testcase.
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llvm-svn: 85266
2009-10-27 17:59:03 +00:00
3d43b38f0f
Fix Thumb2 failures by converting them to FileCheck.
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llvm-svn: 85210
2009-10-27 06:31:02 +00:00
d169e6c281
Fix the rest of the ARM failures by converting them to FileCheck.
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llvm-svn: 85208
2009-10-27 06:16:45 +00:00
04580c8307
Fix some more failures by converting to FileCheck.
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llvm-svn: 85207
2009-10-27 05:50:28 +00:00
e8d20795a3
Convert to FileCheck, fixing failure due to tab change in the process.
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llvm-svn: 85204
2009-10-27 05:30:47 +00:00
8370485db9
Break anti-dependence breaking out into its own class.
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llvm-svn: 85127
2009-10-26 16:59:04 +00:00
Evan Cheng