737718d4f4
Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1),
...
when needed. This fixes PR7001
llvm-svn: 102838
2010-05-01 12:52:34 +00:00
319d71f44f
Do folding for indirect branches, where possible
...
llvm-svn: 102836
2010-05-01 12:28:21 +00:00
ebbdfef2fc
Implement indirect branches on MSP430
...
llvm-svn: 102835
2010-05-01 12:04:32 +00:00
02bc6787ca
Test failing too much on too many platforms.
...
llvm-svn: 102812
2010-05-01 00:12:33 +00:00
06cacb1291
Maybe it needs sse2?
...
llvm-svn: 102802
2010-04-30 23:19:29 +00:00
613fb7daa6
Force 64-bit.
...
llvm-svn: 102800
2010-04-30 22:45:20 +00:00
de4b225093
EXTRACT_VECTOR_ELT of an INSERT_VECTOR_ELT may have the same index, but the
...
indexes could be of a different value type. Or not even using the same SDNode
for the constant (weird, I know). Compare the actual values instead of the
pointers.
llvm-svn: 102791
2010-04-30 22:19:17 +00:00
9afed0f98b
The local register allocator has to spill dirty callee saved registers before a
...
call that might throw. The landing pad assumes that all registers are in stack
slots.
We used to spill those dirty CSRs after the call, and the stack slots would be
wrong when arriving at the landing pad.
llvm-svn: 102770
2010-04-30 21:19:29 +00:00
5f2314f3a3
Fix test.
...
llvm-svn: 102694
2010-04-30 06:00:56 +00:00
5117a555e0
Another sibcall bug. If caller and callee calling conventions differ, then it's only safe to do a tail call if the results are returned in the same way.
...
llvm-svn: 102683
2010-04-30 01:12:32 +00:00
8d4214578d
Reject really weird coalescer case when trying to merge identical subregisters
...
of different register classes. e.g.
%reg1048:3<def> = EXTRACT_SUBREG %RAX<kill>, 3
Where %reg1048 is a GR32 register. This is not impossible to handle, but it is
pretty hard and very rare.
This should unbreak the dragonegg builder.
llvm-svn: 102672
2010-04-29 23:47:46 +00:00
38dfa5cf20
Load folding tail call should not use ebp / rbp after it's popped. PEI
...
should use esp / rsp to reference frame instead.
llvm-svn: 102596
2010-04-29 05:08:22 +00:00
08e9e72fa9
Rework global alignment computation again. Now we do round up
...
alignment of globals to the preferred alignment, but only when
there is no section specified on the global (by far the common
case).
llvm-svn: 102515
2010-04-28 19:58:07 +00:00
050df1b8de
Enable i16 to i32 promotion by default.
...
llvm-svn: 102493
2010-04-28 08:30:49 +00:00
fe420adde0
Update tests.
...
llvm-svn: 102487
2010-04-28 01:53:13 +00:00
50c9431203
Emit debug info for byval parameters.
...
llvm-svn: 102486
2010-04-28 01:39:28 +00:00
eb828b6391
Do not count kill, implicit_def instructions as printed instructions.
...
llvm-svn: 102453
2010-04-27 19:38:45 +00:00
64d43d80be
round zero-byte .zerofill directives up to 1 byte. This
...
should fix some "g++.dg-struct-layout-1" failures,
rdar://7886017
llvm-svn: 102421
2010-04-27 07:41:44 +00:00
6a5e706e3c
on darwin empty functions need to codegen into something of non-zero length,
...
otherwise labels get incorrectly merged. We handled this by emitting a
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes. Handle this by emitting a noop. This
is more gross than it should be because arm/ppc are not fully mc'ized yet.
This fixes rdar://7908505
llvm-svn: 102400
2010-04-26 23:37:21 +00:00
25f85947a3
Handle register-to-register copies within the tGPR class.
...
Radar 7896289
llvm-svn: 102396
2010-04-26 23:20:08 +00:00
58b0470592
When checking whether the special handling for an addrec increment which
...
doesn't dominate the header is needed, don't check whether the increment
expression has computable loop evolution. While the operands of an
addrec are required to be loop-invariant, they're not required to
dominate any part of the loop. This fixes PR6914.
llvm-svn: 102389
2010-04-26 21:46:36 +00:00
f740a8ceeb
fix PR6921 a different way. Intead of increasing the
...
alignment of globals with a specified alignment, we fix
common variables to obey their alignment. Add a comment
explaining why this behavior is important.
llvm-svn: 102365
2010-04-26 18:46:46 +00:00
e80442aa6d
Revert r102300/102301, which serious broke objc apps.
...
llvm-svn: 102359
2010-04-26 18:30:45 +00:00
386a220f70
Fix PR6921: globals were not getting correctly rounded up to their
...
preferred alignment unless they were common or some other special
case.
llvm-svn: 102300
2010-04-25 05:30:43 +00:00
534ba376f6
Generalize LSR's OptimizeMax to handle the new kinds of max expressions
...
that indvars may use, now that indvars is recognizing le and ge loops.
llvm-svn: 102235
2010-04-24 03:13:44 +00:00
c8b2fc0909
Per Chris, fuse four trivial tests using grep (r102199) into one that uses FileCheck.
...
llvm-svn: 102216
2010-04-23 22:12:57 +00:00
e1931fa676
Change TargetData's algorithm for computing defualt vector type
...
alignment to match what's used in clang and GCC for __alignof, rather
than trying to guess what Legalize is going to be doing.
llvm-svn: 102206
2010-04-23 19:41:15 +00:00
24b63f1597
Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029.
...
llvm-svn: 102199
2010-04-23 19:03:32 +00:00
997bbc54d6
Fix LSR to tolerate cases where ScalarEvolution initially
...
misses an opportunity to fold add operands, but folds them
after LSR has separated them out. This fixes rdar://7886751.
llvm-svn: 102157
2010-04-23 01:55:05 +00:00
825cb299cd
Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
...
extraction. This fixes PR5998.
llvm-svn: 102144
2010-04-22 23:24:18 +00:00
02e816b317
Do not try to optimize a copy that has already been marked for deletion.
...
llvm-svn: 102027
2010-04-21 20:57:54 +00:00
4158a0ff6b
Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
...
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181
llvm-svn: 101984
2010-04-21 03:18:23 +00:00
2034d9f2da
- Clean up some crappy code which deals with coalescing of copies which look at
...
extract_subreg / insert_subreg, etc.
- Add support for more aggressive insert_subreg coalescing.
llvm-svn: 101971
2010-04-21 00:44:22 +00:00
ad33d33719
Add another variant of this test which found a place where
...
CodeGen's ComputeMaskedBits was being over-conservative when computing
bits for an ADD.
llvm-svn: 101963
2010-04-21 00:19:28 +00:00
84776786a7
teach the x86 address matching stuff to handle
...
(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.
This finishes off PR1135. Before we compiled the block to:
to:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
leaq 2(%rdx), %r9
movl %esi, (%rdi,%r9,4)
leaq 1(%rdx), %r9
movl %esi, (%rdi,%r9,4)
addq $3, %rdx
movl %esi, (%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
Now we produce:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
movl %esi, 8(%rdi,%rdx,4)
movl %esi, 4(%rdi,%rdx,4)
movl %esi, 12(%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
llvm-svn: 101958
2010-04-20 23:18:40 +00:00
a8ae1783b4
Move CodeGen/X86/2010-04-19-DAGCombineCrash.ll into CodeGen/X86/crash.ll. Also
...
reduce.
llvm-svn: 101925
2010-04-20 18:14:47 +00:00
5100367ff3
Bill's change in r95336 broke empty aggregates embedded
...
in other types. fix this by only bumping zero-byte globals
up to a single byte if the *entire global* is zero size,
fixing PR6340.
This also fixes empty arrays etc to be handled correctly,
and only does this on subsection-via-symbols targets (aka
darwin) which is the only place where this matters.
llvm-svn: 101879
2010-04-20 06:20:21 +00:00
38c1a1a247
teach cellspu how to return i8 and i16 from calls,
...
patch by Kalle Raiskila!
llvm-svn: 101875
2010-04-20 05:36:09 +00:00
467e6c2deb
The visitXOR method can return the same SDNode. If so, we don't want to delete
...
it as it's not dead.
llvm-svn: 101855
2010-04-20 01:25:01 +00:00
92a4685dd2
Fix tests for Neon load/store intrinsics to match the i8* types expected by
...
the intrinsics. The reason for those i8* types is that the intrinsics are
overloaded on the vector type and we don't have a way to declare an intrinsic
where one argument is an overloaded vector type and another argument is a
pointer to the vector element type. The bitcasts added here will match what
the frontend will typically generate when these intrinsics are used.
llvm-svn: 101840
2010-04-20 00:17:16 +00:00
fbe8d2803d
Fix declarations in a few more tests.
...
llvm-svn: 101676
2010-04-17 21:29:25 +00:00
0a8d91a816
fix PR6332, allowing an index of zero into a zero sized array
...
even if the element of the array has no size.
llvm-svn: 101662
2010-04-17 19:02:33 +00:00
4fee6f3bdd
Start function numbering at 0.
...
llvm-svn: 101638
2010-04-17 16:29:15 +00:00
3af19e80c9
Add nounwind.
...
llvm-svn: 101613
2010-04-17 03:43:36 +00:00
dc6d42dbf8
Add test case for machine-sink on critical edges
...
llvm-svn: 101416
2010-04-15 23:19:16 +00:00
f7f97b4bbd
Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.
...
llvm-svn: 101410
2010-04-15 22:20:34 +00:00
b642a27525
Fix PR6847. RegScavenger should ignore DebugValues.
...
llvm-svn: 101392
2010-04-15 20:28:39 +00:00
1ba1428577
ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908
...
llvm is generating poor code for dynamic alloca, I'll fix that later.
llvm-svn: 101383
2010-04-15 18:42:28 +00:00
3245afdf05
enhance the load/store narrowing optimization to handle a
...
tokenfactor in between the load/store. This allows us to
optimize test7 into:
_test7: ## @test7
## BB#0: ## %entry
movl (%rdx), %eax
## kill: SIL<def> ESI<kill>
movb %sil, 5(%rdi)
ret
instead of:
_test7: ## @test7
## BB#0: ## %entry
movl 4(%esp), %ecx
movl $-65281, %eax ## imm = 0xFFFFFFFFFFFF00FF
andl 4(%ecx), %eax
movzbl 8(%esp), %edx
shll $8, %edx
addl %eax, %edx
movl 12(%esp), %eax
movl (%eax), %eax
movl %edx, 4(%ecx)
ret
llvm-svn: 101355
2010-04-15 06:10:49 +00:00
6ebd8674eb
teach codegen to turn trunc(zextload) into load when possible.
...
This doesn't occur much at all, it only seems to formed in the case
when the trunc optimization kicks in due to phase ordering. In that
case it is saves a few bytes on x86-32.
llvm-svn: 101350
2010-04-15 05:40:59 +00:00
Anton Korobeynikov