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5 Commits

Author SHA1 Message Date
Simon Atanasyan 52efd67369 [mips] Move test case for Octeon instructions to cnmips sub-folder. NFC 2019-11-04 00:42:31 +03:00
Simon Dardis d886aba39d [mips] Correct the predicates of the load/store (double)word for coprocessor 3. 
llvm-svn: 329913
 2018-04-12 14:41:38 +00:00
Daniel Sanders 837f15187b [mips] Range check simm10 
Summary:

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D18148

llvm-svn: 264279
 2016-03-24 13:26:59 +00:00
Hrvoje Varga 46458d0bcc [mips][microMIPS] Implement DINSU, DINSM, DINS instructions 
Differential Revision: http://reviews.llvm.org/D16181

llvm-svn: 261860
 2016-02-25 12:53:29 +00:00
Daniel Sanders daa4b6fbd9 [mips][ias] Range check uimm5 operands and fix several bugs this revealed. 
Summary:
The bugs were:
* append, prepend, and balign were not tested
* balign takes a uimm2 not a uimm5.
* drotr32 was correctly implemented with a uimm5 but the tests expected
  '52' to be valid.
* li/la were implemented with a uimm5 instead of simm32. simm32 isn't
  completely correct either but I'll fix that when I get to simm32.

A notable omission are some of the shift instructions. Several of these
have been implemented using a single uimm6 instruction (rather than two
uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated
in the uimm6 patch.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D14712

llvm-svn: 254164
 2015-11-26 16:35:41 +00:00