maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
166,261 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

158 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen 6f39ce4be2 Clean up the Legal/Expand logic for SPARC popc. 
llvm-svn: 200141
 2014-01-26 08:12:34 +00:00
Jakob Stoklund Olesen ead3b3d7a1 Only generate the popc instruction for SPARC CPUs that implement it. 
The popc instruction is defined in the SPARCv9 instruction set
architecture, but it was emulated on CPUs older than Niagara 2.

llvm-svn: 200131
 2014-01-26 06:09:59 +00:00
Jakob Stoklund Olesen 39f0833f47 Fix swapped CASA operands. 
Found by SingleSource/UnitTests/AtomicOps.c

llvm-svn: 200130
 2014-01-26 06:09:54 +00:00
Jakob Stoklund Olesen 05ae2d6715 Implement atomicrmw operations in 32 and 64 bits for SPARCv9. 
These all use the compare-and-swap CASA/CASXA instructions.

llvm-svn: 199975
 2014-01-24 06:23:31 +00:00
Venkatraman Govindaraju dd634cac74 [Sparc] Add support for inline assembly constraints which specify registers by their aliases. 
llvm-svn: 199786
 2014-01-22 03:18:42 +00:00
Venkatraman Govindaraju 407e442245 [Sparc] Add support for inline assembly constraint 'I'. 
llvm-svn: 199781
 2014-01-22 01:29:51 +00:00
Venkatraman Govindaraju f52927fb1b [Sparc] Do not add PC to _GLOBAL_OFFSET_TABLE_ address to access GOT in absolute code. 
Fixes PR#18521

llvm-svn: 199775
 2014-01-22 00:13:18 +00:00
Jakob Stoklund Olesen b6b35a4955 Always let value types influence register classes. 
When creating a virtual register for a def, the value type should be
used to pick the register class. If we only use the register class
constraint on the instruction, we might pick a too large register class.

Some registers can store values of different sizes. For example, the x86
xmm registers can hold f32, f64, and 128-bit vectors. The three
different value sizes are represented by register classes with identical
register sets: FR32, FR64, and VR128. These register classes have
different spill slot sizes, so it is important to use the right one.

The register class constraint on an instruction doesn't necessarily care
about the size of the value its defining. The value type determines
that.

This fixes a problem where InstrEmitter was picking 32-bit register
classes for 64-bit values on SPARC.

llvm-svn: 199187
 2014-01-14 06:18:38 +00:00
Jakob Stoklund Olesen 1995b9fead Handle bundled terminators in isBlockOnlyReachableByFallthrough. 
Targets like SPARC and MIPS have delay slots and normally bundle the
delay slot instruction with the corresponding terminator.

Teach isBlockOnlyReachableByFallthrough to find any MBB operands on
bundled terminators so SPARC doesn't need to specialize this function.

llvm-svn: 199061
 2014-01-12 19:24:08 +00:00
Jakob Stoklund Olesen e7084a1c5c The SPARCv9 ABI returns a float in %f0. 
This is different from the argument passing convention which puts the
first float argument in %f1.

With this patch, all returned floats are treated as if the 'inreg' flag
were set. This means multiple float return values get packed in %f0,
%f1, %f2, ...

Note that when returning a struct in registers, clang will set the
'inreg' flag on the return value, so that behavior is unchanged. This
also happens when returning a float _Complex.

llvm-svn: 199028
 2014-01-12 04:13:17 +00:00
Venkatraman Govindaraju a66b314c34 [Sparc] Add missing processor types: v7 and niagara 
llvm-svn: 199024
 2014-01-11 23:56:13 +00:00
Benjamin Kramer c10563d14e Fix broken CHECK lines. 
llvm-svn: 199016
 2014-01-11 21:06:00 +00:00
Venkatraman Govindaraju 0653218b2b [Sparc] Bundle instruction with delay slow and its filler. Now, we can use -verify-machineinstrs with SPARC backend. 
llvm-svn: 199014
 2014-01-11 19:38:03 +00:00
Venkatraman Govindaraju ad40dfcb4b [Sparc] Emit retl/ret instead of jmp instruction. It improves the readability of the assembly generated. 
llvm-svn: 198910
 2014-01-10 02:55:27 +00:00
Venkatraman Govindaraju 96ab3bc5bd [SparcV9]: Implement RETURNADDR and FRAMEADDR lowering in SPARC64. 
Fixes PR18356.

llvm-svn: 198480
 2014-01-04 07:17:21 +00:00
Venkatraman Govindaraju 9a3da52ea2 [Sparc] Handle atomic loads/stores in sparc backend. 
llvm-svn: 198286
 2014-01-01 22:11:54 +00:00
Venkatraman Govindaraju 77011e861b [SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to __multi3() in correct order. 
llvm-svn: 198281
 2014-01-01 20:22:45 +00:00
Venkatraman Govindaraju acf0233a46 [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does. 
llvm-svn: 198280
 2014-01-01 19:00:10 +00:00
Venkatraman Govindaraju 3e3a29a2e9 [SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns. 
This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot.

llvm-svn: 198157
 2013-12-29 07:15:09 +00:00
Venkatraman Govindaraju 5ac9c8faec [SparcV9] For codegen generated library calls that return float, set inreg flag manually in LowerCall(). 
This makes the sparc backend to generate Sparc64 ABI compliant code.

llvm-svn: 198149
 2013-12-29 04:27:21 +00:00
Venkatraman Govindaraju 0776cc0acd [SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI. 
Also, pass fp128 arguments to varargs through integer registers if necessary.

llvm-svn: 198145
 2013-12-29 01:20:36 +00:00
Venkatraman Govindaraju bf683fd15c [Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter. 
llvm-svn: 198030
 2013-12-26 01:49:59 +00:00
Venkatraman Govindaraju 61116e7084 [SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack BIAS on sparcV9. 
llvm-svn: 196755
 2013-12-09 05:13:25 +00:00
Venkatraman Govindaraju f6c8fe983b [Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that umulo/smulo can be lowered on sparcv9 without an assertion error. 
llvm-svn: 196751
 2013-12-09 04:02:15 +00:00
Venkatraman Govindaraju 72cc248524 [SparcV9]: Expand MULHU/MULHS:i64 and UMUL_LOHI/SMUL_LOHI:i64 on sparcv9. 
This fixes PR18150.

llvm-svn: 196735
 2013-12-08 22:06:07 +00:00
Venkatraman Govindaraju 1116868a0d [Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64. 
llvm-svn: 195576
 2013-11-24 20:23:25 +00:00
Venkatraman Govindaraju f79528c132 [SparcV9]: Do not emit .register directives for global registers that are clobbered by calls but not used in the function itself. 
llvm-svn: 195574
 2013-11-24 18:41:49 +00:00
Venkatraman Govindaraju 0510db0597 [SparcV9] Enable custom lowering of DYNAMIC_STACKALLOC in sparc64. 
llvm-svn: 195573
 2013-11-24 17:41:41 +00:00
Venkatraman Govindaraju 5ae77f7564 [SparcV9] Handle i64 <-> float conversions in sparcv9 mode. 
llvm-svn: 193957
 2013-11-03 12:28:40 +00:00
Venkatraman Govindaraju f1d807ee13 [Sparc] Expand FP_TO_UINT, UINT_TO_FP for fp128. 
llvm-svn: 193947
 2013-11-03 08:00:19 +00:00
Venkatraman Govindaraju 5615aca219 [SparcV9] Add ctpop instruction for i64. Also, expand ctlz, cttz and bswap. 
llvm-svn: 193941
 2013-11-03 05:59:07 +00:00
Roman Divacky 2262cfaf19 SparcV9 doesnt have rem instruction either. 
llvm-svn: 193789
 2013-10-31 19:22:33 +00:00
Venkatraman Govindaraju 8812485d41 [Sparc] Disable tail call optimization for sparc64. 
This patch fixes PR17506.

llvm-svn: 192294
 2013-10-09 12:50:39 +00:00
Venkatraman Govindaraju f482d3d338 [Sparc] Do not emit nop after fcmp* instruction with V9. 
llvm-svn: 192056
 2013-10-06 07:06:44 +00:00
Venkatraman Govindaraju 572d5057e3 [Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64. 
This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes.

llvm-svn: 192054
 2013-10-06 03:36:18 +00:00
Venkatraman Govindaraju 1230342fd2 [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx. 
addx/subx does not modify conditional codes whereas addxcc/subxx does.

llvm-svn: 192053
 2013-10-06 02:11:10 +00:00
Venkatraman Govindaraju ece63dbd0d [Sparc] Use correct alignment while loading/storing fp128 values. 
llvm-svn: 192023
 2013-10-05 02:29:47 +00:00
Venkatraman Govindaraju 30781deb1c [Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with fp128 operand. 
llvm-svn: 192015
 2013-10-05 00:31:41 +00:00
Venkatraman Govindaraju 84f1523cac [Sparc] Correct the floating point conditional code mapping in GetOppositeBranchCondition(). 
llvm-svn: 192006
 2013-10-04 23:54:30 +00:00
Manman Ren adf4cc171e TBAA: update tbaa format from scalar format to struct-path aware format. 
llvm-svn: 191690
 2013-09-30 18:17:55 +00:00
Venkatraman Govindaraju 4c0cdd734c [Sparc] Implements exception handling in SPARC with DwarfCFI. 
llvm-svn: 191432
 2013-09-26 15:11:00 +00:00
Venkatraman Govindaraju cb1dca602c [Sparc] Add support for TLS in sparc. 
llvm-svn: 191164
 2013-09-22 06:48:52 +00:00
Venkatraman Govindaraju 7e7eb8ce69 [SPARC] Make functions with GLOBAL_OFFSET_TABLE access as non-leaf functions. 
llvm-svn: 191160
 2013-09-22 01:40:24 +00:00
Venkatraman Govindaraju e9ef51222b [Sparc] Emit .register directive to declare the use of global registers %g2, %g4, %g6 and %g7. 
llvm-svn: 191158
 2013-09-22 00:42:30 +00:00
Venkatraman Govindaraju 829aec5900 [Sparc] Fix lowering FABS on fp128 (long double) on pre-v9 targets. 
llvm-svn: 191154
 2013-09-21 23:51:08 +00:00
Venkatraman Govindaraju 55ecb10e99 [Sparc] Correctly handle call to functions with ReturnsTwice attribute. 
In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores
the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7)
using the stored %fp and register windows. However, this does not guarantee that the longjmp
will restore the registers, as they were when the setjmp was called. This is because these
registers may be clobbered after returning from setjmp, but before calling longjmp.

This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask.  

llvm-svn: 190033
 2013-09-05 05:32:16 +00:00
Venkatraman Govindaraju b803cec00e [Sparc] Fix an assertion failure while lowering fcmp on long double. 
This assertion is triggered because an integer constant is created with wrong
  type.

llvm-svn: 189948
 2013-09-04 15:15:20 +00:00
Venkatraman Govindaraju 59039dc1bf [Sparc] Add support for soft long double (fp128). 
llvm-svn: 189780
 2013-09-03 04:11:59 +00:00
Venkatraman Govindaraju 01cb19f93c [Sparc] Implement spill and load for long double(f128) registers. 
llvm-svn: 189768
 2013-09-02 18:32:45 +00:00
Venkatraman Govindaraju 35e0c382d5 [Sparc] Add long double (f128) instructions to sparc backend. 
llvm-svn: 189198
 2013-08-25 18:30:06 +00:00