Commit Graph

278 Commits

Author SHA1 Message Date
Dan Gohman be8137b0b4 Replace TargetInstrInfo::isInvariantLoad and its target-specific
implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.

llvm-svn: 83475
2009-10-07 17:38:06 +00:00
Chris Lattner fdd8790718 strength reduce a ton of type equality tests to check the typeid (Through
the new predicates I added) instead of going through a context and doing a
pointer comparison.  Besides being cheaper, this allows a smart compiler
to turn the if sequence into a switch.

llvm-svn: 83297
2009-10-05 05:54:46 +00:00
Devang Patel b296942f6d Remove std::string uses from DebugInfo interface.
llvm-svn: 83083
2009-09-29 18:40:58 +00:00
Dan Gohman 5a6b11cb71 Move MachineMemOperand::getAlignment out of line, to avoid needing
MathExtras.h in MachineMemOperand.h.

llvm-svn: 82822
2009-09-25 23:33:20 +00:00
Dan Gohman 48b185d6f7 Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.

llvm-svn: 82794
2009-09-25 20:36:54 +00:00
Dan Gohman c0353bfff5 Give MachineMemOperand an operator<<, factoring out code from
two different places for printing MachineMemOperands.

Drop the virtual from Value::dump and instead give Value a
protected virtual hook that can be overridden by subclasses
to implement custom printing. This lets printing be more
consistent, and simplifies printing of PseudoSourceValue
values.

llvm-svn: 82599
2009-09-23 01:33:16 +00:00
Dan Gohman e7c8242baa Change MachineMemOperand's alignment value to be the alignment of
the base pointer, without the offset. This matches MemSDNode's
new alignment behavior, and holds more interesting information.

llvm-svn: 82473
2009-09-21 19:47:04 +00:00
Jim Grosbach 9632c14949 grammar
llvm-svn: 82150
2009-09-17 17:57:26 +00:00
Chris Lattner 471ba48cb9 remove some uses of llvm/Support/Streams.h
llvm-svn: 79842
2009-08-23 08:43:55 +00:00
Chris Lattner a6f074fb3a remove various std::ostream version of printing methods from
MachineInstr and MachineOperand.  This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)

llvm-svn: 79813
2009-08-23 03:41:05 +00:00
Owen Anderson 55f1c09e31 Push LLVMContexts through the IntegerType APIs.
llvm-svn: 78948
2009-08-13 21:58:54 +00:00
Jakob Stoklund Olesen f465f06aa4 Don't tamper with <undef> operands in MachineInstr::addRegisterKilled.
For an undef operand, MO.getReg() is meaningless and we should not use it.
Undef operands should be skipped entirely.

llvm-svn: 78095
2009-08-04 20:09:25 +00:00
Jakob Stoklund Olesen 5d8ace0902 Fix Bug 4657: register scavenger asserts with subreg lowering
When LowerSubregsInstructionPass::LowerInsert eliminates an INSERT_SUBREG
instriction because it is an identity copy, make sure that the same registers
are alive before and after the elimination.

When the super-register is marked <undef> this requires inserting an
IMPLICIT_DEF instruction to make sure the super register is live.

Fix a related bug where a kill flag on the inserted sub-register was not transferred properly.

Finally, clear the undef flag in MachineInstr::addRegisterKilled. Undef implies dead and kill implies live, so they cant both be valid.

llvm-svn: 77989
2009-08-03 20:08:18 +00:00
Jakob Stoklund Olesen c59cd9bcd0 Never add a kill flag to a constrained physical register in a two-addr instruction.
llvm-svn: 77906
2009-08-02 19:13:03 +00:00
Evan Cheng 4a04041056 Fix a typo.
llvm-svn: 77369
2009-07-28 21:49:18 +00:00
Jakob Stoklund Olesen aba695c7d0 Fix http://llvm.org/bugs/show_bug.cgi?id=4583
Inline asm instructions may have additional <imp-def,kill> register operands.
These operands are not marked with a flag like the normal asm operands, so we
must not assert that there is a flag.

llvm-svn: 76373
2009-07-19 19:09:59 +00:00
Jakob Stoklund Olesen 070fab8a1f Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands.
The inline asm operands must be parsed from the first flag, you cannot assume
that an immediate operand preceeding a register use operand is the flag.
PowerPC "m" operands are represented as (flag, imm, reg) triples.
isRegTiedToDefOperand() would incorrectly interpret the imm as the flag.

llvm-svn: 76101
2009-07-16 20:58:34 +00:00
Torok Edwin fbcc663cbf llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640
2009-07-14 16:55:14 +00:00
Torok Edwin 56d0659726 assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.

llvm-svn: 75379
2009-07-11 20:10:48 +00:00
Evan Cheng 0dc101b897 Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.

llvm-svn: 74518
2009-06-30 08:49:04 +00:00
Chris Lattner fd682802e3 Rearrange some stuff in MachineOperand and add a new TargetFlags field.
llvm-svn: 74087
2009-06-24 17:54:48 +00:00
Evan Cheng 38f2453817 Fix support for inline asm input / output operand tying when operand spans across multiple registers (e.g. two i64 operands in 32-bit mode).
llvm-svn: 74053
2009-06-24 02:05:51 +00:00
Dan Gohman d9ef48a73e Remove some unnecessary #includes.
llvm-svn: 72948
2009-06-05 16:32:58 +00:00
Argyrios Kyrtzidis a5037484a4 Make DebugLoc independent of DwarfWriter.
-Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable*
-Remove DwarfWriter::getOrCreateSourceID
-Make necessary changes for the above (fix callsites, etc.)

llvm-svn: 70520
2009-04-30 23:22:31 +00:00
Jakob Stoklund Olesen 1971dc7007 MachineInstr::isRegTiedTo{Use,Def}Operand can safely be made const.
llvm-svn: 70408
2009-04-29 20:57:16 +00:00
Dan Gohman 37608532c4 Fix MachineInstr::getNumExplicitOperands to count
variadic operands correctly. Patch by Jakob Stoklund Olesen!

llvm-svn: 69190
2009-04-15 17:59:11 +00:00
Dan Gohman 89892b05c7 Give RemoveRegOperandFromRegInfo a comment and move the
code out of line.

llvm-svn: 69124
2009-04-15 01:17:37 +00:00
Chris Lattner 66ab904f5a ignore register zero in isRegTiedToUseOperand, following the example of
isRegTiedToDefOperand.  Thanks to Bob for pointing this out!

llvm-svn: 68734
2009-04-09 23:33:34 +00:00
Bob Wilson 51856173c8 Fix pr3954. The register scavenger asserts for inline assembly with
register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714
2009-04-09 17:16:43 +00:00
Chris Lattner a725028d41 reg0 references are not real registers. This fixes a crash on the
attached testcase.

llvm-svn: 68712
2009-04-09 16:50:43 +00:00
Evan Cheng 968c3b0d6e Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
llvm-svn: 67512
2009-03-23 08:01:15 +00:00
Evan Cheng 1361cbbb0b Added MachineInstr::isRegTiedToDefOperand to check for two-addressness.
llvm-svn: 67335
2009-03-19 20:30:06 +00:00
Bill Wendling 1a0a3d0ff5 Print out debug info when printing the machine instruction.
llvm-svn: 65067
2009-02-19 21:44:55 +00:00
Dale Johannesen 4e04ef3c55 Add a DebugLoc field and some simple accessors.
llvm-svn: 63152
2009-01-27 23:20:29 +00:00
Dan Gohman 072e52f170 Use isTerminator() instead of isBranch()||isReturn() in
several places. isTerminator() returns true for a superset
of cases, and includes things like FP_REG_KILL, which are
nither return or branch but aren't safe to move/remat/etc.

llvm-svn: 61373
2008-12-23 17:28:50 +00:00
Dan Gohman 0ab1144c79 Print subreg information in MachineInstr::dump.
llvm-svn: 61213
2008-12-18 21:51:27 +00:00
Dan Gohman 9356d8f74d Minor code simplification.
llvm-svn: 60804
2008-12-09 22:45:08 +00:00
Dan Gohman d24be45d99 Drop the reg argument to isRegReDefinedByTwoAddr, which was redundant.
llvm-svn: 60586
2008-12-05 05:45:42 +00:00
Dan Gohman 0b2732598c Add more const qualifiers. This fixes build breakage from r59540.
llvm-svn: 59542
2008-11-18 19:49:32 +00:00
Dan Gohman 0d9d8ae487 Make some methods const.
llvm-svn: 59540
2008-11-18 19:04:29 +00:00
Mon P Wang dfcc1ff8f8 Added missing print functions that take a raw_ostream
llvm-svn: 57339
2008-10-10 01:43:55 +00:00
Dan Gohman 0d1e9a8e04 Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.

llvm-svn: 57006
2008-10-03 15:45:36 +00:00
Dan Gohman 88536398ff Fix a think-o in isSafeToMove. This fixes it from thinking that
volatile memory references are safe to move.

llvm-svn: 56948
2008-10-02 15:04:30 +00:00
Dale Johannesen c36660d756 Next round of earlyclobber handling. Approach the
RA problem by expanding the live interval of an
earlyclobber def back one slot.  Remove
overlap-earlyclobber throughout.  Remove 
earlyclobber bits and their handling from
live internals.

llvm-svn: 56539
2008-09-24 01:07:17 +00:00
Dan Gohman 7c59ed6ff8 Add a method to MachineInstr for testing whether it makes
any volatile memory references.

llvm-svn: 56528
2008-09-24 00:06:15 +00:00
Dale Johannesen f8610ebebc Add a bit to mark operands of asm's that conflict
with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.

llvm-svn: 56290
2008-09-17 21:13:11 +00:00
Dale Johannesen c0d712d9ed adjust last patch per review feedback
llvm-svn: 56194
2008-09-14 01:44:36 +00:00
Dan Gohman 38453eebdc Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189
2008-09-13 17:58:21 +00:00
Dale Johannesen 1f3ab86804 Pass "earlyclobber" bit through to machine
representation; coalescer and RA need to know
about it.  No functional change.

llvm-svn: 56161
2008-09-12 17:49:03 +00:00
Dan Gohman c7367b4546 Fix addRegisterDead and addRegisterKilled to be more thorough
when searching for redundant subregister dead/kill bits.

Previously it was common to see instructions marked like this:
  "RET %EAX<imp-use,kill>, %AX<imp-use,kill>"

With this change, addRegisterKilled continues scanning after
finding the %EAX operand, so it proceeds to discover the
redundant %AX kill and eliminates it, producing this:
  "RET %EAX<imp-use,kill>"

This currently has no effect on the generated code.

llvm-svn: 55698
2008-09-03 15:56:16 +00:00