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98 Commits

Author SHA1 Message Date
Tom Stellard 3494b7ee42 R600/SI: Handle MSAA texture targets 
Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
llvm-svn: 188421
 2013-08-14 22:22:14 +00:00
Tom Stellard 20ee94f152 R600/SI: Allow conversion between v32i8 and v8i32 
Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
llvm-svn: 188420
 2013-08-14 22:22:09 +00:00
Tom Stellard 73c31d541e R600/SI: Add pattern for fp_to_uint 
This fixes the F2U opcode for the Mesa driver.

Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
llvm-svn: 188418
 2013-08-14 22:21:57 +00:00
Niels Ole Salscheider 6509ac65a9 R600/SI: Add FMA pattern 
llvm-svn: 188135
 2013-08-10 10:38:47 +00:00
Niels Ole Salscheider 719fbc9ae7 R600/SI: Implement fp32<->fp64 conversions 
llvm-svn: 187988
 2013-08-08 16:06:15 +00:00
Niels Ole Salscheider 4715d886f8 R600/SI: Implement sint<->fp64 conversions 
llvm-svn: 187987
 2013-08-08 16:06:08 +00:00
Tom Stellard 28d06de6f6 R600: Implement TargetLowering::getVectorIdxTy() 
We use MVT::i32 for the vector index type, because we use 32-bit
operations to caculate offsets when dynamically indexing vectors.

llvm-svn: 187749
 2013-08-05 22:22:07 +00:00
Tom Stellard 5263948a7b R600: Add support for 24-bit MAD instructions 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186923
 2013-07-23 01:48:49 +00:00
Tom Stellard 41fc7853be R600: Add support for 24-bit MUL instructions 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186922
 2013-07-23 01:48:42 +00:00
Tom Stellard 9f95033d33 R600: Improve support for < 32-bit loads 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186921
 2013-07-23 01:48:35 +00:00
Tom Stellard 33dd04bfbe R600: Clean up extended load patterns 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186914
 2013-07-23 01:47:52 +00:00
Tom Stellard 8374720aad R600/SI: Fix crash with VSELECT 
https://bugs.freedesktop.org/show_bug.cgi?id=66175

llvm-svn: 186616
 2013-07-18 21:43:53 +00:00
Tom Stellard adf732cfbc R600/SI: Add support for v2f32 loads 
llvm-svn: 186615
 2013-07-18 21:43:48 +00:00
Tom Stellard ed2f6149f3 R600/SI: Add support for v2f32 stores 
llvm-svn: 186614
 2013-07-18 21:43:42 +00:00
Tom Stellard 31209cc8eb R600/SI: Add support for 64-bit loads 
https://bugs.freedesktop.org/show_bug.cgi?id=65873

llvm-svn: 186339
 2013-07-15 19:00:09 +00:00
Tom Stellard 4e1100ab75 R600/SI: Implement select and compares for SI 
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186181
 2013-07-12 18:15:19 +00:00
Tom Stellard 8ed7b45da3 R600/SI: Add fsqrt pattern for SI 
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186180
 2013-07-12 18:15:13 +00:00
Tom Stellard 2a6a610516 R600/SI: Add double precision fsub pattern for SI 
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186179
 2013-07-12 18:15:08 +00:00
Tom Stellard ab8a8c84d4 R600/SI: SI support for 64bit ConstantFP 
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186178
 2013-07-12 18:15:02 +00:00
Tom Stellard 7512c0803c R600/SI: Add initial double precision support for SI 
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186177
 2013-07-12 18:14:56 +00:00
Michel Danzer 49812b5bbd R600/SI: Initial local memory support 
Enough for the radeonsi driver to use it for calculating derivatives.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186012
 2013-07-10 16:37:07 +00:00
Michel Danzer 1f87df365f R600/SI: Add pattern for the AMDGPU.barrier.local intrinsic 
lit test coverage to follow in the next commit.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186011
 2013-07-10 16:36:57 +00:00
Michel Danzer 8d69617b27 R600/SI: Add intrinsic for retrieving the current thread ID 
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186010
 2013-07-10 16:36:52 +00:00
Michel Danzer 1c45430e76 R600/SI: Initial support for LDS/GDS instructions 
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186009
 2013-07-10 16:36:43 +00:00
Michel Danzer 83f87c4c2e R600/SI: Add intrinsics for texture sampling with user derivatives 
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186008
 2013-07-10 16:36:36 +00:00
Tom Stellard 371573448c R600: Add SI load support for v[24]i32 and store for v2i32 
Also add a seperate vector lit test file, since r600 doesn't seem to handle
v2i32 load/store yet, but we can test both for SI.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 184021
 2013-06-15 00:09:31 +00:00
Tom Stellard a6c6e1bfc2 R600: Rework subtarget info and remove AMDILDevice classes 
This should simplify the subtarget definitions and make it easier to
add new ones.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183566
 2013-06-07 20:37:48 +00:00
Tom Stellard 07a10a3d3f R600/SI: Add support for global loads 
llvm-svn: 183131
 2013-06-03 17:39:43 +00:00
Tom Stellard 556d9aa841 R600/SI: Rework MUBUF store instructions 
The lowering of stores is now mostly handled in the tablegen files.  No
more BUFFER_STORE nodes I generated during legalization.

llvm-svn: 183130
 2013-06-03 17:39:37 +00:00
Tom Stellard f1ee716446 R600/SI: Use a multiclass for MUBUF_Load_Helper 
This will simplify the instructions and also the pattern definitions.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182288
 2013-05-20 15:02:31 +00:00
Tom Stellard b8458f88d6 R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182287
 2013-05-20 15:02:28 +00:00
Tom Stellard d2eebf001e R600/SI: Add pattern for rotr 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182286
 2013-05-20 15:02:24 +00:00
Tom Stellard 1cfd7a50bb R600/SI: Add patterns for 64-bit shift operations 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182284
 2013-05-20 15:02:12 +00:00
Tom Stellard f787ef1d96 R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181269
 2013-05-06 23:02:19 +00:00
Tom Stellard 353b336e8c R600/SI: Add intrinsic for texture image loading 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181267
 2013-05-06 23:02:12 +00:00
Tom Stellard c932d7329c R600/SI: Add pattern for uint_to_fp 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181266
 2013-05-06 23:02:07 +00:00
Tom Stellard cf6452c7d4 R600/SI: Add patterns for integer maxima / minima 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181265
 2013-05-06 23:02:04 +00:00
Tom Stellard 9b3d2535bf R600/SI: Add pattern for AMDGPU.trunc intrinsic 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181263
 2013-05-06 23:02:00 +00:00
Tom Stellard eac65dde30 R600: Add pattern for SHA-256 Ma function 
This can be optimized using the BFI_INT instruction.

llvm-svn: 181033
 2013-05-03 17:21:20 +00:00
Tom Stellard 40b7f1f6c3 R600: Use new tablegen syntax for patterns 
All but two patterns have been converted to the new syntax.  The
remaining two patterns will require COPY_TO_REGCLASS instructions, which
the VLIW DAG Scheduler cannot handle.

llvm-svn: 180922
 2013-05-02 15:30:12 +00:00
Tom Stellard 5447ae20ff R600/SI: remove nonsense select pattern 
Fortunately this pattern never matched, otherwise
we would have generated incorrect code.

Signed-off-by: Christian K??nig <christian.koenig@amd.com>
llvm-svn: 180921
 2013-05-02 15:30:07 +00:00
Tom Stellard 9d10c4ce86 R600: Add pattern for the BFI_INT instruction 
llvm-svn: 179830
 2013-04-19 02:11:06 +00:00
Tom Stellard ea977bc0e3 R600/SI: Use InstFlag for VOP3 modifier operands 
InstFlag has a default value of 0 and will simplify the VOP3 patterns.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179829
 2013-04-19 02:11:00 +00:00
Michel Danzer 8caa904bde R600/SI: Add pattern for AMDGPUurecip 
21 more little piglits with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 179186
 2013-04-10 17:17:56 +00:00
Christian Konig 4ace663255 R600/SI: remove image sample writemask 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179164
 2013-04-10 08:39:01 +00:00
Tom Stellard 754f80ff3a R600/SI: Add support for buffer stores v2 
v2:
  - Use the ADDR64 bit

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178931
 2013-04-05 23:31:51 +00:00
Christian Konig 08f5929942 R600/SI: add SETO/SETUO patterns 
6 more piglit tests.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178145
 2013-03-27 15:27:31 +00:00
Christian Konig 3c14580acb R600/SI: add cummuting of rev instructions 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178127
 2013-03-27 09:12:59 +00:00
Christian Konig 70a5032c1b R600/SI: add mulhu/mulhs patterns 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178126
 2013-03-27 09:12:51 +00:00
Christian Konig 20a7e6b764 R600/SI: add srl/sha patterns for SI 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178125
 2013-03-27 09:12:44 +00:00