0f4ecf7548
Change name of class to ArithOverflowR.
...
llvm-svn: 141743
2011-10-11 23:43:48 +00:00
8f0d549c4c
Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical
...
instructions with two register operands derive from it.
llvm-svn: 141742
2011-10-11 23:38:52 +00:00
2d3ea9b2f2
Make this test more specific. There are 3 stats that matched "machine-licm".
...
llvm-svn: 141741
2011-10-11 23:34:31 +00:00
4035859cb8
Use public accessors on the scope that is returned.
...
llvm-svn: 141739
2011-10-11 23:19:35 +00:00
8d4f74a6b1
Fix comment.
...
llvm-svn: 141737
2011-10-11 23:12:12 +00:00
ae5a9d6578
Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit
...
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.
llvm-svn: 141736
2011-10-11 23:05:46 +00:00
7bd0ea3487
target data is a contract with the code generator, not the "processor"
...
llvm-svn: 141734
2011-10-11 23:02:17 +00:00
487974042e
improve some of the documentation around target data layout strings.
...
llvm-svn: 141733
2011-10-11 23:01:39 +00:00
6647b83087
Add a new wrapper node for a DILexicalBlock that encapsulates it and a
...
file. Since it should only be used when necessary propagate it through
the backend code generation and tweak testcases accordingly.
This helps with code like in clang's test/CodeGen/debug-info-line.c where
we have multiple #line directives within a single lexical block and want
to generate only a single block that contains each file change.
Part of rdar://10246360
llvm-svn: 141729
2011-10-11 22:59:11 +00:00
57d1692750
Formatting.
...
llvm-svn: 141728
2011-10-11 22:59:04 +00:00
cbce39c8b9
Spacing.
...
llvm-svn: 141727
2011-10-11 22:58:58 +00:00
579ff6c39c
N.B. This is with the new EH scheme:
...
The blocks with invokes have branches to the dispatch block, because that more
correctly models the behavior of the CFG. The dispatch of course has edges to
the landing pads. Those landing pads could contain invokes, which then have
branches back to the dispatch. This creates a loop. The machine LICM pass looks
at this loop and thinks it can hoist elements out of it. But because the
dispatch is an alternate entry point into the program, the hoisted instructions
won't be executed.
I wasn't able to get a testcase which was small and could reproduce all of the
time. The function_try_block.cpp in llvm-test was where this showed up.
llvm-svn: 141726
2011-10-11 22:42:31 +00:00
1c18465859
Fix function isUnalignedLoadStore.
...
llvm-svn: 141722
2011-10-11 22:04:01 +00:00
9398141c48
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
...
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
llvm-svn: 141721
2011-10-11 21:55:36 +00:00
10ae11fd57
Remove unused PatLeaf.
...
llvm-svn: 141720
2011-10-11 21:53:08 +00:00
453ac88b56
Change the names of 64-bit logical instructions so that they match the names of
...
the real instructions.
llvm-svn: 141718
2011-10-11 21:48:01 +00:00
265328baf6
Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...
...
llvm-svn: 141716
2011-10-11 21:40:47 +00:00
46a7994ac9
Remove redundancy in setcc patterns using multiclass.
...
llvm-svn: 141715
2011-10-11 21:40:01 +00:00
1a761dcfbd
Fix PR11106 by correcting a typo that has been in the code for over a year. This
...
would have never worked, since the element type of a vector type is never a
vector type. Also fix the conditional to be more direct in checking whether
EltTy is a vector type.
llvm-svn: 141713
2011-10-11 21:26:40 +00:00
8c1c51045d
Use sltiu instead of sltu when a register operand and immediate are compared.
...
llvm-svn: 141708
2011-10-11 20:44:43 +00:00
8c799c9826
Update test for r141704.
...
llvm-svn: 141705
2011-10-11 20:18:50 +00:00
12b2889989
ARM addressing mode cleanup for LDC/STC.
...
We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.
llvm-svn: 141704
2011-10-11 20:17:35 +00:00
037fc9311a
Clean up a few references to System/. We still have docs/SystemLibrary.html
...
lying around...
llvm-svn: 141703
2011-10-11 20:02:52 +00:00
55dbf03e40
Support/DataTypes.h: Clean up some types and add matching (but presumably
...
unused) code from .cmake to DataTypes.h.in so that the files are essentially in
sync module differences in autoconf/cmake replacement syntax.
llvm-svn: 141702
2011-10-11 20:02:49 +00:00
6878b1f233
Remove extra semicolon.
...
llvm-svn: 141699
2011-10-11 19:53:40 +00:00
7148bce86e
Add patterns for conditional branches with 64-bit register operands.
...
llvm-svn: 141696
2011-10-11 19:09:09 +00:00
f75add6236
Add support for 64-bit set-on-less-than instructions.
...
llvm-svn: 141695
2011-10-11 18:53:46 +00:00
4b6ac98fcf
Add support for conditional branch instructions with 64-bit register operands.
...
llvm-svn: 141694
2011-10-11 18:49:17 +00:00
453d401a51
Add dominance check for the instruction being hoisted.
...
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.
llvm-svn: 141689
2011-10-11 18:09:58 +00:00
ff2c52ce63
Fixed docs to reflect the proper default value and behaviour of the natural stack alignment.
...
llvm-svn: 141687
2011-10-11 17:50:14 +00:00
27c579dba4
Expose MachOObjectFile externally, like we do for COFF. First step in reducing the amount of special-purpose code needed for llvm-objdump.
...
llvm-svn: 141684
2011-10-11 17:32:27 +00:00
a95ec99a96
ARM parse alignment specifier for NEON load/store instructions.
...
llvm-svn: 141682
2011-10-11 17:29:55 +00:00
1cb28fdd54
Mention the cmake build guide on the main docs page.
...
llvm-svn: 141674
2011-10-11 16:35:07 +00:00
871dff76df
ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity.
...
llvm-svn: 141671
2011-10-11 15:59:20 +00:00
3283793c9a
Add support for legalization of vector SHL/SRA/SRL instructions
...
llvm-svn: 141667
2011-10-11 14:36:35 +00:00
e8ae98a8d9
Implement the emitFrameIndexDebugValue and getDebugValueLocation hooks.
...
This fixes an assert due to the operands of the DBG_VALUE instruction not
being as expected (PR11105).
llvm-svn: 141666
2011-10-11 12:55:35 +00:00
68591286bc
Fix a iterator out of bounds error, that triggers rarely.
...
llvm-svn: 141665
2011-10-11 12:55:18 +00:00
bd926cbdb5
llvm-objdump.cpp: Use PRIx64 as format specifier for int64_t.
...
llvm-svn: 141664
2011-10-11 12:51:50 +00:00
c5554c9de3
Add -D__STDC_FORMAT_MACROS to use PRIx64.
...
llvm-svn: 141663
2011-10-11 12:51:44 +00:00
e63cd198ba
cmake/modules/HandleLLVMOptions.cmake: Reorder __STDC_CONSTANT_MACROS and __STDC_LIMIT_MACROS.
...
llvm-svn: 141662
2011-10-11 12:51:36 +00:00
198fe81571
Add support for legalization of vector trunc-store where the saved scalar type is illegal (for example, v2i16 on systems where the smallest store size is i32)
...
llvm-svn: 141661
2011-10-11 11:25:16 +00:00
b521b6037b
Cleanup the trunc-store legalization code and add asserts.
...
llvm-svn: 141659
2011-10-11 10:04:25 +00:00
c8a78ded33
Update to a newer doxygen version. PR8214. Patch by Jeremy Huddleston.
...
llvm-svn: 141657
2011-10-11 07:25:38 +00:00
63bc541196
Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as modifying EFLAGS.
...
llvm-svn: 141656
2011-10-11 07:13:09 +00:00
ffc3bd0e08
Minor modifications to make the Hello World example resemble the Hello World
...
pass in the tree. Also some minor formatting changes.
PR9413
llvm-svn: 141655
2011-10-11 07:03:52 +00:00
0fbca75c17
Make Ivy Bridge 16-bit floating point conversion instructions require AVX.
...
llvm-svn: 141654
2011-10-11 07:01:37 +00:00
3e01bd3b60
Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take
...
that into account and test for no U's showing up in the middle, which is what
we really wanted to test for.
llvm-svn: 141653
2011-10-11 06:58:11 +00:00
603cc851f8
Test case for X86 LZCNT instruction selection.
...
llvm-svn: 141652
2011-10-11 06:47:01 +00:00
271064e873
Add X86 LZCNT instruction. Including instruction selection support.
...
llvm-svn: 141651
2011-10-11 06:44:02 +00:00
b4d076e37e
Use the proper name for "externally visible" linkage -- 'external'. This is the
...
keyword in LLVM for externally visible linkage.
PR10636
llvm-svn: 141649
2011-10-11 06:41:28 +00:00
05d9151d2c
Reword the SetVector description to reflect reality.
...
Patch by Michael Ilseman!
llvm-svn: 141648
2011-10-11 06:33:56 +00:00
ab3a9b3baf
Add a test for PR10565.
...
llvm-svn: 141647
2011-10-11 06:10:37 +00:00
d7515ccc47
Remove a lot of the fancy scalar replacement code for dealing with llvm-gcc's
...
lowering of NEON code. It provides little-to-no benefit now and only introduces
additional complexity.
llvm-svn: 141646
2011-10-11 06:10:30 +00:00
288ff0ec82
Test simplification that Ana Pazos noticed.
...
llvm-svn: 141644
2011-10-11 04:43:15 +00:00
a697852386
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
...
llvm-svn: 141642
2011-10-11 04:34:23 +00:00
29e7b315ac
Also create a shndx even if there are no symbols. This lets us test
...
.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.
llvm-svn: 141641
2011-10-11 03:54:50 +00:00
ba38717f34
test/CodeGen/X86/movbe.ll: Give explicit -mtriple=x86_64-linux, to unbreak win32 hosts.
...
llvm-svn: 141640
2011-10-11 03:41:03 +00:00
43f01cae95
Reapply r141605 with fixes for appropriate handling of reserved section numbers
...
in st_shndx fields.
llvm-svn: 141639
2011-10-11 03:18:58 +00:00
7adc4370e0
Add support for .symtab_shnidx. Unfortunately, doing this required breaking a
...
layer of abstraction around SymbolRef where you can read its private
SymbolPimpl member.
llvm-svn: 141636
2011-10-11 02:57:48 +00:00
ecbe22bb8d
Add experimental -enable-lsr-phielim option.
...
I'm not sure we will need it in the long run, but the option is
currently useful for checking if the output of LSR is "clean".
llvm-svn: 141634
2011-10-11 02:30:45 +00:00
f9201c572e
Move replaceCongruentIVs into SCEVExapander and bias toward "expanded"
...
IVs.
Indvars previously chose randomly between congruent IVs. Now it will
bias the decision toward IVs that SCEVExpander likes to create. This
was not done to fix any problem, it's just a welcome side effect of
factoring code.
llvm-svn: 141633
2011-10-11 02:28:51 +00:00
8782734bcc
Test cases for 64-bit load and store instructions.
...
llvm-svn: 141631
2011-10-11 01:52:31 +00:00
44c78f809b
Added a testcase for r141599, rdar://problem/10063881.
...
llvm-svn: 141628
2011-10-11 01:32:10 +00:00
b6d72cbeb9
Make changes necessary for supporting floating point load and store instructions
...
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
llvm-svn: 141623
2011-10-11 01:12:52 +00:00
da7c0f8f7d
Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo().
...
The VMOVS widening needs to look at the implicit COPY operands. Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.
The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.
llvm-svn: 141619
2011-10-11 00:59:06 +00:00
09b23eb7bc
Modify lowering of GlobalAddress so that correct code is emitted when target is
...
Mips64.
llvm-svn: 141618
2011-10-11 00:55:05 +00:00
f22f46bf25
Fixed natural stack alignment for Linux x86-32. Thanks Eli.
...
llvm-svn: 141616
2011-10-11 00:51:36 +00:00
fa55bc27cb
Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too.
...
llvm-svn: 141615
2011-10-11 00:44:20 +00:00
35a90c4baf
Revert r141605 as it broke tests for llvm-nm.
...
llvm-svn: 141614
2011-10-11 00:38:56 +00:00
e6ced5b3d5
Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot.
...
llvm-svn: 141613
2011-10-11 00:37:28 +00:00
be68f3c348
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
...
zextloadi32 for which there is no corresponding pseudo or real instruction.
llvm-svn: 141608
2011-10-11 00:27:28 +00:00
9449b8b9d2
Add testcase for PR11107.
...
llvm-svn: 141607
2011-10-11 00:26:57 +00:00
cbb9140806
Make it possible to use the linker without destroying the source module. This is so the source module can be linked to multiple other destination modules. For all that used LinkModules() before, they will continue to destroy the source module as before.
...
This line, and those below, will be ignored--
M include/llvm/Linker.h
M tools/bugpoint/Miscompilation.cpp
M tools/bugpoint/BugDriver.cpp
M tools/llvm-link/llvm-link.cpp
M lib/Linker/LinkModules.cpp
llvm-svn: 141606
2011-10-11 00:24:54 +00:00
fdbb7c51e9
Add support for reading many-section ELF files.
...
If you want to tackle adding the testcase, let me know. It's a 4.2MB ELF file
and I'll be happy to mail it to you.
llvm-svn: 141605
2011-10-11 00:15:42 +00:00
fd2d7dcc31
Change definitions of classes LoadM and StoreM in preparation for adding support
...
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.
llvm-svn: 141603
2011-10-11 00:11:12 +00:00
98703350d0
Simplify check that optional def is there and is CPSR.
...
llvm-svn: 141602
2011-10-11 00:10:41 +00:00
de7ab801cc
Add a natural stack alignment field to TargetData, and prevent InstCombine from
...
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.
The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.
llvm-svn: 141599
2011-10-10 23:42:08 +00:00
ee3be4f2a9
Fix warning.
...
llvm-svn: 141597
2011-10-10 23:36:56 +00:00
478d5bc0d0
Revert r141569 and r141576.
...
llvm-svn: 141594
2011-10-10 23:18:02 +00:00
c11b7c3805
Simplify operand Kind checks a bit.
...
llvm-svn: 141592
2011-10-10 23:06:42 +00:00
a7d697e4a6
Reapply r141365 now that PR11107 is fixed.
...
llvm-svn: 141591
2011-10-10 22:59:55 +00:00
2957c88c0a
Add a name to sub-operand for clarity.
...
llvm-svn: 141590
2011-10-10 22:55:05 +00:00
0a10cdc704
If the CPSR is defined by a copy, then we don't want to merge it into an IT
...
block. E.g., if we have:
movs r1, r1
rsb r1, 0
movs r2, r2
rsb r2, 0
we don't want this to be converted to:
movs r1, r1
movs r2, r2
itt mi
rsb r1, 0
rsb r2, 0
PR11107 & <rdar://problem/10259534>
llvm-svn: 141589
2011-10-10 22:52:53 +00:00
8ec0897db6
Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102.
...
llvm-svn: 141585
2011-10-10 22:28:47 +00:00
7989460a1f
Object: add getSectionAlignment.
...
llvm-svn: 141581
2011-10-10 21:55:43 +00:00
fcf8462583
Add support for dumping section headers to llvm-objdump. This uses the same
...
flags as binutils objdump but the output is different, not just in format but
also showing different sections. Compare its results against readelf, not
objdump.
llvm-svn: 141579
2011-10-10 21:21:34 +00:00
add0c43ebb
Give targets a chance to expand even standard pseudos.
...
Allow targets to expand COPY and other standard pseudo-instructions
before they are expanded with copyPhysReg().
This allows the target to examine the COPY instruction for extra
operands indicating it can be widened to a preferable super-register
copy. See the ARM -widen-vmovs option.
llvm-svn: 141578
2011-10-10 20:34:28 +00:00
2689f95875
If loop header is also loop exiting block then it may not be safe to hoist instructions.
...
llvm-svn: 141576
2011-10-10 20:32:03 +00:00
a1ac0dab2d
Emit full ED initializers even for pseudo-instructions.
...
This should unbreak the picky buildbots.
llvm-svn: 141575
2011-10-10 20:15:49 +00:00
b9d67ccc23
Allow stat += 0 without activating the stat.
...
For me, this is a nice convenience. We generally want grep to match
stats output only when the event has occurred.
llvm-svn: 141574
2011-10-10 19:48:56 +00:00
d52dd324d6
whitespace
...
llvm-svn: 141572
2011-10-10 19:35:46 +00:00
874c519337
X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge.
...
llvm-svn: 141571
2011-10-10 19:35:07 +00:00
814598563f
Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the
...
instruction set has no 64-bit SRA support.
llvm-svn: 141570
2011-10-10 19:31:45 +00:00
e554d5995b
Add dominance check for the instruction being hoisted.
...
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.
llvm-svn: 141569
2011-10-10 19:09:20 +00:00
ba0bc4f522
Mark the standard pseudos as isPseudo = 1.
...
The difference between isPseudo and isCodeGenOnly is a bit murky, but
isCodeGenOnly should eventually go away. It is used for instructions
that are clones of real instructions with slightly different properties.
The standard pseudo-instructions never mirror real instructions, so they
are definitely in the isPseudo category.
llvm-svn: 141567
2011-10-10 18:51:33 +00:00
cc6659b2ae
The Mips specific function for instruction cache invalidation cannot be
...
compiled on mips32r1 processors because it uses synci and rdhwr instructions
which are supported only on mips32r2, so I replaced this function with the
call to function cacheflush which works for both mips32r1 and mips32r2.
Patch by Sasa Stankovic
llvm-svn: 141564
2011-10-10 18:41:02 +00:00
42c0330a79
X86: Add patterns for the movbe instruction (mov + bswap, only available on atom)
...
llvm-svn: 141563
2011-10-10 18:34:56 +00:00
b253f490c3
Insert dummy ED table entries for pseudo-instructions.
...
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.
Add a test case for xorps which has a very high opcode that exposes this
problem.
llvm-svn: 141562
2011-10-10 18:30:16 +00:00
47aac51043
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
...
hang, and possibly SPEC/CINT2006/464_h264ref.
llvm-svn: 141560
2011-10-10 18:27:30 +00:00
bed5504f5f
MCAtom extending methods need to extend the range of the atom as well.
...
llvm-svn: 141557
2011-10-10 18:09:38 +00:00
Akira Hatanaka