Matheus Almeida
cfc8871596
[mips] Move disassembler tests (Mips MSA test_elm*) into correct folder.
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llvm-svn: 208589
2014-05-12 16:23:45 +00:00
Matheus Almeida
04092f5bc5
[mips] Move disassembler tests (Mips MSA test_lsa, test_dlsa) into correct folder.
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llvm-svn: 208588
2014-05-12 16:20:46 +00:00
Matheus Almeida
7fd9339e38
[mips] Move disassembler test (Mips MSA test_ctrlregs) into correct folder.
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llvm-svn: 208587
2014-05-12 16:16:59 +00:00
Matheus Almeida
38a9a8b675
[mips] Move disassembler test (Mips MSA test_bit) into correct folder.
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llvm-svn: 208586
2014-05-12 16:10:00 +00:00
Matheus Almeida
b4fce72b32
[mips] Move disassembler tests (Mips MSA test_2r, test_2rf, test_3r, test_3rf) into
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correct folder.
llvm-svn: 208584
2014-05-12 16:03:20 +00:00
Vladimir Medic
43e978234a
This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.
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llvm-svn: 202706
2014-03-03 13:12:59 +00:00
Zoran Jovanovic
7d63392da9
LL and SC decoder method fix.
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llvm-svn: 199316
2014-01-15 13:17:33 +00:00
Zoran Jovanovic
d4cb61cf0e
Added support for LWU microMIPS instruction.
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llvm-svn: 199315
2014-01-15 13:01:18 +00:00
Zoran Jovanovic
ccb70caa13
Support for microMIPS trap instruction with immediate operands.
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llvm-svn: 194569
2013-11-13 13:15:03 +00:00
Zoran Jovanovic
c18b6d1083
Support for microMIPS trap instructions 1.
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llvm-svn: 194205
2013-11-07 14:35:24 +00:00
Zoran Jovanovic
8a80aa76c8
Support for microMIPS branch instructions.
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llvm-svn: 193992
2013-11-04 14:53:22 +00:00
Zoran Jovanovic
507e084a18
Support for microMIPS jump instructions
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llvm-svn: 193623
2013-10-29 16:38:59 +00:00
Benjamin Kramer
8a37f63714
Mips: Disassemble sign-extended 64 bit immediates properly.
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This doesn't change the meaning of the output, but makes look right. PR17539.
llvm-svn: 192483
2013-10-11 19:05:08 +00:00
Zoran Jovanovic
fc26cfcde7
Fixed bug when generating Load Upper Immediate microMIPS instruction.
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llvm-svn: 190746
2013-09-14 07:35:41 +00:00
Zoran Jovanovic
3671a5441a
Support for microMIPS DIV instructions.
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llvm-svn: 190745
2013-09-14 07:15:21 +00:00
Zoran Jovanovic
ab85278137
Support for misc microMIPS instructions.
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llvm-svn: 190744
2013-09-14 06:49:25 +00:00
Vladimir Medic
b936da159e
This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
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llvm-svn: 190154
2013-09-06 13:08:00 +00:00
Vladimir Medic
457ba56b05
This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
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llvm-svn: 190152
2013-09-06 12:53:21 +00:00
Vladimir Medic
e0fbb44a48
This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
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llvm-svn: 190148
2013-09-06 12:41:17 +00:00
Vladimir Medic
dde3d582a2
This patch adds support for microMIPS disassembler and disassembler make check tests.
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llvm-svn: 190144
2013-09-06 12:30:36 +00:00
Akira Hatanaka
9bfa2e2e7f
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
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Also, fix predicates.
llvm-svn: 189432
2013-08-28 00:55:15 +00:00
Daniel Dunbar
9efbedfd35
[tests] Cleanup initialization of test suffixes.
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- Instead of setting the suffixes in a bunch of places, just set one master
list in the top-level config. We now only modify the suffix list in a few
suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py).
- Aside from removing the need for a bunch of lit.local.cfg files, this enables
4 tests that were inadvertently being skipped (one in
Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and
CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been
XFAILED).
- This commit also fixes a bunch of config files to use config.root instead of
older copy-pasted code.
llvm-svn: 188513
2013-08-16 00:37:11 +00:00
Akira Hatanaka
8bce21c154
[mips] Fix FP conditional move instructions to have explicit FP condition code
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register operands.
llvm-svn: 187242
2013-07-26 20:51:20 +00:00
Akira Hatanaka
1fb1b8b811
[mips] Fix FP branch instructions to have explicit FP condition code register
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operands.
llvm-svn: 187238
2013-07-26 20:13:47 +00:00
Akira Hatanaka
53900e5124
[mips] Print instructions "beq", "bne" and "or" using assembler pseudo
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instructions "beqz", "bnez" and "move", when possible.
beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or $2, $3, $zero => move $2, $3
llvm-svn: 187229
2013-07-26 18:34:25 +00:00
Akira Hatanaka
263c6af8f3
[mips] Increase the number of floating point control registers available to 32.
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Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.
llvm-svn: 185373
2013-07-01 20:31:44 +00:00
Chad Rosier
253777fdc3
[Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg
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function to lookup the proper tablegen'ed register enumeration. Previously,
it was using the encoded value directly.
llvm-svn: 185026
2013-06-26 22:23:32 +00:00
Akira Hatanaka
59bfaf774b
[mips] DSP-ASE move from HI/LO register instructions.
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llvm-svn: 179739
2013-04-18 00:52:44 +00:00
Nico Rieck
334c7bc7eb
Use object file specific section type for initial text section
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llvm-svn: 179494
2013-04-14 21:18:36 +00:00
Jack Carter
2a74a87b71
This is a resubmittal. For some reason it broke the bots yesterday
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but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
llvm-svn: 172685
2013-01-17 00:28:20 +00:00
Jack Carter
5619f91bf7
reverting 172579
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llvm-svn: 172594
2013-01-16 01:29:10 +00:00
Jack Carter
e0c1e1a47e
Akira,
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Hope you are feeling better.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
llvm-svn: 172579
2013-01-16 00:07:45 +00:00
Jakub Staszak
0c4468b5e6
Remove DOS line endings.
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llvm-svn: 167968
2012-11-14 20:18:34 +00:00
Akira Hatanaka
d0836fd20a
[mips] Fix disassembler test cases.
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llvm-svn: 167326
2012-11-02 22:20:10 +00:00
Akira Hatanaka
a13cd0666e
Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck.
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Patch by Vladimir Medic.
llvm-svn: 160143
2012-07-12 21:19:32 +00:00
Akira Hatanaka
9bf2b5677d
Reapply r158846.
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Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.
llvm-svn: 159953
2012-07-09 18:46:47 +00:00
Akira Hatanaka
b577ff116d
revert r159851.
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llvm-svn: 159854
2012-07-06 20:16:48 +00:00
Akira Hatanaka
cfa35fa0ff
Reapply r158846.
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Include file MipsGenRegisterInfo.inc.
llvm-svn: 159851
2012-07-06 19:29:11 +00:00
Akira Hatanaka
87505f46ac
Revert r158846.
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llvm-svn: 158855
2012-06-20 21:19:39 +00:00
Akira Hatanaka
da448fe0b1
In MipsDisassembler.cpp, instead of defining register class tables, use the ones
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that are generated by TableGen and are already available in
MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen.
Also, fix bug in function DecodeAFGR64RegisterClass.
Patch by Vladimir Medic.
llvm-svn: 158846
2012-06-20 20:39:23 +00:00
Akira Hatanaka
c13ed945aa
Add lit.local.cfg to run the tests in test/MC/Disassembler/Mips.
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llvm-svn: 157725
2012-05-31 00:49:56 +00:00
Akira Hatanaka
71928e681b
Add disassembler to MIPS.
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Patch by Vladimir Medic.
llvm-svn: 154935
2012-04-17 18:03:21 +00:00
Akira Hatanaka
d19f025374
Revert r153924. Delete test/MC/Disassembler/Mips and lib/Target/Mips/Disassembler.
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llvm-svn: 153926
2012-04-03 03:01:13 +00:00
Akira Hatanaka
55059262aa
Revert r153924. There were buildbot failures.
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llvm-svn: 153925
2012-04-03 02:51:09 +00:00
Akira Hatanaka
e2498d014b
MIPS disassembler support.
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Patch by Vladimir Medic.
llvm-svn: 153924
2012-04-03 02:20:58 +00:00