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5 Commits

Author SHA1 Message Date
Fangrui Song f66b767abe [ELF][AArch64] Allow PT_LOAD to have overlapping p_offset ranges 
Ported the D64906 technique to AArch64. It deletes 3 alignments at
PT_LOAD boundaries for the default case: the size of an aarch64 binary
decreases by at most 192kb.

If `sh_addralign(.tdata) < sh_addralign(.tbss)`,
we can potentially make `p_vaddr(PT_TLS)%p_align(PT_TLS) != 0`.

ld.so that are known to have problems if p_vaddr%p_align!=0:

* musl<=1.1.22
* FreeBSD 13.0-CURRENT (and before) rtld-elf arm64

New test aarch64-tls-vaddr-align.s checks that our workaround makes p_vaddr%p_align = 0.

Reviewed By: ruiu

Differential Revision: https://reviews.llvm.org/D64930

llvm-svn: 369344
 2019-08-20 08:34:56 +00:00
Fangrui Song 5387c2cd17 [llvm-objdump] Print newlines before and after "Disassembly of section ...:" 
This improves readability and the behavior is consistent with GNU objdump.

The new test test/tools/llvm-objdump/X86/disassemble-section-name.s
checks we print newlines before and after "Disassembly of section ...:"

Differential Revision: https://reviews.llvm.org/D61127

llvm-svn: 359668
 2019-05-01 10:40:48 +00:00
George Rimar ff3397247f [LLD] - Update the test cases after yaml2obj change. 
https://reviews.llvm.org/D60122 (r357595) changed the
symbols description format.

This change updates the LLD tests.

llvm-svn: 357596
 2019-04-03 14:54:22 +00:00
Dimitry Andric c9de3b4d26 Align AArch64 and i386 image base to superpage 
Summary:

As for x86_64, the default image base for AArch64 and i386 should be
aligned to a superpage appropriate for the architecture.

On AArch64, this is 2 MiB, on i386 it is 4 MiB.

Reviewers: emaste, grimar, javed.absar, espindola, ruiu, peter.smith, srhines, rprichard

Reviewed By: ruiu, peter.smith

Subscribers: jfb, markj, arichardson, krytarowski, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D50297

llvm-svn: 342746
 2018-09-21 16:58:13 +00:00
Peter Smith 20489ec563 [ELF] Always write non-immediate bits for AArch64 branch instruction. 
To support errata patching on AArch64 we need to be able to overwrite
an arbitrary instruction with a branch. For AArch64 it is sufficient to
always write all the bits of the branch instruction and not just the
immediate field. This is safe as the non-immediate bits of the branch
instruction are always the same.

Differential Revision: https://reviews.llvm.org/D36745

llvm-svn: 312727
 2017-09-07 16:29:52 +00:00