Commit Graph

386585 Commits

Author SHA1 Message Date
David Green 258e2e9a0b [ARM] Ensure loop invariant active.lane.mask operands
CGP can move instructions like a ptrtoint into a loop, but the
MVETailPredication when converting them will currently assume invariant
trip counts. This tries to ensure the operands are loop invariant, and
bails if not.

Differential Revision: https://reviews.llvm.org/D100550
2021-04-26 10:04:33 +01:00
Hsiangkai Wang 16dc9afa09 [RISCV] Add REQUIRES: riscv-registered-target for RISC-V test cases. 2021-04-26 17:02:27 +08:00
Djordje Todorovic 6ba150dbb4 [llvm-dwarfdump] Fix split-dwarf bug in stats for inlined var loc cov
Initial (D96045) patch didn't handle split dwarf cases,
so this fixes that bug.

In addition, before applying this patch, we had a slowdown
that happened after the D96045. With this patch,
the slowdown will be fixed as well.

Differential Revision: https://reviews.llvm.org/D100951
2021-04-26 01:56:15 -07:00
Jan Svoboda 9ab4eab570 [clang][deps] NFC: Fix typo 2021-04-26 10:55:24 +02:00
Jan Svoboda 0f7d4105c6 [clang][deps] Only generate absolute paths when asked to
Add option to `clang-scan-deps` to enable/disable generation of command-line arguments with absolute paths. This is essentially a revert of D100533, but with improved naming and added test.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D101051
2021-04-26 10:53:41 +02:00
Sven van Haastregt 18772de1ec [OpenCL] Add inc/dec/cmpxchg C++ legacy atomics with generic
Mirror the remaining C++ for OpenCL specific builtins from opencl-c.h
to the TableGen builtin functions.

Fixes PR50041 (part 2).
2021-04-26 09:46:11 +01:00
Hsiangkai Wang bd32c2d648 [RISCV] Implement the vwcvt{u}.x.x.v/vncvt.x.x.w builtin.
Differential Revision: https://reviews.llvm.org/D100824
2021-04-26 15:38:31 +08:00
Hsiangkai Wang 645c5f27a8 [RISCV] Implement the pseudo compare builtin.
Differential Revision: https://reviews.llvm.org/D100823
2021-04-26 15:38:31 +08:00
Hsiangkai Wang bfb3fca7e1 [RISCV] Implement the vfabs.v/vfneg.v builtin.
Differential Revision: https://reviews.llvm.org/D100822
2021-04-26 15:38:31 +08:00
Hsiangkai Wang 4b2434172c [RISCV] Implement the vmmv.m/vmnot.m builtin.
Differential Revision: https://reviews.llvm.org/D100821
2021-04-26 15:38:31 +08:00
Craig Topper 837442de9c [RISCV] Cleanup setOperationAction calls for INTRINSIC_WO_CHAIN/INTRINSIC_W_CHAIN
We have several extensions that need i32 to be Custom for
INTRINSIC_WO_CHAIN with RV64 so enable it for all RV64.

For V extension, make i32 Custom for RV64 and i64 Custom for RV32.
When the i32 or i64 is legal, the operation action doesn't matter.
LegalizeDAG checks MVT::Other rather than the real type.
2021-04-25 23:44:28 -07:00
Ben Shi 60ed86d350 [RISCV] Optimize addition with immediate
Reviewed by: craig.topper

Differential Revision: https://reviews.llvm.org/D101244
2021-04-26 13:26:17 +08:00
Craig Topper 8f5cd49405 [RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.
This teaches DAG combine that shift amount operands for grev, gorc
shfl, unshfl only read a few bits.

This also teaches DAG combine that grevw, gorcw, shflw, unshflw,
bcompressw, bdecompressw only consume the lower 32 bits of their
inputs.

In the future we can teach SimplifyDemandedBits to also propagate
demanded bits of the output to the inputs in some cases.
2021-04-25 21:54:06 -07:00
Levy Hsu 8cf54c7ff5 [RISCV] [1/2] Add IR intrinsic for Zbe extension
RV32/64:
bcompress
bdecompress

RV64 ONLY:
bcompressw
bdecompressw

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D101143
2021-04-25 19:14:34 -07:00
Jinsong Ji 2c9028170e [DebugInfo][AIX] Set target debugger-tune default to dbx
https://reviews.llvm.org/D99400 set clang DefaultDebuggerTuning for AIX
to dbx. However, we still need to update the target default so that llc
and other tools will get the same default debuggertuning, and avoid
passing extra options in LTO.

Reviewed By: #powerpc, shchenz, dblaikie

Differential Revision: https://reviews.llvm.org/D101197
2021-04-26 01:38:44 +00:00
Lang Hames c1baf946e6 [ORC] Avoid invalidating iterators in EHFrameRegistrationPlugin.
In EHFrameRegistrationPlugin::notifyTransferringResources if SrcKey had
eh-frames associated but DstKey did not we would create a new entry for DskKey,
invalidating the iterator for SrcKey in the process. This commit fixes that by
removing SrcKey first in this case.
2021-04-25 16:55:19 -07:00
Nathan Ridge c624e70149 [clangd] Rename HeuristicResolver::resolveCallExpr() to resolveTypeOfCallExpr()
Differential Revision: https://reviews.llvm.org/D100741
2021-04-25 19:20:14 -04:00
Nathan Ridge 6f6cf2da8d [clangd] Omit parameter hint for setter functions
Differential Revision: https://reviews.llvm.org/D100731
2021-04-25 19:20:12 -04:00
Nathan Ridge 753b247d71 [clangd] Omit parameter hint if parameter name comment is present
Differential Revision: https://reviews.llvm.org/D100715
2021-04-25 19:20:10 -04:00
Vitaly Buka 337a024bba [scudo][NFC] Fix cast warning 2021-04-25 15:47:28 -07:00
Vitaly Buka 98a7563261 [scudo] Mark ARM64 as supported platform 2021-04-25 15:47:28 -07:00
Vitaly Buka 51b4a7ef52 [sanitizer] Use COMPILER_RT_EMULATOR with gtests
Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D100998
2021-04-25 15:41:13 -07:00
Roman Lebedev 7b312e228c
[NFC][X86][AVX2] Add baseline CodeGen/CostModel tests for interleaved loads/stores of i16 w/ strides 2/3/4
`X86TTIImpl::getInterleavedMemoryOpCostAVX2()` currently contains data
only for a handful of tuples. For now, at least add tests for a few more.

I'm guessing that we care how well the patterns codegen since
we use their presumed cost for vectorization decisions,
so i've added codegen tests too.

There's one really easy caveat for these codegen tests:
for interleaved load tests, we really have to ensure that the
deinterleaved vectors are escaped separately. Similarly for stores.
2021-04-26 01:13:07 +03:00
Nathan Ridge d941863de2 [clangd] Use HeuristicResolver to produce a better semantic token for name referring to UnresolvedUsingValueDecl
Fixes https://github.com/clangd/clangd/issues/686

Differential Revision: https://reviews.llvm.org/D99056
2021-04-25 16:45:04 -04:00
Nathan Ridge ddfe13e757 [clangd] Produce semantic token for name referring to UnresolvedUsingValueDecl
For now, use the token kind Unknown. We may be able to improve on this
using HeuristicResolver.

Differential Revision: https://reviews.llvm.org/D99052
2021-04-25 16:43:58 -04:00
Martin Storsjö b493193d74 [googlemock] Fix warnings about superfluous semicolons after 68ff493dfc. NFC. 2021-04-25 23:41:37 +03:00
Nemanja Ivanovic 504eee28fe Disable deprecated-copy warnings on various LLVM code to bring the bot back to green
Bootstrap with `-Werror` is currently broken due to D79714.
This patch is required to bring the bootstrap bot back to green. The
code will likely need to be fixed and the pragmas removed in due time,
but for now we need to bring the bot back up.

Bot that is currently failing:
https://lab.llvm.org/buildbot/#/builders/36/builds/7680

Differential Revision: https://reviews.llvm.org/D101214
2021-04-25 12:41:46 -07:00
Vitaly Buka 68ff493dfc [NFC] Fixed some D79714 warnings 2021-04-25 12:41:46 -07:00
Min-Yih Hsu fc86e6d188 [ARM][disassembler] Fix incorrect number of MCOperands generated by the disassembler
Try to fix bug 49974.

This patch fixes two issues:

 1. BL does not use predicate (BL_pred is the predicate version of BL),
    so we shouldn't add predicate operands in DecodeBranchImmInstruction.
 2. Inside DecodeT2AddSubSPImm, we shouldn't add predicate operands into
    the MCInst because ARMDisassembler::AddThumbPredicate will do that for us.
    However, we should handle CC-out operand for t2SUBspImm and t2AddspImm.

Differential Revision: https://reviews.llvm.org/D100585
2021-04-25 11:55:10 -07:00
Michał Górny 06215023f4 [lldb] [Process/NetBSD] Report fork/vfork events to LLGS
Differential Revision: https://reviews.llvm.org/D100554
2021-04-25 19:40:59 +02:00
Michał Górny 65f2a75737 [lldb] [Process/FreeBSD] Report fork/vfork events to LLGS
Differential Revision: https://reviews.llvm.org/D100547
2021-04-25 19:40:46 +02:00
Florian Hahn 4b9be5ac08
[VPlan] Add VPBlockUtils::blocksOnly helper.
This patch adds a blocksOnly helpers which take an iterator range
over VPBlockBase * or const VPBlockBase * and returns an interator
range that only include BlockTy blocks. The accesses are casted to
BlockTy.

Reviewed By: a.elovikov

Differential Revision: https://reviews.llvm.org/D101093
2021-04-25 17:38:09 +01:00
LLVM GN Syncbot 92880ab7a2 [gn build] Port 1cea7ab4ba 2021-04-25 12:00:31 +00:00
Tomasz Miąsko 1cea7ab4ba [demangler] Use standard semantics for StringView::substr
The StringView::substr now accepts a substring starting position and its
length instead of previous non-standard `from` & `to` positions.

All uses of two argument StringView::substr are in MicrosoftDemangler
and have 0 as a starting position, so no changes are necessary.

This also fixes a bug where attempting to extract a suffix with substr
(a `to` position equal to size) would return a substring without the
last character.

Fixing the issue should not introduce observable changes in the
demangler, since as currently used, a second argument to
StringView::substr is either: 1) a result of a successful call to
StringView::find and so necessarily smaller than size., or 2) in the
case of Demangler::demangleCharLiteral potentially equal to size, but
with demangler expecting more data to follow later on and failing either
way.

Reviewed By: #libc_abi, ldionne, erik.pilkington

Differential Revision: https://reviews.llvm.org/D100246
2021-04-25 13:56:41 +02:00
Simon Pilgrim 535df472b0 Revert rG2149aa73f640c96 "[X86] Add support for reusing ZF etc. from locked XADD instructions (PR20841)"
This might be the cause of some msan build failures - I don't have access to a msan build right now, so this is a speculative revert.
2021-04-25 12:45:07 +01:00
LLVM GN Syncbot c5cb5053a9 [gn build] Port a354fd56c5 2021-04-25 11:27:54 +00:00
Mark de Wever a354fd56c5 [libc++] Adds __utility/to_underlying.h.
During the review of D97115 it was mentioned adding the `<utility>`
header for `__to_underlying` was a bit unfortunate. Nowadays we tend to
implement smaller headers, so a good reason to move `std::to_underlying`
to its own header and adjust `<charconv>` to use the new header.

Differential Revision: https://reviews.llvm.org/D101233
2021-04-25 13:27:19 +02:00
Stephen Kelly 8d018c79ee Add srcloc output to clang-query
Differential Revision: https://reviews.llvm.org/D93325
2021-04-25 12:12:04 +01:00
Stephen Kelly a9676febb9 [AST] Add DeclarationNameInfo to node introspection
Differential Revision: https://reviews.llvm.org/D101049
2021-04-25 12:12:03 +01:00
Simon Pilgrim 2149aa73f6 [X86] Add support for reusing ZF etc. from locked XADD instructions (PR20841)
XADD has the same EFLAGS behaviour as ADD
2021-04-25 12:02:33 +01:00
Simon Pilgrim 5dd5859c42 [X86] Add PR20841 test cases showing failure to reuse ZF from XADD ops 2021-04-25 11:50:18 +01:00
Simon Pilgrim 72471c656e [X86] Regenerate atomic-flags.ll test file 2021-04-25 11:50:18 +01:00
Florian Hahn fa2f162e76
[NewGVN] Properly transfer PredDep in move constructor. 2021-04-25 11:22:59 +01:00
Florian Hahn 1d8ef761be
[NewGVN] Use ExprResult to add extra predicate users.
This patch updates performSymbolicPredicateInfoEvaluation to manage
registering additional dependencies using ExprResult. Similar to D99987,
this fixes an issues where we failed to track the correct dependency for
a phi-of-ops value, which is marked as temporary.

Fixes PR49873.

Reviewed By: asbirlea, ruiling

Differential Revision: https://reviews.llvm.org/D100560
2021-04-25 11:13:32 +01:00
Hsiangkai Wang d8fa5ef6a2 [RISCV] Apply clang_builtin_alias to overloaded builtins.
We only apply `clang_builtin_alias` to non-masked builtins.
Masked builtins could not use `clang_builtin_alias` because the
operand order is different between overloaded intrinsics and builtins.

A bunch of test cases need to be updated.

Differential Revision: https://reviews.llvm.org/D100658
2021-04-25 18:12:19 +08:00
Simon Pilgrim f68cd33567 [PhaseOrdering] Add PR32544 test coverage 2021-04-25 11:05:32 +01:00
Xiang1 Zhang c3f95e9197 [X86] Refine AMX fast register allocation 2021-04-25 14:20:53 +08:00
Xiang1 Zhang 3b8ec86fd5 [X86] Support AMX fast register allocation
Differential Revision: https://reviews.llvm.org/D100026
2021-04-25 09:45:41 +08:00
Hsiangkai Wang e6131f7ee5 [Clang] Fixup for D100611 2021-04-25 09:41:19 +08:00
Lang Hames c572ff840f [ORC][C-bindings] Fix missing ')' in comments. 2021-04-24 18:04:57 -07:00