maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
149,422 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

6682 Commits

Author SHA1 Message Date
Mihai Popa dc1764c5a4 The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. 
llvm-svn: 181705
 2013-05-13 14:10:04 +00:00
Lang Hames 67c09b3f88 Correctly preserve the input chain for potential tailcall nodes whose 
return values are bitcasts.

The chain had previously been being clobbered with the entry node to
the dag, which sometimes caused other code in the function to be
erroneously deleted when tailcall optimization kicked in.

<rdar://problem/13827621>

llvm-svn: 181696
 2013-05-13 10:21:19 +00:00
Rafael Espindola 227144c23c Remove the MachineMove class. 
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.

I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.

llvm-svn: 181680
 2013-05-13 01:16:13 +00:00
Rafael Espindola 140a837acd Remove unused argument. 
llvm-svn: 181618
 2013-05-10 18:16:59 +00:00
Logan Chien 4ea23b56c5 Implement AsmParser for ARM unwind directives. 
This commit implements the AsmParser for fnstart, fnend,
cantunwind, personality, handlerdata, pad, setfp, save, and
vsave directives.

This commit fixes some minor issue in the ARMELFStreamer:

* The switch back to corresponding section after the .fnend
  directive.

* Emit the unwind opcode while processing .fnend directive
  if there is no .handlerdata directive.

* Emit the unwind opcode to .ARM.extab while processing
  .handlerdata even if .personality directive does not exist.

llvm-svn: 181603
 2013-05-10 16:17:24 +00:00
Stepan Dyatkovskiy 2703bcaad3 For r181148: fixed warning 'enumeral and non-enumeral type in conditional expression'. 
llvm-svn: 181437
 2013-05-08 14:51:27 +00:00
Evan Cheng 9fad6352d4 ARM AnalyzeBranch should conservatively return true when it sees a predicated 
indirect branch at the end of the BB. Otherwise if-converter, branch folding
pass may incorrectly update its successor info if it consider BB as fallthrough
to the next BB.

rdar://13782395

llvm-svn: 181161
 2013-05-05 18:06:32 +00:00
Stepan Dyatkovskiy 8c02c98259 For ARM backend, fixed "byval" attribute support. 
Now even the small structures could be passed within byval (small enough
to be stored in GPRs).
In regression tests next function prototypes are checked:

PR15293:
  %artz = type { i32 }
  define void @foo(%artz* byval %s)
  define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2)
foo: "s" stored in R0
foo2: "s" stored in R0, "s2" stored in R2.

Next AAPCS rules are checked:
5.5 Parameters Passing, C.4 and C.5,
"ParamSize" is parameter size in 32bit words:
-- NSAA != 0, NCRN < R4 and NCRN+ParamSize > R4.
   Parameter should be sent to the stack; NCRN := R4.
-- NSAA != 0, and NCRN < R4, NCRN+ParamSize < R4.
   Parameter stored in GPRs; NCRN += ParamSize.

llvm-svn: 181148
 2013-05-05 07:48:36 +00:00
Dmitri Gribenko 3238fb7595 Add ArrayRef constructor from None, and do the cleanups that this constructor enables 
Patch by Robert Wilhelm.

llvm-svn: 181138
 2013-05-05 00:40:33 +00:00
Amara Emerson d9104c0359 Revert r181009. 
llvm-svn: 181079
 2013-05-03 23:57:17 +00:00
Amara Emerson 2f54d9fe10 Add support for reading ARM ELF build attributes. 
Build attribute sections can now be read if they exist via ELFObjectFile, and
the llvm-readobj tool has been extended with an option to dump this information
if requested. Regression tests are also included which exercise these features.

Also update the docs with a fixed ARM ABI link and a new link to the Addenda
which provides the build attributes specification.

llvm-svn: 181009
 2013-05-03 11:36:35 +00:00
Rafael Espindola 789a1c8a23 Text files should not be marked executable. 
Patch by Oliver Pinter.

llvm-svn: 180797
 2013-04-30 19:06:15 +00:00
Mihai Popa af22d91af0 s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL. 
llvm-svn: 180778
 2013-04-30 09:00:12 +00:00
Stepan Dyatkovskiy f5aa83dbb0 Refactoring patch. 
1. VarArgStyleRegisters: functionality that emits "store" instructions for byval regs moved out into separated method "StoreByValRegs". Before this patch VarArgStyleRegisters had confused use-cases. It was used for both variadic functions and for regular functions with byval parameters. In last case it created new stack-frame and registered it as VarArg frame, that is wrong.

This patch replaces VarArgsStyleRegisters usage for byval parameters with StoreByValRegs method.

2. In ARMMachineFunctionInfo, "get/setVarArgsRegSaveSize" was renamed to "get/setArgRegsSaveSize". By the same reason. Sometimes it was used for variadic functions, and sometimes for byval parameters in regular functions. Actually, this property means the size of registers, that keeps arguments, and thats why it was renamed.

3. In ARMISelLowering.cpp, ARMTargetLowering class, in methods computeRegArea and StoreByValRegs, VARegXXXXXX was renamed to ArgRegsXXXXXX still by the same reasons.

llvm-svn: 180774
 2013-04-30 07:19:58 +00:00
Quentin Colombet a83d5e9f91 ARM: Fix encoding of hint instruction for Thumb. 
"hint" space for Thumb actually overlaps the encoding space of the CPS
instruction. In actuality, hints can be defined as CPS instructions where imod
and M bits are all nil.

Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe,
sev) in DecodeT2CPSInstruction.

This commit adds a proper diagnostic message for Imm0_4 and updates all tests.

Patch by Mihail Popa <Mihail.Popa@arm.com>.

llvm-svn: 180617
 2013-04-26 17:54:54 +00:00
Benjamin Kramer ae81474a38 ARM/NEON: Pattern match vector integer abs to vabs. 
llvm-svn: 180604
 2013-04-26 15:00:57 +00:00
Arnold Schwaighofer 9881dcf2f2 ARM cost model: Integer div and rem is lowered to a function call 
Reflect this in the cost model. I observed this in MiBench/consumer-lame.

radar://13354716

llvm-svn: 180576
 2013-04-25 21:16:18 +00:00
Stephen Lin 8118e0b588 Add more tests for r179925 to verify correct handling of signext/zeroext; strengthen condition check to require actual MVT::i32 virtual register types, just in case (no actual functionality change) 
llvm-svn: 180138
 2013-04-23 19:42:25 +00:00
Stephen Lin 4eedb29b05 Lowercase "is" boolean variable prefix for consistency within function, no functionality change. 
llvm-svn: 180136
 2013-04-23 19:30:12 +00:00
Eric Christopher cc2cfe426d No really, don't store anything to this since it's unconditionally 
set below.

llvm-svn: 180015
 2013-04-22 14:11:25 +00:00
Eric Christopher 6647fb2c60 Remove variable store that is never read. 
llvm-svn: 180014
 2013-04-22 13:51:44 +00:00
Stepan Dyatkovskiy f80f9513ce Fix for 5.5 Parameter Passing --> Stage C: 
-- C.4 and C.5 statements, when NSAA is not equal to SP.
 -- C.1.cp statement for VA functions. Note: There are no VFP CPRCs in a
    variadic procedure.

Before this patch "NSAA != 0" means "don't use GPRs anymore ". But there are
some exceptions in AAPCS.
1. For non VA function: allocate all VFP regs for CPRC. When all VFPs are allocated
   CPRCs would be sent to stack, while non CPRCs may be still allocated in GRPs.
2. Check that for VA functions all params uses GPRs and then stack.
   No exceptions, no CPRCs here.

llvm-svn: 180011
 2013-04-22 13:06:52 +00:00
Jim Grosbach 563983c8a3 Legalize vector truncates by parts rather than just splitting. 
Rather than just splitting the input type and hoping for the best, apply
a bit more cleverness. Just splitting the types until the source is
legal often leads to an illegal result time, which is then widened and a
scalarization step is introduced which leads to truly horrible code
generation. With the loop vectorizer, these sorts of operations are much
more common, and so it's worth extra effort to do them well.

Add a legalization hook for the operands of a TRUNCATE node, which will
be encountered after the result type has been legalized, but if the
operand type is still illegal. If simple splitting of both types
ends up with the result type of each half still being legal, just
do that (v16i16 -> v16i8 on ARM, for example). If, however, that would
result in an illegal result type (v8i32 -> v8i8 on ARM, for example),
we can get more clever with power-two vectors. Specifically,
split the input type, but also widen the result element size, then
concatenate the halves and truncate again.  For example on ARM,
To perform a "%res = v8i8 trunc v8i32 %in" we transform to:
  %inlo = v4i32 extract_subvector %in, 0
  %inhi = v4i32 extract_subvector %in, 4
  %lo16 = v4i16 trunc v4i32 %inlo
  %hi16 = v4i16 trunc v4i32 %inhi
  %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
  %res = v8i8 trunc v8i16 %in16

This allows instruction selection to generate three VMOVN instructions
instead of a sequences of moves, stores and loads.

Update the ARMTargetTransformInfo to take this improved legalization
into account.

Consider the simplified IR:

define <16 x i8> @test1(<16 x i32>* %ap) {
  %a = load <16 x i32>* %ap
  %tmp = trunc <16 x i32> %a to <16 x i8>
  ret <16 x i8> %tmp
}

define <8 x i8> @test2(<8 x i32>* %ap) {
  %a = load <8 x i32>* %ap
  %tmp = trunc <8 x i32> %a to <8 x i8>
  ret <8 x i8> %tmp
}

Previously, we would generate the truly hideous:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #20
	bic	sp, sp, #7
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d24, d25}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	vld1.64	{d18, d19}, [r2:128]
	add	r1, r0, #16
	vmovn.i32	d22, q8
	vld1.64	{d16, d17}, [r1:128]
	vmovn.i32	d20, q9
	vmovn.i32	d18, q12
	vmov.u16	r0, d22[3]
	strb	r0, [sp, #15]
	vmov.u16	r0, d22[2]
	strb	r0, [sp, #14]
	vmov.u16	r0, d22[1]
	strb	r0, [sp, #13]
	vmov.u16	r0, d22[0]
	vmovn.i32	d16, q8
	strb	r0, [sp, #12]
	vmov.u16	r0, d20[3]
	strb	r0, [sp, #11]
	vmov.u16	r0, d20[2]
	strb	r0, [sp, #10]
	vmov.u16	r0, d20[1]
	strb	r0, [sp, #9]
	vmov.u16	r0, d20[0]
	strb	r0, [sp, #8]
	vmov.u16	r0, d18[3]
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	vldmia	sp, {d16, d17}
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	mov	sp, r7
	pop	{r7}
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #12
	bic	sp, sp, #7
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d20, d21}, [r0:128]
	vmovn.i32	d18, q8
	vmov.u16	r0, d18[3]
	vmovn.i32	d16, q10
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	ldm	sp, {r0, r1}
	mov	sp, r7
	pop	{r7}
	bx	lr

Now, however, we generate the much more straightforward:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d20, d21}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	add	r1, r0, #16
	vld1.64	{d18, d19}, [r2:128]
	vld1.64	{d22, d23}, [r1:128]
	vmovn.i32	d17, q8
	vmovn.i32	d16, q9
	vmovn.i32	d18, q10
	vmovn.i32	d19, q11
	vmovn.i16	d17, q8
	vmovn.i16	d16, q9
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d18, d19}, [r0:128]
	vmovn.i32	d16, q8
	vmovn.i32	d17, q9
	vmovn.i16	d16, q8
	vmov	r0, r1, d16
	bx	lr

llvm-svn: 179989
 2013-04-21 23:47:41 +00:00
Tim Northover 798697d662 ARM: Use ldrd/strd to spill 64-bit pairs when available. 
This allows common sp-offsets to be part of the instruction and is
probably faster on modern CPUs too.

llvm-svn: 179977
 2013-04-21 11:57:07 +00:00
Tim Northover d9d4211fe2 ARM: don't add FrameIndex offset for LDMIA (has no immediate) 
Previously, when spilling 64-bit paired registers, an LDMIA with both
a FrameIndex and an offset was produced. This kind of instruction
shouldn't exist, and the extra operand was being confused with the
predicate, causing aborts later on.

This removes the invalid 0-offset from the instruction being
produced.

llvm-svn: 179956
 2013-04-20 19:31:00 +00:00
Tim Northover 16aba17024 Remove unused ShouldFoldAtomicFences flag. 
I think it's almost impossible to fold atomic fences profitably under
LLVM/C++11 semantics. As a result, this is now unused and just
cluttering up the target interface.

llvm-svn: 179940
 2013-04-20 12:32:43 +00:00
Tim Northover a2b533906a Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE. 
llvm-svn: 179939
 2013-04-20 12:32:17 +00:00
Stephen Lin b8bd232a3d Add CodeGen support for functions that always return arguments via a new parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter). 
llvm-svn: 179925
 2013-04-20 05:14:40 +00:00
Stephen Lin d36fd2cfe2 Test commit 
llvm-svn: 179913
 2013-04-20 00:47:48 +00:00
Eli Bendersky 90dd3e7dfd Move TryToFoldFastISelLoad to FastISel, where it belongs. In general, I'm 
trying to move as much FastISel logic as possible out of the main path in
SelectionDAGISel - intermixing them just adds confusion.

llvm-svn: 179902
 2013-04-19 22:29:18 +00:00
Michael Liao b53d8963ce ArrayRefize getMachineNode(). No functionality change. 
llvm-svn: 179901
 2013-04-19 22:22:57 +00:00
Tim Northover 27ff504653 ARM: Permit "sp" in ARM variant of STREXD instructions 
Patch from Mihail Popa

llvm-svn: 179854
 2013-04-19 15:44:32 +00:00
Tim Northover a155ab2dd2 ARM: permit "sp" in ARM variants of MOVW/MOVT instructions 
llvm-svn: 179847
 2013-04-19 09:58:09 +00:00
Chad Rosier 9f7a221fdc [asm parser] Add support for predicating MnemonicAlias based on the assembler 
variant/dialect.  Addresses a FIXME in the emitMnemonicAliases function.
Use and test case to come shortly.
rdar://13688439 and part of PR13340.

llvm-svn: 179804
 2013-04-18 22:35:36 +00:00
Hao Liu a2ff69863e Fix for PR14824, An ARM Load/Store Optimization bug 
llvm-svn: 179751
 2013-04-18 09:11:08 +00:00
Peter Collingbourne 2f495b93ee Add support for subsections to the ELF assembler. Fixes PR8717. 
Differential Revision: http://llvm-reviews.chandlerc.com/D598

llvm-svn: 179725
 2013-04-17 21:18:16 +00:00
Quentin Colombet 6f03f624df Fix treatment of ARM unallocated hint instructions. 
The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction:
1. nop (imm == 0)
2. yield (imm == 1)
3. wfe (imm == 2)
4. wfi (imm == 3)
5. sev (imm == 4)

Therefore, restrict the permitted values for the "hint" instruction to 0 through 4.

Patch by Mihail Popa <Mihail.Popa@arm.com>

llvm-svn: 179707
 2013-04-17 18:46:12 +00:00
Logan Chien 3d134ebb73 Fix build failure introduced in 179591 when assertions are disabled. 
llvm-svn: 179593
 2013-04-16 14:02:30 +00:00
Logan Chien d8bb4b7e06 Implement ARM unwind opcode assembler. 
llvm-svn: 179591
 2013-04-16 12:02:21 +00:00
Jim Grosbach 9b81a4f0f1 ARM: Add VACLT and VACLE assembly aliases. 
These are aliases for VACGT and VACGE, respectively, with the source
operands reversed.

rdar://13638090

llvm-svn: 179575
 2013-04-15 22:42:50 +00:00
Quentin Colombet c313220b18 ARM: Correct printing of pre-indexed operands. 
According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes.
The MC disassembler was not obeying this when the offset is 0.
It was producing instructions like: str r0, [r1]!.
Correct syntax is: str r0, [r1, #0]!.

This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used.

Patch by Mihail Popa <Mihail.Popa@arm.com>

llvm-svn: 179398
 2013-04-12 18:47:25 +00:00
Tim Northover c6047655a7 ARM: Make "SMC" instructions conditional on new TrustZone architecture feature. 
These instructions aren't universally available, but depend on a specific
extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new
feature is appropriate.

This also enables the feature by default on A-class cores which usually have
these extensions, to avoid breaking existing code and act as a sensible
default.

llvm-svn: 179171
 2013-04-10 12:08:35 +00:00
Benjamin Kramer d56a324e30 ARM: Remove unused variable. 
llvm-svn: 179001
 2013-04-08 08:07:35 +00:00
Renato Golin 91de828f46 Reverting 178851 as it broke buildbots 
llvm-svn: 178883
 2013-04-05 16:39:53 +00:00
Stepan Dyatkovskiy 6b53a2f50a Buildbot fix for r178851: mistake was in wrong TargetRegisterInfo::getRegClass usage. 
llvm-svn: 178854
 2013-04-05 07:34:08 +00:00
Stepan Dyatkovskiy b309b3b33e Fix for PR14824: "Optimization arm_ldst_opt inserts newly generated instruction vldmia at incorrect position". 
Patch introduces memory operands tracking in ARMLoadStoreOpt::LoadStoreMultipleOpti. For each register it keeps the order of load operations as it was before optimization pass.
It is kind of deep improvement of fix proposed by Hao: http://llvm.org/bugs/show_bug.cgi?id=14824#c4
But it also tracks conflicts between different register classes (e.g. D2 and S5).
For more details see:
Bug description: http://llvm.org/bugs/show_bug.cgi?id=14824
LLVM Commits discussion: 
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130311/167936.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130318/168688.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130325/169376.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130401/170238.html

llvm-svn: 178851
 2013-04-05 05:52:14 +00:00
Arnold Schwaighofer fb6b9f48d0 ARM scheduler model: Add scheduler info to more instructions and resource 
descriptions for compares

llvm-svn: 178844
 2013-04-05 05:01:06 +00:00
Arnold Schwaighofer 5dde1f39c1 ARM scheduler model: Swift has varying latencies, uops for simple ALU ops 
llvm-svn: 178842
 2013-04-05 04:42:00 +00:00
Jakob Stoklund Olesen 299475e0c6 Avoid high-latency false CPSR dependencies even for tMOVSi. 
The Thumb2SizeReduction pass avoids false CPSR dependencies, except it
still aggressively creates tMOVi8 instructions because they are so
common.

Avoid creating false CPSR dependencies even for tMOVi8 instructions when
the the CPSR flags are known to have high latency. This allows integer
computation to overlap floating point computations.

Also process blocks in a reverse post-order and propagate high-latency
flags to successors.

<rdar://problem/13468102>

llvm-svn: 178773
 2013-04-04 18:25:36 +00:00
Arnold Schwaighofer 6793aebb84 ARM Scheduler Model: Add resources instructions, map resources in subtargets 
Reapply r177968:
After commit 178074 we can now have undefined scheduler variants.

Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.

Incooperate Andrew's feedback.

llvm-svn: 178460
 2013-04-01 13:07:05 +00:00