Commit Graph

277206 Commits

Author SHA1 Message Date
Peter Collingbourne 24ca79c776 COFF: Simplify construction of safe SEH table. NFCI.
Instead of building intermediate sets of exception handlers for each
object file, just create one for the final output file.

Differential Revision: https://reviews.llvm.org/D40581

llvm-svn: 319244
2017-11-28 22:50:53 +00:00
Simon Pilgrim 1bc7b0e148 [X86][SSE] Use SSE_PACK OpndItins in PACKSS/PACKUS instruction definitions
Update multi-classes to take the scheduling OpndItins instead of hard coding it.

SSE_PACK will be reused in the AVX512 equivalents.

llvm-svn: 319243
2017-11-28 22:47:45 +00:00
Adam Nemet 80fb55625b Remove this test
After r319235, we no longer generate this remark.

llvm-svn: 319242
2017-11-28 22:39:38 +00:00
Dean Michael Berris 28832d2b36 [XRay][compiler-rt] Fix runtime build
This isolates the per-architecture files from the common files
implementing the XRay facilities. Because of the refactoring done in
D39114, we were including the definition of the sources in the archive
twice, causing link-time failures.

Follow-up to D39114.

llvm-svn: 319241
2017-11-28 22:33:07 +00:00
Simon Pilgrim 14d3fd29f8 Fix VS2017 narrowing conversion warning. NFCI
llvm-svn: 319240
2017-11-28 22:32:43 +00:00
Craig Topper ab9bfc904b [X86] Remove unused variable.
llvm-svn: 319239
2017-11-28 22:28:23 +00:00
Rui Ueyama ceb15e8a51 Fix spelling. NFC.
llvm-svn: 319238
2017-11-28 22:17:39 +00:00
Alex Shlyapnikov 15b71ea646 [LSan] Fix one source of stale segments in the process memory mapping.
Summary:
Load process memory map after updating the same cache to reflect the
umap happening in the process of updating.
Also clear out the buffer in case of failed read of /proc/self/maps (not
the source of stale segments, but can lead to the similar crash).

Reviewers: eugenis

Subscribers: llvm-commits, kubamracek

Differential Revision: https://reviews.llvm.org/D40529

llvm-svn: 319237
2017-11-28 22:15:27 +00:00
Rui Ueyama 2445b0ccac Remove unused `using`.
llvm-svn: 319236
2017-11-28 22:14:13 +00:00
Adam Nemet 2e92289014 Demote this opt remark to DEBUG.
From a random opt-stat output:

Top 10 remarks:
  tailcallelim/tailcall          53%
  inline/AlwaysInline            13%
  gvn/LoadClobbered              13%
  inline/Inlined                  8%
  inline/TooCostly                2%
  inline/NoDefinition             2%
  licm/LoadWithLoopInvariantAddressInvalidated  2%
  licm/Hoisted                    1%
  asm-printer/InstructionCount    1%
  prologepilog/StackSize          1%

llvm-svn: 319235
2017-11-28 22:11:00 +00:00
Craig Topper a27f1e675a [X86] Remove code from combineUIntToFP that tried to favor UINT_TO_FP if legal when zero extending from vXi8/vX816.
The UINT_TO_FP is immediately converted to SINT_TO_FP when the node is re-evaluated because we'll detect that the sign bit is zero.

llvm-svn: 319234
2017-11-28 22:08:51 +00:00
Craig Topper 3aaa71f222 [X86] Remove custom lowering for uint_to_fp from vXi8/vXi16.
We have a DAG combine that uses a zero extend that should prevent this from ever occurring now.

llvm-svn: 319233
2017-11-28 22:08:48 +00:00
Daniel Sanders 766646517f [globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, G_ATOMICRMW_* rules from SelectionDAG.
GIM_CheckNonAtomic has been replaced by GIM_CheckAtomicOrdering to allow it to support a wider
range of orderings. This has then been used to import patterns using nodes such
as atomic_cmp_swap, atomic_swap, and atomic_load_*.

llvm-svn: 319232
2017-11-28 22:07:05 +00:00
Adrian Prantl 77d90b0c39 SROA: Don't create variable fragments that are outside of the variable.
An alloca may be larger than a variable that is described to be stored
there. Don't create a dbg.value for fragments that are outside of the
variable.

This fixes PR35447.
https://bugs.llvm.org/show_bug.cgi?id=35447

llvm-svn: 319230
2017-11-28 21:30:38 +00:00
Peter Collingbourne bcf7f290ff COFF: Do not add symbols in discarded sections to SEH handler list.
Differential Revision: https://reviews.llvm.org/D40576

llvm-svn: 319229
2017-11-28 21:30:05 +00:00
Don Hinton f5aab5454e [cmake] Pass LLVM_USE_LINKER flag when building host tools, e.g.,
LLVM_OPTIMIZED_TABLEGEN=ON, and not crosscompiling.

Differential Revision: https://reviews.llvm.org/D39734

llvm-svn: 319228
2017-11-28 21:23:30 +00:00
Alexey Bataev 2ba67045e3 [OPENMP] Generalize capturing of clauses expressions.
The handling and capturing of the non-constant expressions of some of
the capturable clauses in combined directives is generalized.

llvm-svn: 319227
2017-11-28 21:11:44 +00:00
Jim Ingham 4e0b043009 Add elf-core/RegisterUtilities.{cpp,h} to the project file.
llvm-svn: 319226
2017-11-28 21:11:15 +00:00
Aaron Ballman d3d78b903a Add a new clang-tidy module for Fuchsia as an umbrella to diagnose issues with the Fuschia and Zircon coding guidelines (https://fuchsia.googlesource.com/zircon/+/master/docs/cxx.md). Adds the first of such checkers, which detects when default arguments are declared in a function declaration or when default arguments are used at call sites.
Patch by Julie Hockett

llvm-svn: 319225
2017-11-28 21:09:25 +00:00
Alexey Bataev ab5f3f2b33 [SLP] Additional test for PR35354, NFC.
llvm-svn: 319224
2017-11-28 20:48:24 +00:00
Mandeep Singh Grang e0173664e9 [Hexagon] Use stable sort for HexagonShuffler to remove non-deterministic ordering
Summary:
This fixes failures in the following tests uncovered by D39245:
        LLVM :: CodeGen/Hexagon/args.ll
        LLVM :: CodeGen/Hexagon/constp-extract.ll
        LLVM :: CodeGen/Hexagon/expand-condsets-basic.ll
        LLVM :: CodeGen/Hexagon/gp-rel.ll
        LLVM :: CodeGen/Hexagon/packetize_cond_inst.ll
        LLVM :: CodeGen/Hexagon/simple_addend.ll
        LLVM :: CodeGen/Hexagon/swp-stages4.ll
        LLVM :: CodeGen/Hexagon/swp-vmult.ll
        LLVM :: CodeGen/Hexagon/swp-vsum.ll
        LLVM :: MC/Hexagon/align.s
        LLVM :: MC/Hexagon/asmMap.s
        LLVM :: MC/Hexagon/dis-duplex-p0.s
        LLVM :: MC/Hexagon/double-vector-producer.s
        LLVM :: MC/Hexagon/inst_select.ll
        LLVM :: MC/Hexagon/instructions/j.s

Reviewers: colinl, kparzysz, adasgupt, slarin

Reviewed By: kparzysz

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D40227

llvm-svn: 319223
2017-11-28 20:48:10 +00:00
Mandeep Singh Grang b14fb6a216 [OpenMP] Stable sort Privates to remove non-deterministic ordering
Summary:
This fixes the following failures uncovered by D39245:
    Clang :: OpenMP/task_firstprivate_codegen.cpp
    Clang :: OpenMP/task_private_codegen.cpp
    Clang :: OpenMP/taskloop_firstprivate_codegen.cpp
    Clang :: OpenMP/taskloop_lastprivate_codegen.cpp
    Clang :: OpenMP/taskloop_private_codegen.cpp
    Clang :: OpenMP/taskloop_simd_firstprivate_codegen.cpp
    Clang :: OpenMP/taskloop_simd_lastprivate_codegen.cpp
    Clang :: OpenMP/taskloop_simd_private_codegen.cpp

Reviewers: rjmccall, ABataev, AndreyChurbanov

Reviewed By: rjmccall, ABataev

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D39947

llvm-svn: 319222
2017-11-28 20:41:13 +00:00
Rui Ueyama 2017d52b54 Move Memory.{h,cpp} to Common.
Differential Revision: https://reviews.llvm.org/D40571

llvm-svn: 319221
2017-11-28 20:39:17 +00:00
Daniel Sanders 7b361b50d8 [aarch64][globalisel] Add missing tests from r319216
llvm-svn: 319220
2017-11-28 20:27:59 +00:00
Sam Clegg f95826dccd [WebAssembly] Remove initializers from Config.h
These should get initialized in by Driver.cpp based on
command line options.

Also, sort entries.

Differential Revision: https://reviews.llvm.org/D40570

llvm-svn: 319219
2017-11-28 20:27:21 +00:00
Sean Fertile e200016ea9 [PowerPC] Allow tail calls of fastcc functions from C CallingConv functions.
Allow fastcc callees to be tail-called from ccc callers.

Differential Revision: https://reviews.llvm.org/D40355

llvm-svn: 319218
2017-11-28 20:25:58 +00:00
Rafael Espindola f70502d3a6 Bring r319051 back.
It had been reverted because it depended on r319008 which has been
recommitted.

Original message:

Add a missing test.

We were not testing that we correctly handled a .o with a weak symbol
after a .so.

llvm-svn: 319217
2017-11-28 20:21:44 +00:00
Daniel Sanders 7fe7acc6b1 [aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal
The IRTranslator cannot generate these instructions at the moment so there's no
issue with not having implemented ISel for them yet. D40092 will add
G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_* to the IRTranslator and a
further patch will add support for lowering G_ATOMIC_CMPXCHG_WITH_SUCCESS into
G_ATOMIC_CMPXCHG with an external success check via the `Lower` action.

The separation of G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMIC_CMPXCHG is
to import SelectionDAG rules while still supporting targets that prefer to
custom lower the original LLVM-IR-like operation.

llvm-svn: 319216
2017-11-28 20:21:15 +00:00
Rafael Espindola 1d4b3023dc Bring back r319008.
This includes a fix to mark copy reloc aliases as used.

Original message:

[ELF] Do not keep symbols if they referenced only from discarded sections.

This patch also ensures that in case of "--as-needed" is used,
DT_NEEDED entries are not created if they are required only by
these eliminated symbols.

llvm-svn: 319215
2017-11-28 20:17:58 +00:00
Rafael Espindola 57ef60f0f9 Add missing test.
This would have found the issue with r319008.

llvm-svn: 319214
2017-11-28 20:13:12 +00:00
Greg Clayton 7547aca722 Update remote debugging page with many more details.
llvm-svn: 319213
2017-11-28 20:04:43 +00:00
Rui Ueyama 28c65bc20b Fix formatting.
llvm-svn: 319212
2017-11-28 20:01:30 +00:00
Rui Ueyama 3e03944f02 Factor out more code to Common/Args.cpp.
Differential Revision: https://reviews.llvm.org/D40540

llvm-svn: 319211
2017-11-28 19:58:45 +00:00
Mandeep Singh Grang 230b0a1477 [SelectionDAG] Make sorting predicate stronger to remove non-deterministic ordering
Summary:
Recommitting this with the correct sorting predicate. The Low field of Clusters is a ConstantInt and
cannot be directly compared. So we needed to invoke slt (signed less than) to compare correctly.

This fixes failures in the following tests uncovered by D39245:

LLVM :: CodeGen/ARM/ifcvt3.ll
LLVM :: CodeGen/ARM/switch-minsize.ll
LLVM :: CodeGen/X86/switch.ll
LLVM :: CodeGen/X86/switch-bt.ll
LLVM :: CodeGen/X86/switch-density.ll

Reviewers: hans, fhahn

Reviewed By: hans

Subscribers: aemerson, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D40541

llvm-svn: 319210
2017-11-28 19:55:54 +00:00
Simon Pilgrim d49bd0cd87 [X86][SSE] Add SSE_HADDSUB/SSE_PABS/SSE_PALIGN OpndItins
Update multi-classes to take the scheduling OpndItins instead of hard coding it.

Will be reused in the AVX512 equivalents.

llvm-svn: 319209
2017-11-28 19:39:47 +00:00
Craig Topper dd4295626b [X86] In lowerVectorShuffleAsElementInsertion, if were able to find a scalar i8 or i16 and need to zero extend it, make sure we use a vXi32 type of the full vector width.
Previously, this was hardcoded to v4i32, but if the input type is 256 bits we need to use v8i32.

Fixes PR35443

llvm-svn: 319208
2017-11-28 19:25:45 +00:00
Francis Visoiu Mistrih 3aa8eaa951 [CodeGen] Fix doxygen \file comment style
llvm-svn: 319207
2017-11-28 19:23:39 +00:00
Francis Visoiu Mistrih d4b340b460 [CodeGen] Fix doxygen
llvm-svn: 319206
2017-11-28 19:15:46 +00:00
Sanjay Patel 1a72f67006 [InstCombine] auto-generate complete test checks; NFC
llvm-svn: 319205
2017-11-28 19:13:23 +00:00
Krzysztof Parzyszek 081e458e90 [Hexagon] Make sure to zero-extend bytes before building a vector
llvm-svn: 319204
2017-11-28 19:13:17 +00:00
Sanjay Patel b1a97d3774 [InstCombine] auto-generate complete test checks; NFC
llvm-svn: 319203
2017-11-28 19:07:28 +00:00
Daniel Sanders 17d277b734 [mir] Print/Parse both MOLoad and MOStore when they occur together.
Summary:
They're not always mutually exclusive. read-modify-write atomics are both
at the same time. One example of this is the SWP instructions on AArch64.
Another example is GlobalISel's G_ATOMICRMW_* generic instructions which
will be added in a later patch.

Reviewers: arphaman, aemerson

Reviewed By: aemerson

Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D40157

llvm-svn: 319202
2017-11-28 18:57:02 +00:00
Artem Belevich 50e6e54587 [CUDA] Report "unsupported VLA" errors only on device side.
This fixes erroneously reported CUDA compilation errors
in host-side code during device-side compilation.

I've also restricted OpenMP-specific checks to trigger only
if we're compiling with OpenMP enabled.

Differential Revision: https://reviews.llvm.org/D40275

llvm-svn: 319201
2017-11-28 18:51:42 +00:00
Rafael Espindola bba7f862d8 Fix non assert build warnings.
llvm-svn: 319200
2017-11-28 18:50:08 +00:00
Hans Wennborg ca46db957d EntryExitInstrumenter: set DebugLocs on the inserted call instructions (PR35412)
Apparently the verifier requires that inlineable calls in a function
with debug info have debug locations.

llvm-svn: 319199
2017-11-28 18:44:26 +00:00
Zachary Turner 6900de1dfb [CodeView] Refactor / Rewrite TypeSerializer and TypeTableBuilder.
The motivation behind this patch is that future directions require us to
be able to compute the hash value of records independently of actually
using them for de-duplication.

The current structure of TypeSerializer / TypeTableBuilder being a
single entry point that takes an unserialized type record, and then
hashes and de-duplicates it is not flexible enough to allow this.

At the same time, the existing TypeSerializer is already extremely
complex for this very reason -- it tries to be too many things. In
addition to serializing, hashing, and de-duplicating, ti also supports
splitting up field list records and adding continuations. All of this
functionality crammed into this one class makes it very complicated to
work with and hard to maintain.

To solve all of these problems, I've re-written everything from scratch
and split the functionality into separate pieces that can easily be
reused. The end result is that one class TypeSerializer is turned into 3
new classes SimpleTypeSerializer, ContinuationRecordBuilder, and
TypeTableBuilder, each of which in isolation is simple and
straightforward.

A quick summary of these new classes and their responsibilities are:

- SimpleTypeSerializer : Turns a non-FieldList leaf type into a series of
  bytes. Does not do any hashing. Every time you call it, it will
  re-serialize and return bytes again. The same instance can be re-used
  over and over to avoid re-allocations, and in exchange for this
  optimization the bytes returned by the serializer only live until the
  caller attempts to serialize a new record.

- ContinuationRecordBuilder : Turns a FieldList-like record into a series
  of fragments. Does not do any hashing. Like SimpleTypeSerializer,
  returns references to privately owned bytes, so the storage is
  invalidated as soon as the caller tries to re-use the instance. Works
  equally well for LF_FIELDLIST as it does for LF_METHODLIST, solving a
  long-standing theoretical limitation of the previous implementation.

- TypeTableBuilder : Accepts sequences of bytes that the user has already
  serialized, and inserts them by de-duplicating with a hash table. For
  the sake of convenience and efficiency, this class internally stores a
  SimpleTypeSerializer so that it can accept unserialized records. The
  same is not true of ContinuationRecordBuilder. The user is required to
  create their own instance of ContinuationRecordBuilder.

Differential Revision: https://reviews.llvm.org/D40518

llvm-svn: 319198
2017-11-28 18:33:17 +00:00
Simon Pilgrim 4fecbd8871 [X86][X87] Tag FP_TO_INT_IN_MEM pseudos with hasNoSchedulingInfo
We don't need scheduling info for pseudos

llvm-svn: 319197
2017-11-28 18:10:29 +00:00
Rafael Espindola b45c164fc2 Handle binding in --wrap.
Copying the binding seems reasonable and matches the bfd behavior.

llvm-svn: 319196
2017-11-28 18:02:22 +00:00
Craig Topper b338400188 [Target] Make a copy of TargetOptions feature list before sorting during CodeGen
Currently CodeGen is calling std::sort on the features vector in TargetOptions for every function, but I don't think CodeGen should be modifying TargetOptions.

Differential Revision: https://reviews.llvm.org/D40228

llvm-svn: 319195
2017-11-28 18:00:32 +00:00
Francis Visoiu Mistrih aa739695a4 [CodeGen] Separate MachineOperand implementation from MachineInstr
Move the implementation to its own file.

Differential Revision: https://reviews.llvm.org/D40419

llvm-svn: 319194
2017-11-28 17:58:43 +00:00