Commit Graph

13879 Commits

Author SHA1 Message Date
Chris Lattner 0a8d91a816 fix PR6332, allowing an index of zero into a zero sized array
even if the element of the array has no size.

llvm-svn: 101662
2010-04-17 19:02:33 +00:00
Chris Lattner b927073f2e teach the x86 asm parser how to handle segment prefixes
in memory operands.  rdar://7874844

llvm-svn: 101661
2010-04-17 18:56:34 +00:00
Dan Gohman 1f0f2142cc Fix -Wcast-qual warnings.
llvm-svn: 101655
2010-04-17 17:42:52 +00:00
Chris Lattner 05f34394d9 remove a dead variable, PR6856
llvm-svn: 101648
2010-04-17 17:28:00 +00:00
Dan Gohman 53d4a08d2b Add const qualifiers to TargetLoweringObjectFile usage.
llvm-svn: 101640
2010-04-17 16:44:48 +00:00
Dan Gohman 88f7f6aeda Use const_cast instead of a C-style cast to cast away const.
llvm-svn: 101639
2010-04-17 16:43:55 +00:00
Dan Gohman 8422e57baa Delete now-unnecessary const_casts.
llvm-svn: 101637
2010-04-17 15:32:28 +00:00
Dan Gohman 20e094c711 Use cast instead of dyn_cast when assuming success.
llvm-svn: 101636
2010-04-17 15:31:16 +00:00
Dan Gohman 21cea8ac2e Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635
2010-04-17 15:26:15 +00:00
Dan Gohman 31ae586c74 Move per-function state out of TargetLowering subclasses and into
MachineFunctionInfo subclasses.

llvm-svn: 101634
2010-04-17 14:41:14 +00:00
Chandler Carruth ca0a53ac52 Name these stub files consistently with the SPU and PPC targets' conventions.
Also rename the classes appropriately. The CMake build already used these
names.

llvm-svn: 101631
2010-04-17 08:50:29 +00:00
Chris Lattner 7f5088e6de a bunch of ssse3 instructions are misencoded to think they have an
i8 field when they really do not.  This fixes rdar://7840289

llvm-svn: 101629
2010-04-17 07:38:24 +00:00
Evan Cheng f1bd5fcdb4 More work to allow dag combiner to promote 16-bit ops to 32-bit.
llvm-svn: 101621
2010-04-17 06:13:15 +00:00
Bob Wilson 59b70eacad Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this
may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.

llvm-svn: 101615
2010-04-17 05:30:19 +00:00
Chris Lattner cfc921cd2a add a note
llvm-svn: 101581
2010-04-16 23:52:30 +00:00
Eric Christopher 7258dcd77f Revert 101465, it broke internal OpenGL testing.
Probably the best way to know that all getOperand() calls have been handled
is to replace that API instead of updating.

llvm-svn: 101579
2010-04-16 23:37:20 +00:00
Johnny Chen c275414575 Cast to (uint64_t) instead of relying on the "ul" suffix.
llvm-svn: 101573
2010-04-16 23:30:28 +00:00
Dan Gohman 9becdddc49 Add skeleton target-specific SelectionDAGInfo files.
llvm-svn: 101564
2010-04-16 23:04:22 +00:00
Johnny Chen ed9bee150b Fixed logic error. Should check Builder for validity before calling SetSession
on it.

llvm-svn: 101563
2010-04-16 23:02:25 +00:00
Johnny Chen b90b6f1a35 Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a
case.  Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.

Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().

llvm-svn: 101557
2010-04-16 22:40:20 +00:00
Chris Lattner d4758fc393 add a missing break back, patch by Nico Schmidt!
llvm-svn: 101538
2010-04-16 21:15:15 +00:00
Dan Gohman 148c69a3f6 Eliminate an unnecessary SelectionDAG dependency in getOptimalMemOpType.
llvm-svn: 101531
2010-04-16 20:11:05 +00:00
Johnny Chen 2b7aba10c2 In the same spirit of r101524, which removed the assert() from printAddrMode2OffsetOperand(),
this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.

llvm-svn: 101529
2010-04-16 19:57:21 +00:00
Johnny Chen 807e1748fc Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed
to the UAL syntax of LDCL<c>, instead.

Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().

llvm-svn: 101527
2010-04-16 19:33:23 +00:00
Johnny Chen 88599a42bb Remove the assert() from printAddrMode2OffsetOperand(). "#0 and #-0" are
considered legal instructions.

Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM)
-- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395.

llvm-svn: 101524
2010-04-16 19:10:52 +00:00
Gabor Greif f375520f7b reapply r101434
with a fix for self-hosting

rotate CallInst operands, i.e. move callee to the back
of the operand array

the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary

llvm-svn: 101465
2010-04-16 15:33:14 +00:00
Evan Cheng af56facacd Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding.
x86 support is off by default. It can be enabled with -promote-16bit.

Work in progress.

llvm-svn: 101448
2010-04-16 06:14:10 +00:00
Evan Cheng 3da64f7672 Use getAL() rather than a major constant.
llvm-svn: 101446
2010-04-16 05:46:06 +00:00
Gabor Greif 403e9694f9 back out r101423 and r101397, they break llvm-gcc self-host on darwin10
llvm-svn: 101434
2010-04-16 01:16:20 +00:00
Johnny Chen acbc06c2a3 Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not
am2offset.  Modified the instruction table entry and added a new test case.

llvm-svn: 101415
2010-04-15 23:12:47 +00:00
Evan Cheng f7f97b4bbd Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.
llvm-svn: 101410
2010-04-15 22:20:34 +00:00
Gabor Greif 33ae80bff7 reapply r101364, which has been backed out in r101368
with a fix

rotate CallInst operands, i.e. move callee to the back
of the operand array

the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary

llvm-svn: 101397
2010-04-15 20:51:13 +00:00
Evan Cheng 1ba1428577 ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908
llvm is generating poor code for dynamic alloca, I'll fix that later.

llvm-svn: 101383
2010-04-15 18:42:28 +00:00
Johnny Chen 4230e35879 DEBUG() print out "Unknown format" msg.
llvm-svn: 101382
2010-04-15 18:13:51 +00:00
Dan Gohman 48a189280e ReuseFrameIndexVals is used in multiple files, so it can't be static.
llvm-svn: 101379
2010-04-15 17:34:58 +00:00
Dan Gohman 2085719a98 EnablePPC64RS and EnablePPC32RS are used in multiple files, so they
can't be static.

llvm-svn: 101377
2010-04-15 17:20:57 +00:00
Dan Gohman b29cda9b3c Fix a bunch of namespace polution.
llvm-svn: 101376
2010-04-15 17:08:50 +00:00
Gabor Greif 9fd00c7d25 back out r101364, as it trips the linux nightlybot on some clang C++ tests
llvm-svn: 101368
2010-04-15 12:46:56 +00:00
Gabor Greif aafd209632 rotate CallInst operands, i.e. move callee to the back
of the operand array

the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary

llvm-svn: 101364
2010-04-15 10:49:53 +00:00
Chris Lattner 4041ab6e00 Implement rdar://7860110 (also in target/readme.txt) narrowing
a load/or/and/store sequence into a narrower store when it is
safe.  Daniel tells me that clang will start producing this sort
of thing with bitfields, and this does  trigger a few dozen times
on 176.gcc produced by llvm-gcc even now.

This compiles code like CodeGen/X86/2009-05-28-DAGCombineCrash.ll 
into:

        movl    %eax, 36(%rdi)

instead of:

        movl    $4294967295, %eax       ## imm = 0xFFFFFFFF
        andq    32(%rdi), %rax
        shlq    $32, %rcx
        addq    %rax, %rcx
        movq    %rcx, 32(%rdi)

and each of the testcases into a single store.  Each of them used
to compile into craziness like this:

_test4:
	movl	$65535, %eax            ## imm = 0xFFFF
	andl	(%rdi), %eax
	shll	$16, %esi
	addl	%eax, %esi
	movl	%esi, (%rdi)
	ret

llvm-svn: 101343
2010-04-15 04:48:01 +00:00
Dan Gohman 913c998703 Add more const qualifiers for LLVM IR pointers in CodeGen.
llvm-svn: 101342
2010-04-15 04:33:49 +00:00
Anders Carlsson 47bccf7f28 Fix build.
llvm-svn: 101335
2010-04-15 03:11:28 +00:00
Dan Gohman bcaf681cde Add const qualifiers to CodeGen's use of LLVM IR constructs.
llvm-svn: 101334
2010-04-15 01:51:59 +00:00
Eric Christopher eabc9623da Allow lowering for palignr instructions for mmx sized vectors. Add
patterns to handle the lowering.

llvm-svn: 101331
2010-04-15 01:40:20 +00:00
Johnny Chen 0175ec1263 Wrap the error msgs in DEBUG() macro so that they won't appear in NDEBUG build.
llvm-svn: 101329
2010-04-15 01:20:56 +00:00
Johnny Chen 82c50b11fa Fixed another assert exposed by fuzzing. Now, the DisassembleVFPLdStMulFrm()
function checks whether we have a valid submode for VLDM/VSTM (must be either
"ia" or "db") before calling ARM_AM::getAM5Opc(AMSubMode, unsigned char).

llvm-svn: 101306
2010-04-14 22:37:17 +00:00
Jim Grosbach 32bb362655 Add -arm-long-calls option to force calls to be indirect. This makes the
kernel linker happier when dealing with kexts.

Radar 7805069

llvm-svn: 101303
2010-04-14 22:28:31 +00:00
Johnny Chen 9aaaf4d5fa For t2BFI disassembly, apply the same error checking as in r101205.
Change the error msg to read "Encoding error: msb < lsb".

llvm-svn: 101293
2010-04-14 22:04:45 +00:00
Johnny Chen 7637827064 Fixed another assert exposed by fuzzing. The utility function getRegisterEnum()
was asserting because the (RegClass, RegNum) combination doesn't make sense from
an encoding point of view.

Since getRegisterEnum() is used all over the place, to change the code to check
for encoding error after each call would not only bloat the code, but also make
it less readable.  An Err flag is added to the ARMBasicMCBuilder where a client
can set a non-zero value to indicate some kind of error condition while building
up the MCInst.  ARMBasicMCBuilder::BuildIt() checks this flag and returns false
if a non-zero value is detected.

llvm-svn: 101290
2010-04-14 21:03:13 +00:00
Bob Wilson c05b887c84 Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand
does not have a legal type.  The legalizer does not know how to handle those
nodes.  Radar 7854640.

llvm-svn: 101282
2010-04-14 20:45:23 +00:00