Commit Graph

163041 Commits

Author SHA1 Message Date
Sander de Smalen 149916d29a [AArch64][AsmParser] Extend RegOp with integrated 'shift/extend'.
Summary:
In some cases the shift/extend needs to be explicitly parsed together
with the register, rather than as a separate operand. This is needed
for addressing modes where the instruction as a whole dictates the
scaling/extend, rather than specific bits in the instruction.
By parsing them as a single operand, we avoid the need to pass an
extra operand in all CodeGen patterns (because all operands need to
have an associated value), and we avoid the need to update TableGen to
accept operands that have no associated bits in the instruction.

An added benefit of parsing them together is that the assembler
can give a sensible diagnostic if the scaling is not correct.

This is patch [2/4] in a series to add assembler/disassembler support for
SVE's contiguous LD1 (scalar+scalar) instructions:
- Patch [1/4]: https://reviews.llvm.org/D45687
- Patch [2/4]: https://reviews.llvm.org/D45688
- Patch [3/4]: https://reviews.llvm.org/D45689
- Patch [4/4]: https://reviews.llvm.org/D45690

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: fhahn, SjoerdMeijer

Subscribers: kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45688

llvm-svn: 330394
2018-04-20 07:24:20 +00:00
Nicolai Haehnle 7a87977fb2 AMDGPU: Legalize the operand of SI_INIT_M0
Summary:
This fixes a case where the argument to a sendmsg intrinsic
ends up in a VGPR, for whatever reason.

The underlying performance issue is that a multiplication that
can be an s_mul_i32 is instead needlessly generated as
v_mul_u32_u24, but this is not addressed by this patch.

Change-Id: I61fd4034314d5acdf6074632c30b65364dfa7328

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D45826

llvm-svn: 330393
2018-04-20 07:14:25 +00:00
Daniel Cederman 793af3b9f0 [Sparc] Fix addressing mode when using 64-bit values in inline assembly
Summary:
If a 64-bit register is used as an operand in inline assembly together
with a memory reference, the memory addressing will be wrong. The
addressing will be a single reg, instead of reg+reg or reg+imm. This
will generate a bad offset value or an exception in printMemOperand().

For example:

```
long long int val = 5;
long long int mem;
__asm__ volatile ("std %1, %0":"=m"(mem):"r"(val));
```
becomes:

```
std %i0, [%i2+589833]
```

The problem is that SelectInlineAsmMemoryOperand() is never called for
the memory references if one of the operands is a 64-bit register.
By calling SelectInlineAsmMemoryOperands() in tryInlineAsm() the Sparc
version of  SelectInlineAsmMemoryOperand() gets called for each memory
reference.

Reviewers: jyknight, venkatra

Reviewed By: jyknight

Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits

Differential Revision: https://reviews.llvm.org/D45761

llvm-svn: 330392
2018-04-20 06:57:49 +00:00
Vlad Tsyrklevich 5d15230c37 Fix build failures for r330387 on buildbots that don't build the X86 target
llvm-svn: 330388
2018-04-20 02:26:12 +00:00
Vlad Tsyrklevich 230b256783 LowerTypeTests: Propagate symver directives
Summary:
This change fixes https://crbug.com/834474, a build failure caused by
LowerTypeTests not preserving .symver symbol versioning directives for
exported functions. Emit symver information to ThinLTO summary data and
then propagate symver directives for exported functions to the merged
module.

Emitting symver information to the summaries increases the size of
intermediate build artifacts for a Chromium build by less than 0.2%.

Reviewers: pcc

Reviewed By: pcc

Subscribers: tejohnson, mehdi_amini, eraman, llvm-commits, eugenis, kcc

Differential Revision: https://reviews.llvm.org/D45798

llvm-svn: 330387
2018-04-20 01:36:48 +00:00
Amara Emerson 6aacbf4d7c Move a dump() implementation out of line.
Fixes some link issues.

llvm-svn: 330384
2018-04-20 00:42:46 +00:00
Jessica Paquette 1eca23bdd8 [MachineOutliner] NFC: Move EnableLinkOnceODROutlining into MachineOutliner.cpp
This moves the EnableLinkOnceODROutlining flag from TargetPassConfig.cpp into
MachineOutliner.cpp. It also removes OutlineFromLinkOnceODRs from the
MachineOutliner constructor. This is now handled by the moved command-line
flag.

llvm-svn: 330373
2018-04-19 22:17:07 +00:00
Simon Pilgrim 0a6bfb1843 [llvm-mca][X86] Add prefetch instruction resource tests
llvm-svn: 330371
2018-04-19 22:11:58 +00:00
Sam Clegg f009da2448 [WebAssembly] Enabled -triple=wasm32-unknown-unknown-wasm path using ELF directive parser.
This is a temporary solution until a proper WASM implementation of
MCAsmParserExtension is in place, but at least for now will unblock this
path.

Added test to make sure this path works with the WASM Assembler.

Patch By Wouter van Oortmerssen!

Differential Revision: https://reviews.llvm.org/D45386

llvm-svn: 330370
2018-04-19 22:00:53 +00:00
Sanjay Patel ad8976db16 [Reassociate] add baseline tests for binop swapping; NFC
Similar to rL330086, I don't know if we want to do these 
transforms here, but we might as well have the tests
here either way to show that this pass is missing 
potential functionality (intentionally or not).

llvm-svn: 330368
2018-04-19 21:56:17 +00:00
Simon Pilgrim 7209117868 [llvm-mca][FMA] Add FMA resource tests
llvm-svn: 330366
2018-04-19 21:32:22 +00:00
Stanislav Mekhanoshin 160f85794d [AMDGPU] Use packed literals with zero either lower or hi part
Differential Revision: https://reviews.llvm.org/D45790

llvm-svn: 330365
2018-04-19 21:16:50 +00:00
Gerolf Hoflehner bf26d54047 [llvm-objdump] Issue error message when object file cannot be created
llvm-svn: 330364
2018-04-19 20:48:35 +00:00
Craig Topper 6496d51284 [X86] Remove non-existant instruction name from X86DisassemblerTables.cpp.
This instruction was removed a long time so we don't need to check for it here.

llvm-svn: 330363
2018-04-19 20:44:15 +00:00
Jin Lin 585f2699cf Refine the loop rotation's API
Summary:
The following changes addresses the following two issues.

1) The existing loop rotation pass contains both loop latch simplification and loop rotation. So one flag RotationOnly is added to be passed to the loop rotation pass.
2) The threshold value is initialized with MAX_UINT since the loop rotation utility should not have threshold limit.

Reviewers: dmgreen, efriedma

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D45582

llvm-svn: 330362
2018-04-19 20:29:43 +00:00
Lang Hames ee68ec06a1 [ORC] Fix an assertion condition from r329934.
Thanks to Alexander Ivchenko for finding the issue!

llvm-svn: 330359
2018-04-19 19:30:35 +00:00
Craig Topper bc895a3afc [X86] Enable popcnt false dependency breaking on Silvermont and Goldmont.
Silvermont and Goldmont have the same issue on popcnt as Sandy Bridge, Haswell, Broadwell, and Skylake. Believe it is fixed in Goldmont Plus.

llvm-svn: 330358
2018-04-19 19:25:24 +00:00
Chandler Carruth 32e62f9c5b [PM/LoopUnswitch] Detect irreducible control flow within loops and skip unswitching non-trivial edges.
Summary:
This fixes the bug pointed out in review with non-trivial unswitching.

This also provides a basis that should make it pretty easy to finish
fleshing out a routine to scan an entire function body for irreducible
control flow, but this patch remains minimal for disabling loop
unswitch.

Reviewers: sanjoy, fedor.sergeev

Subscribers: mcrosier, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D45754

llvm-svn: 330357
2018-04-19 18:44:25 +00:00
Lang Hames 9bbd653084 [ORC] Make VSO symbol resolution/finalization operations private.
This forces these operations to be carried out via a
MaterializationResponsibility instance, ensuring responsibility is explicitly
tracked.

llvm-svn: 330356
2018-04-19 18:42:49 +00:00
Simon Pilgrim 4a486c13fa [llvm-mca][X86] Add resource test for every out-of-order scheduler model
I've copied and regenerated a resource file from btver2 to every x86 scheduler model supported by llvm-mca so we have at least some basic coverage.

For most this has been the avx1 tests, but for silvermont I've used sse42 as thats the latest it supports.

More will be added later.

llvm-svn: 330352
2018-04-19 18:08:10 +00:00
Simon Pilgrim 4ba057dbd1 [X86][SLM] Fix typo using SandyBridge resources.
Luckily this was on instructions not supported on Silvermont....

llvm-svn: 330351
2018-04-19 18:01:52 +00:00
Craig Topper b5f2659130 [X86] Correct the scheduling data for register forms of XCHG and XADD on Intel CPUs.
The XCHG16rr/XCHG32rr/XCHG64rr instructions should be 3 uops just like XCHG8rr. I believe they're just implemented as 3 move uops with a temporary register.

XADD is probably 2 moves and an add also using a temporary register.

Change the latency for both from 2 cycles to 3 cycles. Only 2 of the uops are serialized in their execution, the move into the temporary and the move out of the temporary. The move from one GPR to the other should be able to go in parallel with this if there are ALU resources available.

llvm-svn: 330349
2018-04-19 18:00:17 +00:00
Sanjay Patel a201787fd7 [Reassociate] fix formatting; NFC
llvm-svn: 330348
2018-04-19 17:56:36 +00:00
Simon Pilgrim 5e492d29a3 [X86] Merge some MMX instregex
There's a lot more but I'd prefer focussing on removing unnecessary InstRWs first.

llvm-svn: 330347
2018-04-19 17:32:10 +00:00
Krzysztof Parzyszek fbee8574ab [if-converter] Handle BBs that terminate in ret during diamond conversion
This fixes https://llvm.org/PR36825.

Original patch by Valentin Churavy (D45218).

Differential Revision: https://reviews.llvm.org/D45731

llvm-svn: 330345
2018-04-19 17:26:46 +00:00
Krzysztof Parzyszek 2a9a83cd3f [Hexagon] Use legal types when lowering CONCAT_VECTORS via BUILD_VECTOR
llvm-svn: 330344
2018-04-19 17:11:58 +00:00
Francis Visoiu Mistrih dca79d2867 [llvm-objdump] Remove test object file
Forgot to remove it from the previous commit.

llvm-svn: 330343
2018-04-19 17:05:03 +00:00
Francis Visoiu Mistrih 1834682b97 [llvm-objdump] Print "..." instead of random data for virtual sections
When disassembling with -D, skip virtual sections by printing "..." for
each symbol.

This patch also implements `MachOObjectFile::isSectionVirtual`.

Test case comes from:

```
.zerofill __DATA,__common,_data64unsigned,472,3
```

Differential Revision: https://reviews.llvm.org/D45824

llvm-svn: 330342
2018-04-19 17:02:57 +00:00
Teresa Johnson aa94393ec5 [gold/ThinLTO] Invoke llvm_shutdown when exiting after ThinLTO indexing
Summary:
Instead of manually invoking PrintStatistics, simply invoke
llvm_shutdown which will take care of destroying managed statics, and as
a side effect will destroy the StatisticInfo ManagedStatic, invoking
PrintStatistics when needed.

Reviewers: fhahn

Subscribers: inglorion, llvm-commits

Differential Revision: https://reviews.llvm.org/D45820

llvm-svn: 330341
2018-04-19 16:55:13 +00:00
Mark Searles 1bc6e71f32 [AMDGPU] Do not only rely on BB number when finding bottom loop
We should also check that the "bottom" basic block of a loopis a successor of the "header" basic block, otherwise we don't propagate the information correctly when the CFG is complex. This fixes an important rendering problem with Wolfsentein 2, because of one vector-memory wait was missing.

Differential Revision: https://reviews.llvm.org/D43831

llvm-svn: 330337
2018-04-19 15:42:30 +00:00
Simon Pilgrim f209321d61 [llvm-mca][X86] Add mmx instruction to btver2 resource tests
Useful to see scheduler class deltas against xmm equivalents

llvm-svn: 330335
2018-04-19 15:09:46 +00:00
Florian Hahn b789165e6b [NewGVN] Add ops as dependency if we cannot find a leader for ValueOp.
If those operands change, we might find a leader for ValueOp, which
could enable new phi-of-op creation.

This fixes a case where we missed creating a phi-of-ops node. With D43865
and this patch, bootstrapping clang/llvm works with -enable-newgvn, whereas
without it, the "value changed after iteration" assertion is triggered.

Reviewers: dberlin, davide

Reviewed By: dberlin

Differential Revision: https://reviews.llvm.org/D42180

llvm-svn: 330334
2018-04-19 15:05:47 +00:00
Krzysztof Parzyszek d92c37e090 [Hexagon] Generate code for vector bswap intrinsics
llvm-svn: 330333
2018-04-19 14:46:44 +00:00
Simon Pilgrim f21ace6cdd [X86][BtVer2] Remove SSE4A EXTRQ/EXTRQI InstRW overrides.
These are already handled identically by WriteALU.

llvm-svn: 330332
2018-04-19 14:38:36 +00:00
Krzysztof Parzyszek 23bcf06a15 [Hexagon] Add/fix patterns for 32/64-bit vector compares and logical ops
llvm-svn: 330330
2018-04-19 14:24:31 +00:00
Mikhail Maltsev aeb6c48d29 [Unittests] Fix plugins test
Summary:
Currently the PluginsTests.LoadPlugin unit test is failing in
LLVM configurations that have LLVM_EXPORT_SYMBOLS_FOR_PLUGINS enabled
because the EnableABIBreakingChecks symbol is missing.

This patch fixes the issue by linking some additional libraries to the
test plugin if LLVM_EXPORT_SYMBOLS_FOR_PLUGINS is enabled.

Reviewers: philip.pfaffe

Reviewed By: philip.pfaffe

Subscribers: mgorny, llvm-commits, rogfer01

Differential Revision: https://reviews.llvm.org/D45811

llvm-svn: 330329
2018-04-19 14:02:46 +00:00
Simon Dardis 5d61c8b225 [mips] Correct the definitions of the unaligned word memory operation instructions
These instructions lacked the correct predicates, were not marked
as loads and stores and lacked the proper instruction mapping information.

In the case of microMIPS sw(l|r)e (EVA) these instructions were using the load
EVA description.

Reviewers: abeserminji, smaksimovic, atanasyan

Differential Revision: https://reviews.llvm.org/D45626

llvm-svn: 330326
2018-04-19 13:33:51 +00:00
Roman Lebedev d536de1e7b [NFC][InstCombine] A few more tests for masked merge add/xor -> or with constant mask
llvm-svn: 330325
2018-04-19 13:02:17 +00:00
Alexander Ivchenko e8fed1546e Lowering x86 adds/addus/subs/subus intrinsics (llvm part)
This is the patch that lowers x86 intrinsics to native IR
in order to enable optimizations. The patch also includes folding
of previously missing saturation patterns so that IR emits the same
machine instructions as the intrinsics.

Patch by tkrupa

Differential Revision: https://reviews.llvm.org/D44785

llvm-svn: 330322
2018-04-19 12:13:30 +00:00
Florian Hahn 9a175bc1bc Remove file accidentally added in r330320.
llvm-svn: 330321
2018-04-19 12:09:05 +00:00
Florian Hahn 2342533e1a [IR/BasicBlockTest] Fix asan failure introduced in rL330316.
The argument has to be deleted after the module containing the function
gets deleted.

llvm-svn: 330320
2018-04-19 12:06:26 +00:00
Simon Pilgrim 3c06617f0e [X86][FMA] Remove FMA reg-reg InstRW scheduler overrides.
These are all already handled identically by WriteFMA.

llvm-svn: 330319
2018-04-19 11:37:26 +00:00
Simon Pilgrim 33dede9075 [X86][BtVer2] Remove 128-bit F16C InstRW overrides.
These are already handled identically by WriteCvtF2F.

llvm-svn: 330318
2018-04-19 11:16:33 +00:00
Simon Pilgrim b04cd1b9f3 [llvm-exegesis] Fix PfmIssueCountersTable creation
This patch ensures that the pfm issue counter tables are the correct size, accounting for the invalid resource entry at the beginning of the resource tables.

It also fixes an issue with pfm failing to match event counters due to a trailing comma added to all the event names.

I've also added a counter comment to each entry as it helps locate problems with the tables.

Note: I don't have access to a SandyBridge test machine, which is the only model to make use of multiple event counters being mapped to a single resource. I don't know if pfm accepts a comma-seperated list or not, but that is what it was doing.

Differential Revision: https://reviews.llvm.org/D45787

llvm-svn: 330317
2018-04-19 10:59:49 +00:00
Florian Hahn 147fc016e3 [BasicBlock] Add instructionsWithoutDebug methods to skip debug insts.
Reviewers: aprantl, vsk, mattd, chandlerc

Reviewed By: aprantl, vsk

Differential Revision: https://reviews.llvm.org/D45657

llvm-svn: 330316
2018-04-19 09:48:07 +00:00
Simon Dardis fdc052686c [mips] Guard some macro expansions properly
Reviewers: atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D45565

llvm-svn: 330315
2018-04-19 09:45:04 +00:00
Sjoerd Meijer a79ea80d7b [ARM] Add some missing FP16 VSEL test cases
Differential Revision: https://reviews.llvm.org/D45724

llvm-svn: 330313
2018-04-19 08:21:50 +00:00
Sander de Smalen 50d8702f26 [AArch64][AsmParser] NFC: Cleanup parsing of scalar registers.
Summary:
- Renamed tryParseRegister to tryParseScalarRegister, which
  now returns an OperandMatchResultTy.
- Moved matching of certain aliases into matchRegisterNameAlias.
- Changed type of most 'Reg' variables to 'unsigned'.

This is patch [1/4] in a series to add assembler/disassembler support for
SVE's contiguous LD1 (scalar+scalar) instructions:
- Patch [1/4]: https://reviews.llvm.org/D45687
- Patch [2/4]: https://reviews.llvm.org/D45688
- Patch [3/4]: https://reviews.llvm.org/D45689
- Patch [4/4]: https://reviews.llvm.org/D45690

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro, samparker

Reviewed By: samparker

Subscribers: samparker, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45687

llvm-svn: 330311
2018-04-19 07:35:08 +00:00
Craig Topper f846e2d1b1 [X86] Scrub scheduling information for MUL/IMUL on Intel CPUs.
This removes a bunch of unnecessary InstRW overrides. It also cleans up the missing information from the Sandy Bridge model. Other fixes to other models.

llvm-svn: 330308
2018-04-19 05:34:05 +00:00
Bob Haarman cb80a3fce0 Fix data race in X86FloatingPoint.cpp ASSERT_SORTED
Summary:
ASSERT_SORTED checks if a table is sorted, and uses a boolean to
prevent the check from being run again if it was earlier determined
that the table is in fact sorted. Unsynchronized reads and writes of
that boolean triggered ThreadSanitizer's data race detection. This
change rewrites the code to use std::atomic<bool> instead.

Fixes PR36922.

Reviewers: rnk

Reviewed By: rnk

Subscribers: llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D45742

llvm-svn: 330301
2018-04-18 23:04:09 +00:00