Commit Graph

23 Commits

Author SHA1 Message Date
Marek Olsak eac5062cc0 R600/SI: Use i32 vectors for resources and samplers
This affects new intrinsics only.

What surprises me is that v32i8 still works.

llvm-svn: 212831
2014-07-11 17:11:52 +00:00
Marek Olsak d8ecaeec02 R600/SI: add sample and image intrinsics exposing all instruction fields
We need the intrinsics with offsets, so why not just add them all.
The R128 parameter will also be useful for reducing SGPR usage.
GL_ARB_image_load_store also adds some image GLSL modifiers like "coherent",
so Mesa will probably translate those to slc, glc, etc.

When LLVM 3.5 is released, I'll switch Mesa to these new intrinsics.

llvm-svn: 212830
2014-07-11 17:11:46 +00:00
Marek Olsak 51b8e7b2e7 R600/SI: add gather4 and getlod intrinsics (v3)
This contains all the previous patches + getlod support on top of it.
It doesn't use SDNodes anymore, so it's quite small.
It also adds v16i8 to SReg_128, which is used for the sampler descriptor.

Reviewed-by: Tom Stellard
llvm-svn: 211228
2014-06-18 22:00:29 +00:00
Michel Danzer 13736221e3 R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 200196
2014-01-27 07:20:51 +00:00
Michel Danzer 6064f57ae8 R600/SI: Add intrinsic for S_SENDMSG instruction
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 200195
2014-01-27 07:20:44 +00:00
Tom Stellard afcf12f33a R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback
For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist.

The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take
a resource descriptor might be nicer.

The maximum number of input SGPRs is bumped to 17.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 190575
2013-09-12 02:55:14 +00:00
Tom Stellard 9fa1791a1b R600/SI: Convert v16i8 resource descriptors to i128
Now that compute support is better on SI, we can't continue using v16i8
for descriptors since this is also a legal type in OpenCL.

This patch fixes numerous hangs with the piglit OpenCL test and since
we now use a target specific DAG node for LOAD_CONSTANT with the
correct MemOperandFlags, this should also fix:

https://bugs.freedesktop.org/show_bug.cgi?id=66805

llvm-svn: 188429
2013-08-14 23:24:45 +00:00
Michel Danzer 8d69617b27 R600/SI: Add intrinsic for retrieving the current thread ID
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186010
2013-07-10 16:36:52 +00:00
Michel Danzer 83f87c4c2e R600/SI: Add intrinsics for texture sampling with user derivatives
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186008
2013-07-10 16:36:36 +00:00
Tom Stellard f787ef1d96 R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181269
2013-05-06 23:02:19 +00:00
Tom Stellard 353b336e8c R600/SI: Add intrinsic for texture image loading
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181267
2013-05-06 23:02:12 +00:00
Christian Konig 4ace663255 R600/SI: remove image sample writemask
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179164
2013-04-10 08:39:01 +00:00
Christian Konig 727d06de1d R600/SI: mark most intrinsics as readnone v2
They read from constant register space anyway.

v2: fix lit tests

Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178020
2013-03-26 14:03:57 +00:00
Christian Konig 737d4a1665 R600/SI: replace WQM intrinsic
Just enable WQM when we see an LDS interpolation instruction.

Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178019
2013-03-26 14:03:50 +00:00
Christian Konig 49374087f5 R600/SI: implement SI.load.const intrinsic
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 177273
2013-03-18 11:33:55 +00:00
Christian Konig 99ee0f4790 R600/SI: rework input interpolation v2
v2: update CMakeLists.txt as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176626
2013-03-07 09:04:14 +00:00
Christian Konig aa9f4e6d3a R600/SI: remove SI_vs_load_buffer_index
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176625
2013-03-07 09:04:04 +00:00
Christian Konig 2214f14ab9 R600/SI: switch types of SGPRs to v*i8
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176621
2013-03-07 09:03:38 +00:00
Tom Stellard ae6c06e5de R600/SI: Make sample intrinsic address parameter type overloaded.
Handle vectors of 1 to 16 integers.

Change the intrinsic names to prevent the wrong one from being selected at
runtime due to the overloading.

Patch By: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174633
2013-02-07 17:02:13 +00:00
Tom Stellard 14421a793f R600/SI: Take target parameter for sample intrinsics.
Patch by: Michel Dänzer

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 173052
2013-01-21 15:40:47 +00:00
Tom Stellard 74dda0da31 R600/SI: Derive all sample intrinsics from a single class.
Patch by: Michel Dänzer

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 173051
2013-01-21 15:40:46 +00:00
Tom Stellard f8794354b2 R600: New control flow for SI v2
This patch replaces the control flow handling with a new
pass which structurize the graph before transforming it to
machine instruction. This has a couple of different advantages
and currently fixes 20 piglit tests without a single regression.

It is now a general purpose transformation that could be not
only be used for SI/R6xx, but also for other hardware
implementations that use a form of structurized control flow.

v2: further cleanup, fixes and documentation

Patch by: Christian König

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 170591
2012-12-19 22:10:31 +00:00
Tom Stellard 75aadc2813 Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX

llvm-svn: 169915
2012-12-11 21:25:42 +00:00