Commit Graph

279961 Commits

Author SHA1 Message Date
Craig Topper 243f20f117 [lli] Make lli support -mcpu=native for CPU autodetection
llc, opt, and clang can all autodetect the CPU and supported features. lli cannot as far as I could tell.

This patch uses the getCPUStr() and introduces a new getCPUFeatureList() and uses those in lli in place of MCPU and MAttrs.

Ideally, we would merge getCPUFeatureList and getCPUFeatureStr, but opt and llc need a string and lli wanted a list. Maybe we should just return the SubtargetFeature object and let the caller decide what it needs?

Differential Revision: https://reviews.llvm.org/D41833

llvm-svn: 322100
2018-01-09 18:14:18 +00:00
Matthew Voss 3e826f4f1b Test commit
This is a commit to test commit access.

llvm-svn: 322099
2018-01-09 17:52:00 +00:00
Florian Hahn 4ed75a73e6 [TargetParser] Add missing armv8l ARMv8 variant.
This change adds the missing armv8l variant as an alias of armv8 architecture.
The issue was observed with several regressions in validation on armv8l
hardware (for instance ExecutionEngine/frem.ll failed due to lack of neon fpu).

Tested with regression testsuite passed without regression on ARM and x86_64.

Patch by Yvan Roux.

Reviewers: rengolin, rogfer01, olista01, fhahn

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D41859

llvm-svn: 322098
2018-01-09 17:49:25 +00:00
Eric Liu 76f6b44443 [clangd] Add more symbol information for code completion.
Reviewers: hokein, sammccall

Reviewed By: sammccall

Subscribers: klimek, ilya-biryukov, cfe-commits

Differential Revision: https://reviews.llvm.org/D41345

llvm-svn: 322097
2018-01-09 17:32:00 +00:00
Francis Visoiu Mistrih 7d9bef8f5c [CodeGen] Don't print "pred:" and "opt:" in -debug output
In -debug output we print "pred:" whenever a MachineOperand is a
predicate operand in the instruction descriptor, and "opt:" whenever a
MachineOperand is an optional def in the instruction descriptor.

Differential Revision: https://reviews.llvm.org/D41870

llvm-svn: 322096
2018-01-09 17:31:07 +00:00
Davide Italiano 4762c069de [Support] Use realpath(3) instead of trying to open a file.
If we don't have read permissions on the directory the call would
fail.

<rdar://problem/35871293>

llvm-svn: 322095
2018-01-09 17:27:45 +00:00
Pavel Labath 9aaf5d3e71 [Support] Add WritableMemoryBuffer::getNewMemBuffer
Summary:
The idea is that it would replace
(non-Writable)MemoryBuffer::getNewMemBuffer, which is quite useless
unless you const_cast its contents to write to it (which all (both)
callers of this function were doing). This patch also fixes one of the usages in
COFFWriter. After fixing the other usage in clang, I plan to delete the old
function.

Reviewers: dblaikie, Bigcheese

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41540

llvm-svn: 322094
2018-01-09 17:26:06 +00:00
John Baldwin 40bab37551 [libunwind][MIPS]: Rename Registers_mips_n64 to Registers_mips_newabi.
This is in preparation for adding support for N32 unwinding which reuses
the newabi register class.

Reviewed By: compnerd

Differential Revision: https://reviews.llvm.org/D41842

llvm-svn: 322093
2018-01-09 17:07:18 +00:00
Sander de Smalen 906a5deace Recommit r322073: [AArch64][SVE] Asm: Add predicated ADD/SUB instructions
Fixed issue that was found on sanitizer-x86_64-linux-fast.
I changed the result type of 'Parser.getTok().getString().lower()'
in AArch64AsmParser::tryParseSVEPredicateVector() from 'StringRef' to
'auto', since StringRef::lower() returns a std::string.

llvm-svn: 322092
2018-01-09 17:01:27 +00:00
Aleksei Sidorin e267a0f342 [ASTImporter] Support importing CXXUnresolvedConstructExpr and UnresolvedLookupExpr
* Note: This solution is based on
  https://github.com/haoNoQ/clang/blob/summary-ipa-draft/lib/AST/ASTImporter.cpp#L7605.

Patch by Peter Szecsi!

Differential Revision: https://reviews.llvm.org/D38694

llvm-svn: 322091
2018-01-09 16:40:40 +00:00
Zvi Rackover 72b0bb1405 X86 Tests: Update more isel tests with FastVariableShuffle feature
Summary:
Added the FastVariableShuffle feature to cases that resembled processors
for which this fearure is on.
For AVX2 there are processors with and w/o this fearue enable.
For AVX512 only KNL does enable this feature so cases which only have
+avx512f were left without the FastVariableShuffle enabled.

Reviewers: RKSimon, craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41851

llvm-svn: 322090
2018-01-09 16:26:06 +00:00
Zvi Rackover b11e84c1d8 X86 Tests: Add common check prefix to test-case. NFC.
As suggested in D41851

llvm-svn: 322089
2018-01-09 16:14:15 +00:00
Francis Visoiu Mistrih 72cc21eefe [CodeGen] Print frame-setup/destroy flags in -debug output like we do in MIR
Currently the MachineInstr::print function prints the
frame-setup/frame-destroy differently than it does in MIR.

Instead of:

  %x21 = LDR %sp, -16; flags: FrameDestroy

print:

  %x21 = frame-destroy LDR %sp, -16

llvm-svn: 322088
2018-01-09 16:11:51 +00:00
Sanjay Patel 37e28e40cb [SelectionDAG] lower math intrinsics to finite version of libcalls when possible (PR35672)
Ingredients in this patch:
1. Add HANDLE_LIBCALL defs for finite mathlib functions that correspond to LLVM intrinsics.
2. Plumbing to send TargetLibraryInfo down to SelectionDAGLegalize.
3. Relaxed math and library checking in SelectionDAGLegalize::ConvertNodeToLibcall() to choose finite libcalls.

There was a bug about determining the availability of the finite calls that should be fixed with:
rL322010

Not in this patch:
This doesn't resolve the question/bug of clang creating the intrinsic IR in the first place.
There's likely follow-up work needed to support the long double variants better.
There's room for improvement to reduce the code duplication.
Create finite calls that don't originate from a corresponding intrinsic or DAG node?

Differential Revision: https://reviews.llvm.org/D41338

llvm-svn: 322087
2018-01-09 15:41:00 +00:00
Francis Visoiu Mistrih 2b3bd30637 [CodeGen] Don't print register classes in -debug output
Since register classes and banks are already printed with the register
definition, don't print it at the end of every instruction anymore.

This follows MIR in this regard and is another step to the unification
of the two formats.

llvm-svn: 322086
2018-01-09 15:39:44 +00:00
Nirav Dave 30304a3bd7 [DAG] Elide overlapping stores
Relanding after fixing handling of pre-indexed memory operations in
BaseIndexOffset analysis (r322003).

Extend overlapping store elision to handle overwrites of stores by
larger stores.

Reviewers: craig.topper, rnk, t.p.northover

Subscribers: javed.absar, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D40969

llvm-svn: 322085
2018-01-09 15:23:12 +00:00
Eric Liu 5732c0e6ea [clangd] Use ToolExecutor to write the global-symbol-builder tool.
Summary:
This enables more execution modes like standalone and Mapreduce-style execution.

See also D41729

Reviewers: hokein, sammccall

Subscribers: klimek, ilya-biryukov, cfe-commits

Differential Revision: https://reviews.llvm.org/D41730

llvm-svn: 322084
2018-01-09 15:21:45 +00:00
Petar Jovanovic 1d26c7e4ff [EarlyCSE] Salvage debug info during DCE
EarlyCSE did not try to salvage debug info during erasing of instructions.
This change fixes it.

Patch by Djordje Todorovic.

Differential Revision: https://reviews.llvm.org/D41496

llvm-svn: 322083
2018-01-09 15:08:37 +00:00
Alexander Kornienko bb3c2432fa Explicitly specify output file.
Otherwise the test fails when LLVM sources are on a read-only partition.

llvm-svn: 322082
2018-01-09 15:05:13 +00:00
Michal Gorny c5e0b63e56 [test] Fix tests to use more portable LLVM_ENABLE_ZLIB
The HAVE_LIBZ variable is not exported by LLVM, and therefore is not
available in stand-alone builds of other tools. Use LLVM_ENABLE_ZLIB
which is the name under which the effective value is exported.

Additional, use llvm_canonicalize_cmake_booleans() to make sure that
a correct (Python-safe) boolean value is passed down to lit.

Differential Revision: https://reviews.llvm.org/D41725

llvm-svn: 322081
2018-01-09 14:44:04 +00:00
Ilya Biryukov f6e2b4cb4b [clangd] Fix a bug in asynchronous code completion
A StringRef that goes out of scope was copied and used in a handler
running on a separate thread.
We didn't catch it because clangd does not use the async completion
API yet.

llvm-svn: 322080
2018-01-09 14:39:27 +00:00
Aleksei Sidorin 47dbaf6c8e [ASTImporter] Fix missing SourceLoc import for ObjCMethodDecl selectors
Patch by Nico Rieck, test case by Sean Callanan!

Differential Revision: https://reviews.llvm.org/D6550

llvm-svn: 322079
2018-01-09 14:25:05 +00:00
Simon Pilgrim 5d909be91b [InstCombine] Check for out of range ashr values using APInt before calling getZExtValue
Reduced from oss-fuzz #5032 test case

llvm-svn: 322078
2018-01-09 14:23:46 +00:00
Sander de Smalen 6595603187 Reverted r322073 because of AddressSanitizer failure on
sanitizer-x86_64-linux-fast builder.

llvm-svn: 322077
2018-01-09 13:51:09 +00:00
Simon Pilgrim 9cf3e765d8 [X86][AVX] Add v2i64/v2f64 load tests
Ensure these use insertions, not masked load ops

llvm-svn: 322076
2018-01-09 13:35:18 +00:00
Pavel Labath 03ed2249a6 TestConflictingSymbols: simplify test by using run_break_set_by_source_regexp
follow-up to r321271 based on post-commit feedback by Jim Ingham.

llvm-svn: 322075
2018-01-09 13:22:22 +00:00
Aaron Ballman a503855906 Track in the AST whether the operand to a UnaryOperator can overflow and then use that logic when evaluating constant expressions and emitting codegen.
llvm-svn: 322074
2018-01-09 13:07:03 +00:00
Sander de Smalen 1f97363e5f [AArch64][SVE] Asm: Add predicated ADD/SUB instructions
Summary:
Add the predicated ADD/SUB instructions and corresponding tests.

Patch [3/3] in a series to add predicated ADD/SUB instructions for SVE.

Reviewers: rengolin, mcrosier, evandro, fhahn, echristo

Reviewed By: fhahn

Subscribers: aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D41443

llvm-svn: 322073
2018-01-09 12:43:46 +00:00
Simon Pilgrim 94357afd26 [InstCombine] Add pow2 mul -> shl tests for vectors with uniform/non-uniform constants
llvm-svn: 322072
2018-01-09 11:55:27 +00:00
Francis Visoiu Mistrih dbf2c48fc7 [MIR] Add support for the frame-destroy MachineInstr flag
We are printing / parsing the `frame-setup` MachineInstr flag but not
the `frame-destroy` one.

Differential Revision: https://reviews.llvm.org/D41509

llvm-svn: 322071
2018-01-09 11:33:22 +00:00
Sander de Smalen 7868e74033 [AArch64][SVE] Asm: Add parsing of merging/zeroing suffix for SVE predicate vector operands
Summary:
Parsing of the '/m' (merging) or '/z' (zeroing) suffix of a predicate operand.

Patch [2/3] in a series to add predicated ADD/SUB instructions for SVE.

Reviewers: rengolin, mcrosier, evandro, fhahn, echristo, MatzeB, t.p.northover

Reviewed By: fhahn

Subscribers: t.p.northover, MatzeB, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D41442

llvm-svn: 322070
2018-01-09 11:17:06 +00:00
Nikolai Bozhenov eededdade9 [Nios2] Arithmetic instructions for R1 and R2 ISA.
Summary:
This commit enables some of the arithmetic instructions for Nios2 ISA (for both
R1 and R2 revisions), implements facilities required to emit those instructions
and provides LIT tests for added instructions.

Reviewed By: hfinkel

Differential Revision: https://reviews.llvm.org/D41236

Author: belickim <mateusz.belicki@intel.com>
llvm-svn: 322069
2018-01-09 11:15:08 +00:00
Paul Osmialowski 6db41e608f Fix type mismatch in omp_control_tool() implementation that makes it run incorrectly on 32-bit machines.
Differential Revision: https://reviews.llvm.org/D41854

llvm-svn: 322068
2018-01-09 10:54:06 +00:00
Haojian Wu fe22b7474b [clangd] Catch more symbols in SymbolCollector.
Summary:
We currently only collect external-linkage symbols in the collector,
which results in missing some typical symbols (like no-linkage type alias symbols).

This patch relaxes the constraint a bit to allow collecting more symbols.

Reviewers: ilya-biryukov

Reviewed By: ilya-biryukov

Subscribers: klimek, cfe-commits

Differential Revision: https://reviews.llvm.org/D41759

llvm-svn: 322067
2018-01-09 10:44:09 +00:00
Igor Kudrin 5e9da2d06b [ELF] Add a comment for ARMExidxSentinelSection::Highest; Use "= nullptr" instead of "= 0". NFC.
Differential Revision: https://reviews.llvm.org/D41234

llvm-svn: 322066
2018-01-09 09:44:27 +00:00
Sam McCall 94af5214a7 Avoid assumption that lit tests are writable (in a couple more places). NFC
llvm-svn: 322065
2018-01-09 09:32:53 +00:00
Ed Schouten c94f3eb0cf ananas: Add shared library support
The Ananas Operating System (https://github.com/zhmu/ananas) has shared
library support as of commit 57739c0b6ece56dd4872aedf30264ed4b9412c77.

This change adds the necessary settings to clang so that shared
executables and libraries can be build correctly.

Submitted by:	Rink Springer
Differential Revision:	https://reviews.llvm.org/D41500

llvm-svn: 322064
2018-01-09 09:18:14 +00:00
Oren Ben Simhon 57cc1a5d77 Added Control Flow Protection Flag
Cf-protection is a target independent flag that instructs the back-end to instrument control flow mechanisms like: Branch, Return, etc.
For example in X86 this flag will be used to instrument Indirect Branch Tracking instructions.

Differential Revision: https://reviews.llvm.org/D40478

Change-Id: I5126e766c0e6b84118cae0ee8a20fe78cc373dea
llvm-svn: 322063
2018-01-09 08:53:59 +00:00
Oren Ben Simhon 1c6308ecd5 Instrument Control Flow For Indirect Branch Tracking
CET (Control-Flow Enforcement Technology) introduces a new mechanism called IBT (Indirect Branch Tracking).
According to IBT, each Indirect branch should land on dedicated ENDBR instruction (End Branch).
The new pass adds ENDBR instructions for every indirect jmp/call (including jumps using jump tables / switches).
For more information, please see the following:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

Differential Revision: https://reviews.llvm.org/D40482

Change-Id: Icb754489faf483a95248f96982a4e8b1009eb709
llvm-svn: 322062
2018-01-09 08:51:18 +00:00
Shoaib Meenai 1295088fba [cmake] Use symlinks for Windows-hosted toolchains built on Unix
When cross-compiling for Windows on Unix, the built toolchain will need
to be transferred to Windows to actually run. My opinion is that the
Unix build should use symlinks, and the transfer to Windows should take
care of making those symlinks usable. E.g., I envision tarballs to be a
common form of transfer from Unix to Windows, in which case the tarball
can be created using --dereference to follow the symlinks.

The motivation here is that, when cross-compiling for Windows on Unix,
the installation will *already* create symlinks. The reason is that the
installation script will be invoked without knowing the host system, so
the `if(UNIX)` check in the installation symlink creation script will
reflect the build system rather than the host system. We could either
make the build and install trees both contain copies or both contain
symlinks, and using symlinks is a significant space saving without (in
my opinion) having any detrimental effect on the usage of the cross-
compiled toolchain on Windows.

A secondary motivation is that Windows 10 version 1703 and later finally
lift the administrator rights requirement for creating symbolic links
(if the system is in Developer Mode), which makes symlinks a lot more
practical even on Windows. Of course Unix and Windows symlinks aren't
interoperable, but symlinks for Windows toolchains is a reasonable
future direction to be going in anyway.

Differential Revision: https://reviews.llvm.org/D41314

llvm-svn: 322061
2018-01-09 07:50:18 +00:00
Craig Topper def1c30c66 [X86] Allow more cmpps/pd immediate encodings to be commuted during isel.
The code that checks the immediate wasn't masking to the lower 3-bits like the code in X86InstrInfo.cpp that's used by the peephole pass does.

llvm-svn: 322060
2018-01-09 07:09:34 +00:00
Serguei Katkov 6a7a4c6a55 [SCEV] Do not cache S -> V if S is not equivalent of V
SCEV tracks the correspondence of created SCEV to original instruction.
However during creation of SCEV it is possible that nuw/nsw/exact flags are
lost.

As a result during expansion of the SCEV the instruction with nuw/nsw/exact
will be used where it was expected and we produce poison incorreclty.

Reviewers: sanjoy, mkazantsev, sebpop, jbhateja
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41578

llvm-svn: 322058
2018-01-09 06:47:14 +00:00
Easwaran Raman bfa48a14ab [ELF] Explicit template instantiations for addFile
Summary:
All other templated methods have explicit instantiations but this one is
missing. Discovered while building with a clang with inliner
modifications.

Reviewers: espindola

Subscribers: emaste, llvm-commits, davidxl

Differential Revision: https://reviews.llvm.org/D41847

llvm-svn: 322057
2018-01-09 05:35:29 +00:00
Serguei Katkov 4d1dd6b53a [CGP] Fix Complex addressing mode for offset
If the offset is differ in two addressing mode we can continue only if
ScaleReg is not set due to we will use it as merge of different offsets.

It should fix PR35799 and PR35805.

Reviewers: john.brawn, reames
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41227

llvm-svn: 322056
2018-01-09 04:37:06 +00:00
Sean Fertile 33a17762bb [PowerPC] Can not assume an intrinsic argument is a simple type.
The CTRLoop pass performs checks on the argument of certain libcalls/intrinsics,
and assumes the arguments must be of a simple type. This isn't always the case
though. For example if we unroll and vectorize a loop we may end up with vectors
larger then the largest legal type, along with intrinsics that operate on those
wider types. This happened in the ffmpeg build, where we unrolled a loop and
ended up with a sqrt intrinsic that operated on V16f64, triggering an assertion.

Differential Revision: https://reviews.llvm.org/D41758

llvm-svn: 322055
2018-01-09 03:03:41 +00:00
Jim Ingham 9c7ba8e047 Cut and paste error - I wasn't actually running both tests...
llvm-svn: 322054
2018-01-09 03:03:20 +00:00
Eric Christopher c44717774a Remove unused function HvxSelector::zerous.
llvm-svn: 322053
2018-01-09 02:38:17 +00:00
Erich Keane bc40c5c68f Fix use-after-free found by address-san on -r322028.
r322028 attempted to remove something from the "Manglings"
list when it was no longer valid, and did so with 'erase'.

However, StringRefs to these were stored, so these became
dangling references.  This patch changes to using 'remove' instead
of 'erase' to keep the strings valid.

llvm-svn: 322052
2018-01-09 01:09:12 +00:00
Stefan Pintilie 7e10987b12 Revert "[PowerPC] Manually schedule the prologue and epilogue"
[PowerPC] This reverts commit r322036.

Failing build bots. Revert the commit now.

llvm-svn: 322051
2018-01-09 01:06:21 +00:00
Craig Topper cc342d465e [X86] Remove llvm.x86.avx512.cvt*2mask.* intrinsics and autoupgrade to (icmp slt X, 0)
I had to drop fast-isel-abort from a test because we can't fast isel some of the mask stuff. When we used intrinsics we implicitly fell back to SelectionDAG for the intrinsic call without triggering the abort error. But with native IR that doesn't happen the same way.

llvm-svn: 322050
2018-01-09 00:50:47 +00:00