Commit Graph

67401 Commits

Author SHA1 Message Date
Benjamin Kramer 9c794c7a7c [C++11] Remove a leftover std::function instance.
It's not needed anymore.

llvm-svn: 202748
2014-03-03 19:49:02 +00:00
Chandler Carruth d031fe9fcf [C++11] Remove the completely unnecessary requirement on SetVector's
remove_if that its predicate is adaptable. We don't actually need this,
we can write a generic adapter for any predicate.

This lets us remove some very wrong std::function usages. We should
never be using std::function for predicates to algorithms. This incurs
an *indirect* call overhead for every evaluation of the predicate, and
makes it very hard to inline through.

llvm-svn: 202742
2014-03-03 19:28:52 +00:00
Diego Novillo 282450d94c Add DWARF discriminator support to DILexicalBlocks.
This adds support for emitting discriminators from DILexicalBlocks.

llvm-svn: 202736
2014-03-03 18:53:17 +00:00
Lang Hames 1863582863 Re-apply r202551, which introduced new PBQP solver.
llvm-svn: 202735
2014-03-03 18:50:05 +00:00
Benjamin Kramer 17388a61b2 Revert "[C++11] Replace LLVM atomics with std::atomic."
Breaks the MSVC build.
DataStream.cpp(44): error C2552: 'llvm::Statistic::Value' : non-aggregates cannot be initialized with initializer list

llvm-svn: 202731
2014-03-03 18:02:34 +00:00
Benjamin Kramer 0b6eb591a4 [C++11] Replace LLVM atomics with std::atomic.
With C++11 we finally have a standardized way to specify atomic operations. Use
them to replace the existing custom implemention. Sadly the translation is not
entirely trivial as std::atomic allows more fine-grained control over the
atomicity. I tried to preserve the old semantics as well as possible.

Differential Revision: http://llvm-reviews.chandlerc.com/D2915

llvm-svn: 202730
2014-03-03 17:53:30 +00:00
Daniel Sanders fa961d76f0 [mips] Prevent %lo relocation being used on MSA loads and stores.
Summary:
Parts of the compiler still believed MSA load/stores have a 16-bit offset when
it is actually 10-bit. Corrected this, and fixed a closely related issue this
uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS
respectively) could not load/store using offsets from the stack/frame pointer.
They accepted frameindex+offset, but not frameindex by itself.

Reviewers: jacksprat, matheusalmeida

Reviewed By: jacksprat

Differential Revision: http://llvm-reviews.chandlerc.com/D2888

llvm-svn: 202717
2014-03-03 14:31:21 +00:00
Ed Maste 2a710d0a5b [mips] support FK_Data_2 and FK_Data_8 to fix big-endian debug data
This fixes invalid lengths in .debug_aranges on big-endian mips64
(lengths appear to be left-shifted by 32 bits) and in .debug_loc.

Differential Revision: http://llvm-reviews.chandlerc.com/D2517

llvm-svn: 202716
2014-03-03 14:27:49 +00:00
Vladimir Medic f9f8f4859a Fixing a build failure reported by certain buildbots. This will disable jalx instruction for micromips target.
llvm-svn: 202715
2014-03-03 14:05:14 +00:00
Evgeniy Stepanov 77be532f71 [msan] Handle X86 SIMD bitshift intrinsics.
llvm-svn: 202712
2014-03-03 13:47:42 +00:00
Vladimir Medic 43e978234a This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.
llvm-svn: 202706
2014-03-03 13:12:59 +00:00
Tobias Grosser 4abf9d3a54 [C++11] Add a basic block range view for RegionInfo
This also switches the users in LLVM to ensure this functionality is tested.

llvm-svn: 202705
2014-03-03 13:00:39 +00:00
Chandler Carruth 1583e99c23 [C++11] Add two range adaptor views to User: operands and
operand_values. The first provides a range view over operand Use
objects, and the second provides a range view over the Value*s being
used by those operands.

The naming is "STL-style" rather than "LLVM-style" because we have
historically named iterator methods STL-style, and range methods seem to
have far more in common with their iterator counterparts than with
"normal" APIs. Feel free to bikeshed on this one if you want, I'm happy
to change these around if people feel strongly.

I've switched code in SROA and LCG to exercise these mostly to ensure
they work correctly -- we don't really have an easy way to unittest this
and they're trivial.

llvm-svn: 202687
2014-03-03 10:42:58 +00:00
Venkatraman Govindaraju 925ec9b11e [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend.
llvm-svn: 202670
2014-03-02 23:39:07 +00:00
Venkatraman Govindaraju 07d3af2821 [Sparc] Add return/rett instruction to Sparc backend.
llvm-svn: 202666
2014-03-02 22:55:53 +00:00
Venkatraman Govindaraju 4fa2ab26f5 [Sparc] Add support for decoding jmpl/retl/ret instruction.
llvm-svn: 202663
2014-03-02 21:17:44 +00:00
Venkatraman Govindaraju c3084ad294 [Sparc] Add fcmpe* instructions to Sparc backend.
llvm-svn: 202661
2014-03-02 19:56:19 +00:00
Venkatraman Govindaraju f9a202a9ac [Sparc] Add VIS instructions to sparc backend.
llvm-svn: 202660
2014-03-02 19:31:21 +00:00
Hal Finkel 6aca2373f2 Add a PPC inline asm constraint type for single CR bits
Now that the PowerPC backend can track individual CR bits as first-class
registers, we should also have a way of allocating them for inline asm
statements. Because these registers are only one bit, if an output variable is
implicitly cast to a larger integer size, we'll get an any_extend to that
larger type (this is part of the existing target-independent logic). As a
result, regardless of the size of the output type, only the first bit is
meaningful.

The constraint identifier "wc" has been chosen for this purpose. Although gcc
does not currently support allocating individual CR bits, this identifier
choice has been coordinated with the gcc PowerPC team, and will be marked as
reserved for this purpose in the gcc constraints.md file.

llvm-svn: 202657
2014-03-02 18:23:39 +00:00
Benjamin Kramer d6f1f84f51 [C++11] Replace llvm::tie with std::tie.
The old implementation is no longer needed in C++11.

llvm-svn: 202644
2014-03-02 13:30:33 +00:00
Chandler Carruth cf01800b1f [C++11] Replace LLVM_STATIC_ASSERT with static_assert, we now have
access to it on all host toolchains.

llvm-svn: 202642
2014-03-02 13:10:45 +00:00
Benjamin Kramer b6d0bd48bd [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.
Remove the old functions.

llvm-svn: 202636
2014-03-02 12:27:27 +00:00
Venkatraman Govindaraju b745e67a64 [SparcV9] Adds support for branch on integer register instructions (BPr) and conditional moves on integer register (MOVr/FMOVr).
llvm-svn: 202628
2014-03-02 09:46:56 +00:00
Elena Demikhovsky 9737e3886b AVX-512: Fixed extract_vector_elt for v8i1 vector
llvm-svn: 202624
2014-03-02 09:19:44 +00:00
Craig Topper 73156025e0 Switch all uses of LLVM_OVERRIDE to just use 'override' directly.
llvm-svn: 202621
2014-03-02 09:09:27 +00:00
Craig Topper 77dfe45f81 Switch all uses of LLVM_FINAL to just use 'final', and remove the macro.
llvm-svn: 202618
2014-03-02 08:08:51 +00:00
Venkatraman Govindaraju 600f390bb9 [Sparc] Add support for parsing branches and conditional move instructions with %fcc1-%fcc3 conditional registers.
llvm-svn: 202616
2014-03-02 06:28:15 +00:00
Venkatraman Govindaraju 293a81c406 [Sparc] Make floating point branch instruction formats to accept %fcc0-%fcc1 conditional registers as input.
No functionality change.

llvm-svn: 202614
2014-03-02 04:43:45 +00:00
Chandler Carruth 002da5db29 [C++11] Switch all uses of the llvm_move macro to use std::move
directly, and remove the macro.

llvm-svn: 202612
2014-03-02 04:08:41 +00:00
Venkatraman Govindaraju 81aae57282 [Sparc] Add support for parsing fcmp with %fcc registers.
llvm-svn: 202610
2014-03-02 03:39:39 +00:00
Alp Toker 61007d8ee0 [C++11] Expand and eliminate the LLVM_ENUM_INT_TYPE() macro
llvm-svn: 202607
2014-03-02 03:20:38 +00:00
Venkatraman Govindaraju bac285f588 [Sparc] Add register class for floating point conditional flags (%fcc0 - %fcc3).
llvm-svn: 202604
2014-03-02 02:12:33 +00:00
Venkatraman Govindaraju c86e0f3873 [SparcV9] Add support for parsing branch instructions with prediction.
llvm-svn: 202602
2014-03-01 22:03:07 +00:00
Hal Finkel 46043edc56 Remove extra truncs/exts around i32 bit operations on PPC64
This generalizes the code to eliminate extra truncs/exts around i1 bit
operations to also do the same on PPC64 for i32 bit operations. This eliminates
a fairly prevalent code wart:

int foo(int a) {
  return a == 5 ? 7 : 8;
}

On PPC64, because of the extension implied by the ABI, this would generate:

	cmplwi 0, 3, 5
	li 12, 8
	li 4, 7
	isel 3, 4, 12, 2
	rldicl 3, 3, 0, 32
	blr

where the 'rldicl 3, 3, 0, 32', the extension, is completely unnecessary. At
least for the single-BB case (which is all that the DAG combine mechanism can
handle), this unnecessary extension is no longer generated.

llvm-svn: 202600
2014-03-01 21:36:57 +00:00
Venkatraman Govindaraju 2286874119 [Sparc] Add support for parsing annulled branch instructions.
llvm-svn: 202599
2014-03-01 20:08:48 +00:00
Venkatraman Govindaraju e0c5bff720 [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc.
llvm-svn: 202598
2014-03-01 18:54:52 +00:00
Venkatraman Govindaraju 2a9c430677 [Sparc] Add missing ALU instruction patterns.
llvm-svn: 202597
2014-03-01 17:51:00 +00:00
Benjamin Kramer 573ff3620c Make helper function static.
llvm-svn: 202596
2014-03-01 17:24:40 +00:00
Benjamin Kramer 3a377bce4e Now that we have C++11, turn simple functors into lambdas and remove a ton of boilerplate.
No intended functionality change.

llvm-svn: 202588
2014-03-01 11:47:00 +00:00
Chandler Carruth 172f7c37b9 [C++11] Remove the use of LLVM_HAS_RVALUE_REFERENCES from the rest of
the core LLVM libraries.

llvm-svn: 202582
2014-03-01 09:32:03 +00:00
Venkatraman Govindaraju 256735d485 [Sparc] Add support to decode unimp instruction.
llvm-svn: 202581
2014-03-01 09:28:18 +00:00
Chandler Carruth 1bf3847766 [C++11] Remove the R-value reference #if usage from the ADT and Support
libraries. It is now always 1 in LLVM builds.

llvm-svn: 202580
2014-03-01 09:27:28 +00:00
Venkatraman Govindaraju 484ca1a030 [Sparc] Add support to decode negative simm13 operands in the sparc disassembler.
llvm-svn: 202578
2014-03-01 09:11:57 +00:00
Venkatraman Govindaraju 78df2dec0c [Sparc] Add support for decoding call instructions in the sparc disassembler.
llvm-svn: 202577
2014-03-01 08:30:58 +00:00
Venkatraman Govindaraju fb54821398 [Sparc] Add support to disassemble sparc memory instructions.
llvm-svn: 202575
2014-03-01 07:46:33 +00:00
Venkatraman Govindaraju bf70566a45 Add support for parsing sun-style section flags in ELFAsmParser.
llvm-svn: 202573
2014-03-01 06:21:00 +00:00
Venkatraman Govindaraju 2b1682bcd4 [Sparc] Implement writeNopData. Emit actual NOP instruction instead of just filling with zeroes.
llvm-svn: 202572
2014-03-01 05:45:09 +00:00
Venkatraman Govindaraju 9fc29098df [Sparc] Teach SparcAsmParser to emit correct relocations for PIC code.
llvm-svn: 202571
2014-03-01 05:07:21 +00:00
Mark Seaborn 552d9e49d9 Fix RWMutex to be thread-safe when pthread_rwlock is not available
lib/Support/RWMutex.cpp contains an implementation of RWMutex that
uses pthread_rwlock, but when pthread_rwlock is not available (such as
under NaCl, when using newlib), it silently falls back to using the
no-op definition in lib/Support/Unix/RWMutex.inc, which is not
thread-safe.

Fix this case to be thread-safe by using a normal mutex.

Differential Revision: http://llvm-reviews.chandlerc.com/D2892

llvm-svn: 202570
2014-03-01 04:30:32 +00:00
Venkatraman Govindaraju 3b6b0e42f0 [Sparc] 80 column rule. No functionality change.
llvm-svn: 202565
2014-03-01 02:28:34 +00:00