Commit Graph

571 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen 813a109fa5 Don't move normal loads across volatile/atomic loads.
It is technically allowed to move a normal load across a volatile load,
but probably not a good idea.

It is not allowed to move a load across an atomic load with
Ordering > Monotonic, and we model those with MOVolatile as well.

I recently removed the mayStore flag from atomic load instructions, so
they don't need a pseudo-opcode. This patch makes up for the difference.

llvm-svn: 162857
2012-08-29 20:48:45 +00:00
Jakob Stoklund Olesen 2b16664522 Maintain a vaild isTied bit as operands are added and removed.
The isTied bit is set automatically when a tied use is added and
MCInstrDesc indicates a tied operand. The tie is broken when one of the
tied operands is removed.

llvm-svn: 162814
2012-08-29 00:37:58 +00:00
Jakob Stoklund Olesen e56c60c5eb Add a MachineOperand::isTied() flag.
While in SSA form, a MachineInstr can have pairs of tied defs and uses.
The tied operands are used to represent read-modify-write operands that
must be assigned the same physical register.

Previously, tied operand pairs were computed from fixed MCInstrDesc
fields, or by using black magic on inline assembly instructions.

The isTied flag makes it possible to add tied operands to any
instruction while getting rid of (some of) the inlineasm magic.

Tied operands on normal instructions are needed to represent predicated
individual instructions in SSA form. An extra <tied,imp-use> operand is
required to represent the output value when the instruction predicate is
false.

Adding a predicate to:

  %vreg0<def> = ADD %vreg1, %vreg2

Will look like:

  %vreg0<tied,def> = ADD %vreg1, %vreg2, pred:3, %vreg7<tied,imp-use>

The virtual register %vreg7 is the value given to %vreg0 when the
predicate is false. It will be assigned the same physreg as %vreg0.

This commit adds the isTied flag and sets it based on MCInstrDesc when
building an instruction. The flag is not used for anything yet.

llvm-svn: 162774
2012-08-28 18:34:41 +00:00
Jakob Stoklund Olesen dba99d0dfa Don't allow TargetFlags on MO_Register MachineOperands.
Register operands are manipulated by a lot of target-independent code,
and it is not always possible to preserve target flags. That means it is
not safe to use target flags on register operands.

None of the targets in the tree are using register operand target flags.
External targets should be using immediate operands to annotate
instructions with operand modifiers.

llvm-svn: 162770
2012-08-28 18:05:48 +00:00
Jakob Stoklund Olesen ae7b9711b1 Also update MRI use lists when changing a use to a def and vice versa.
This was the cause of the buildbot failures.

llvm-svn: 161643
2012-08-10 00:21:26 +00:00
Jakob Stoklund Olesen c4102d4902 Move use list management into MachineRegisterInfo.
Register MachineOperands are kept in linked lists accessible via MRI's
reg_iterator interfaces. The linked list management was handled partly
by MachineOperand methods, partly by MRI methods.

Move all of the list management into MRI, delete
MO::AddRegOperandToRegInfo() and MO::RemoveRegOperandFromRegInfo().

Be more explicit about handling the cases where an MRI pointer isn't
available.

llvm-svn: 161632
2012-08-09 22:49:37 +00:00
Jakob Stoklund Olesen 84689b0d5a Add a new kind of MachineOperand: MO_TargetIndex.
A target index operand looks a lot like a constant pool reference, but
it is completely target-defined. It contains the 8-bit TargetFlags, a
32-bit index, and a 64-bit offset. It is preserved by all code generator
passes.

TargetIndex operands can be used to carry target-specific information in
cases where immediate operands won't suffice.

llvm-svn: 161441
2012-08-07 18:56:39 +00:00
Chandler Carruth 264854f9a0 Finish fixing the MachineOperand hashing, providing a nice modern
hash_value overload for MachineOperands. This addresses a FIXME
sufficient for me to remove it, and cleans up the code nicely too.

The important changes to the hashing logic:
- TargetFlags are now included in all of the hashes. These were complete
  missed.
- Register operands have their subregisters and whether they are a def
  included in the hash.
- We now actually hash all of the operand types. Previously, many
  operand types were simply *dropped on the floor*. For example:
  - Floating point immediates
  - Large integer immediates (>64-bit)
  - External globals!
  - Register masks
  - Metadata operands
- It removes the offset from the block-address hash; I'm a bit
  suspicious of this, but isIdenticalTo doesn't consider the offset for
  black addresses.

Any patterns involving these entities could have triggered extreme
slowdowns in MachineCSE or PHIElimination. Let me know if there are PRs
you think might be closed now... I'm looking myself, but I may miss
them.

llvm-svn: 159743
2012-07-05 11:06:22 +00:00
Chandler Carruth 1d5d23106e The hash function for MI expressions, used by MachineCSE, is really
broken. This patch fixes the superficial problems which lead to the
intractably slow compile times reported in PR13225.

The specific issue is that we were failing to include the *offset* of
a global variable in the hash code. Oops. This would in turn cause all
MIs which were only distinguishable due to operating on different
offsets of a global variable to produce identical hash functions. In
some of the test cases attached to the PR I saw hash table activity
where there were O(1000) probes-per-lookup *on average*. A very few
entries were responsible for most of these probes.

There is still quite a bit more to do here. The ad-hoc layering of data
in MachineOperands makes them *extremely* brittle to hash correctly.
We're missing quite a few other cases, the only ones I've fixed here are
the specific MO types which were allowed through the assert() in
getOffset().

llvm-svn: 159741
2012-07-05 10:03:57 +00:00
Jakob Stoklund Olesen c300ef0e50 Allow trailing physreg RegisterSDNode operands on non-variadic instructions.
Also allow trailing register mask operands on non-variadic both
MachineSDNodes and MachineInstrs.

The extra physreg RegisterSDNode operands are added to the MI as
<imp-use> operands. This makes it possible to have non-variadic call
instructions.

Call and return instructions really are non-variadic, the argument
registers should only be used implicitly - they are not part of the
encoding.

llvm-svn: 159727
2012-07-04 23:53:23 +00:00
Bill Wendling e38859dc8e Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and
include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h.

The reasoning is because the DebugInfo module is simply an interface to the
debug info MDNodes and has nothing to do with analysis.

llvm-svn: 159312
2012-06-28 00:05:13 +00:00
Andrew Trick 4b037005d2 MachineInstr::eraseFromParent fix for removing bundled instrs.
Patch by Ivan Llopard.

llvm-svn: 158025
2012-06-05 21:44:23 +00:00
Jakob Stoklund Olesen 54038d796c Switch all register list clients to the new MC*Iterator interface.
No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

llvm-svn: 157854
2012-06-01 23:28:30 +00:00
Jakob Stoklund Olesen 3a48c06456 Remove some redundant tests.
An empty list is not represented as a null pointer. Let TRI do its own
shortcuts.

llvm-svn: 157702
2012-05-30 18:38:56 +00:00
Jakob Stoklund Olesen 3c52f0281f Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

llvm-svn: 156328
2012-05-07 22:10:26 +00:00
Jakob Stoklund Olesen e89496fe63 Remove extra comma in debug output.
llvm-svn: 156219
2012-05-04 22:53:26 +00:00
Jakob Stoklund Olesen 7111a630d5 Print <def,read-undef> to avoid confusion.
The <undef> flag on a def operand only applies to partial register
redefinitions. Only print the flag when relevant, and print it as
<def,read-undef> to make it clearer what it means.

llvm-svn: 155239
2012-04-20 21:45:33 +00:00
Rafael Espindola 80c540e656 Teach CodeGen's version of computeMaskedBits to understand the range metadata.
This is the CodeGen equivalent of r153747. I tested that there is not noticeable
performance difference with any combination of -O0/-O2 /-g when compiling
gcc as a single compilation unit.

llvm-svn: 153817
2012-03-31 18:14:00 +00:00
Benjamin Kramer 97f889f43b MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty.
This is particularly helpful as both arguments tend to be constants.

llvm-svn: 152991
2012-03-17 17:03:45 +00:00
Benjamin Kramer d03878bdf2 Limit the number of memory operands in MachineInstr to 2^16 and store the number in padding.
Saves one machine word on MachineInstr (88->80 bytes on x86_64, 48->44 on i386).

llvm-svn: 152930
2012-03-16 16:39:27 +00:00
Craig Topper 5a4bcc749a Use uint16_t to store instruction implicit uses and defs. Reduces static data.
llvm-svn: 152301
2012-03-08 08:22:45 +00:00
Chandler Carruth 636ee38a88 Try to clarify this comment some.
llvm-svn: 152221
2012-03-07 10:13:40 +00:00
Chandler Carruth 962152ca7a Remove another outbreak of customized (and completely broken) hashing.
This one is particularly annoying because the hashing algorithm is
highly specialized, with a strange "equivalence" definition that subsets
the fields involved.

Still, this looks at the exact same set of data as the old code, but
without bitwise or-ing over parts of it and other mixing badness. No
functionality changed here. I've left a substantial fixme about the fact
that there is a cleaner and more principled way to do this, but it
requires making the equality definition actual stable for particular
types...

llvm-svn: 152218
2012-03-07 09:39:46 +00:00
Craig Topper 1d32658877 Use uint16_t to store register overlaps to reduce static data.
llvm-svn: 152001
2012-03-04 10:43:23 +00:00
Jakob Stoklund Olesen d256c21666 Move getBundleStart() into MachineInstrBundle.h.
This allows the function to be inlined, and makes it suitable for use in
getInstructionIndex().

Also provide a const version. C++ is great for touch typing practice.

llvm-svn: 151782
2012-03-01 01:26:01 +00:00
Lang Hames 3eedcce906 Reverse iterator - should be incrementing rather than decrementing.
llvm-svn: 150778
2012-02-17 01:54:11 +00:00
Lang Hames 923d199a67 Make LiveIntervals::handleMove() bundle aware.
llvm-svn: 150630
2012-02-15 23:21:33 +00:00
Jakob Stoklund Olesen e7d3f441b5 Handle regmasks in findRegisterDefOperandIdx().
Only accept register masks when looking for an 'overlapping' def. When
Overlap is not set, the function searches for a proper definition of
Reg.

This means MI->modifiesRegister() considers register masks, but
MI->definesRegister() doesn't.

llvm-svn: 150529
2012-02-14 23:49:37 +00:00
Benjamin Kramer bf152d57a4 Put instruction names into an indexed string table on the side, removing a pointer from MCInstrDesc.
Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't
have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64.

llvm-svn: 150245
2012-02-10 13:18:44 +00:00
Andrew Trick 3bc0e0c651 Added MachineInstr::isBundled() to check if an instruction is part of a bundle.
llvm-svn: 150044
2012-02-08 02:17:25 +00:00
Jakob Stoklund Olesen 56fe2ed51e Handle register mask operands in setPhysRegsDeadExcept().
Calls that use register mask operands don't have implicit defs for
returned values.  The register mask operand handles the call clobber,
but it always behaves like a set of dead defs.

Add live implicit defs for any implicitly defined physregs that are
actually used.

llvm-svn: 149715
2012-02-03 21:23:14 +00:00
Jakob Stoklund Olesen 4290be4386 ArrayRef'ize MI::setPhysRegsDeadExcept().
llvm-svn: 149709
2012-02-03 20:43:39 +00:00
Jakob Stoklund Olesen f650732cab Handle all live physreg defs in the same place.
SelectionDAG has 4 different ways of passing physreg defs to users.
Collect all of the uses at the same time, and pass all of them to
MI->setPhysRegsDeadExcept() to mark the remaining defs dead.

The setPhysRegsDeadExcept() function will soon add the required
implicit-defs to instructions with register mask operands.

llvm-svn: 149708
2012-02-03 20:43:35 +00:00
Jakob Stoklund Olesen 5e1ac45b93 Require non-NULL register masks.
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

llvm-svn: 149646
2012-02-02 23:52:57 +00:00
Jakob Stoklund Olesen 8c139a5125 Clear kill flags before propagating a copy.
The live range of the source register may be extended when a redundant
copy is eliminated. Make sure any kill flags between the two copies are
cleared.

This fixes PR11765.

llvm-svn: 149069
2012-01-26 17:52:15 +00:00
Jakob Stoklund Olesen 374ed322f2 Add a new kind of MachineOperand: MO_RegisterMask.
Register masks will be used as a compact representation of large clobber
lists.  Currently, an x86 call instruction has some 40 operands
representing call-clobbered registers.  That's more than 1kB of useless
operands per call site.

A register mask operand references a bit mask of call-preserved
registers, everything else is clobbered.  The bit mask will typically
come from TargetRegisterInfo::getCallPreservedMask().

By abandoning ImplicitDefs for call-clobbered registers, it also becomes
possible to share call instruction descriptions between calling
conventions, and we can get rid of the WINCALL* instructions.

This patch introduces the new operand kind.  Future patches will add
RegMask support to target-independent passes before finally the fixed
clobber lists can be removed from call instruction descriptions.

llvm-svn: 148250
2012-01-16 19:22:00 +00:00
Chandler Carruth f3e8502cc1 Add 'llvm_unreachable' to passify GCC's understanding of the constraints
of several newly un-defaulted switches. This also helps optimizers
(including LLVM's) recognize that every case is covered, and we should
assume as much.

llvm-svn: 147861
2012-01-10 18:08:01 +00:00
David Blaikie edbb58c577 Remove unnecessary default cases in switches that cover all enum values.
llvm-svn: 147855
2012-01-10 16:47:17 +00:00
Evan Cheng 7fae11b231 - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
  and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
  prevent IT blocks from being broken apart.

llvm-svn: 146542
2011-12-14 02:11:42 +00:00
Evan Cheng cdf89fdeaf Make MachineInstr instruction property queries more flexible. This change all
clients to decide whether to look inside bundled instructions and whether
the query should return true if any / all bundled instructions have the
queried property.

llvm-svn: 146168
2011-12-08 19:23:10 +00:00
Evan Cheng 7f8e563a69 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Jakob Stoklund Olesen 6ad6848522 Add missing check.
llvm-svn: 146004
2011-12-07 01:08:22 +00:00
Jakob Stoklund Olesen b0d91abec0 Add MachineOperand IsInternalRead flag.
This flag is used when bundling machine instructions.  It indicates
whether the operand reads a value defined inside or outside its bundle.

llvm-svn: 145997
2011-12-07 00:22:07 +00:00
Evan Cheng 2a81dd4a3c First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975
2011-12-06 22:12:01 +00:00
Pete Cooper 82cd9e81fc Added invariant field to the DAG.getLoad method and changed all calls.
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses

llvm-svn: 144100
2011-11-08 18:42:53 +00:00
Pete Cooper 65ba66c660 Reverted r143600 - selector reference change
llvm-svn: 143646
2011-11-03 20:47:50 +00:00
Pete Cooper e6173d81ae Treat objc selector reference globals as invariant so that MachineLICM can hoist them out of loops. Fixes <rdar://problem/6027699>
llvm-svn: 143600
2011-11-03 00:56:36 +00:00
Nick Lewycky 8488225984 Add missing braces to pacify GCC's -Wparentheses.
llvm-svn: 141842
2011-10-13 00:54:59 +00:00
Jakob Stoklund Olesen 35b362fab2 Add MachineInstr::getRegClassConstraint().
Most instructions have some requirements for their register operands.
Usually, this is expressed as register class constraints in the
MCInstrDesc, but for inline assembly the constraints are encoded in the
flag words.

llvm-svn: 141835
2011-10-12 23:37:36 +00:00
Jakob Stoklund Olesen 1e73716eae Extract a method for finding the inline asm flag operand.
llvm-svn: 141834
2011-10-12 23:37:33 +00:00
Jakob Stoklund Olesen 24abd9d9b6 Encode register class constreaints in inline asm instructions.
The inline asm operand constraint is initially encoded in the virtual
register for the operand, but that register class may change during
coalescing, and the original constraint is lost.

Encode the original register class as part of the flag word for each
inline asm operand.  This makes it possible to recover the actual
constraint required by inline asm, just like we can for normal
instructions.

llvm-svn: 141833
2011-10-12 23:37:29 +00:00
Jakob Stoklund Olesen 463b05a2d0 Remove NumImplicitOps which is now unused.
llvm-svn: 140767
2011-09-29 01:47:36 +00:00
Jakob Stoklund Olesen 2318d1e0e9 Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.
The function needs to scan the implicit operands anyway, so no
performance is won by caching the number of implicit operands added to
an instruction.

This also fixes a bug when adding operands after an implicit operand has
been added manually.  The NumImplicitOps count wasn't kept up to date.

MachineInstr::addOperand() will now consistently place all explicit
operands before all the implicit operands, regardless of the order they
are added.  It is possible to change an MI opcode and add additional
explicit operands.  They will be inserted before any existing implicit
operands.

The only exception is inline asm instructions where operands are never
reordered.  This is because of a hack that marks explicit clobber regs
on inline asm as <implicit-def> to please the fast register allocator.
This hack can go away when InstrEmitter and FastIsel can add exact
<dead> flags to physreg defs.

llvm-svn: 140744
2011-09-29 00:40:51 +00:00
Jim Grosbach ed16ec4248 Thumb2 parsing and encoding for IT blocks.
llvm-svn: 138773
2011-08-29 22:24:09 +00:00
Jim Grosbach dee9e8a37c Tidy up. Trailing whitespace.
llvm-svn: 138437
2011-08-24 16:44:17 +00:00
Jakob Stoklund Olesen 9eb77bf615 Don't treat a partial <def,undef> operand as a read.
Normally, a partial register def is treated as reading the
super-register unless it also defines the full register like this:

  %vreg110:sub_32bit<def> = COPY %vreg77:sub_32bit, %vreg110<imp-def>

This patch also uses the <undef> flag on partial defs to recognize
non-reading operands:

  %vreg110:sub_32bit<def,undef> = COPY %vreg77:sub_32bit

This fixes a subtle bug in RegisterCoalescer where LIS->shrinkToUses
would treat a coalesced copy as still reading the register, extending
the live range artificially.

My test case only works when I disable DCE so a dead copy is left for
RegisterCoalescer, so I am not including it.

<rdar://problem/9967101>

llvm-svn: 138018
2011-08-19 00:30:17 +00:00
Devang Patel d61b1d505c Print DBG_VALUE variable's location info as a comment.
llvm-svn: 136916
2011-08-04 20:44:26 +00:00
Devang Patel bf8cc60d1b If known DebugLocs do not match then two DBG_VALUE machine instructions are not identical. For example,
DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ]
        DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ]

These two MIs represent identical value, 3.31...,  for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". 

llvm-svn: 134620
2011-07-07 17:45:33 +00:00
Jakob Stoklund Olesen 25a404eb81 Include a source location when complaining about bad inline assembly.
Add a MI->emitError() method that the backend can use to report errors
related to inline assembly. Call it from X86FloatingPoint.cpp when the
constraints are wrong.

This enables proper clang diagnostics from the backend:

$ clang -c pr30848.c
pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack
  __asm__ ("" : "=u" (d));  /* { dg-error "output regs" } */
           ^
1 error generated.

llvm-svn: 134307
2011-07-02 03:53:34 +00:00
Cameron Zwarich 7da0f9a58e Take a stab at fixing the llvm-x86_64-linux-checks failure.
llvm-svn: 134287
2011-07-01 23:45:21 +00:00
Evan Cheng 6cc775f905 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
2011-06-28 19:10:37 +00:00
Jakob Stoklund Olesen 537a302d1a Distinguish early clobber output operands from clobbered registers.
Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we
now use two different asm operand kinds.

The new Kind_Clobber is treated identically to the old
Kind_RegDefEarlyClobber for now, but x87 floating point stack inline
assembly does care about the difference.

This will pop a register off the stack:

  asm("fstp %st" : : "t"(x) : "st");

While this will pop the input and push an output:

  asm("fst %st" : "=&t"(r) : "t"(x));

We need to know if ST0 was a clobber or an output operand, and we can't
depend on <dead> flags for that.

llvm-svn: 133902
2011-06-27 04:08:33 +00:00
Jakob Stoklund Olesen 6b356b18b4 Decode and pretty print inline asm operand descriptors.
The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so
it is easier to read:

  INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def>

llvm-svn: 133901
2011-06-27 04:08:29 +00:00
Devang Patel f071d72c44 Handle debug info for i128 constants.
llvm-svn: 133821
2011-06-24 20:46:11 +00:00
Evan Cheng cfdf33904b Re-commit 131172 with fix. MachineInstr identity checks should check dead
markers. In some cases a register def is dead on one path, but not on
another.

This is passing Clang self-hosting.

llvm-svn: 131214
2011-05-12 00:56:58 +00:00
Jakob Stoklund Olesen 89bd2ae517 Remove an assertion to fix PR9872.
It can happen that a live debug variable is the last use of a sub-register, and
the register allocator will pick a larger register class for the virtual
register.  If the allocated register doesn't support the sub-register index,
just use %noreg for the debug variables instead of asserting.

In PR9872, a debug variable ends up in the sub_8bit_hi part of a GR32_ABCD
register. The register is split and one part is inflated to GR32 and assigned
%ESI because there are no more normal uses of sub_8bit_hi.

Since %ESI doesn't have that sub-register, substPhysReg asserted. Now it will
simply insert a %noreg instead, and the debug variable will be marked
unavailable in that range.

We don't currently have a way of saying: !"value" is in bits 8-15 of %ESI, I
don't know if DWARF even supports that.

llvm-svn: 131073
2011-05-08 19:21:08 +00:00
Bill Wendling 9f638ab181 Print out the 'nontemporal' info on a store.
llvm-svn: 130562
2011-04-29 23:45:22 +00:00
Jakob Stoklund Olesen 76ad3debab Ensure all defs referring to a virtual register are marked dead by addRegisterDead().
There can be multiple defs for a single virtual register when they are defining
sub-registers.

The missing <dead> flag was stopping the inline spiller from eliminating dead
code after rematerialization.

llvm-svn: 128888
2011-04-05 16:53:50 +00:00
Anton Korobeynikov 65cff414b6 Add FrameSetup MI flags
llvm-svn: 127098
2011-03-05 18:43:04 +00:00
Jakob Stoklund Olesen 2fb5b31578 Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

llvm-svn: 123155
2011-01-10 02:58:51 +00:00
Jakob Stoklund Olesen 1331a15b0c Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance.
Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first virtual register is printed as %vreg0.
TRI::NoRegister is printed as %noreg.

llvm-svn: 123107
2011-01-09 03:05:53 +00:00
Evan Cheng 6eb516dbea Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.

This allows memory instructions to be moved around INLINEASM instructions.

llvm-svn: 123044
2011-01-07 23:50:32 +00:00
Evan Cheng 0638c20e7c DBG_VALUE does not have any side effects; it also makes no sense to mark it cheap as a copy.
llvm-svn: 123031
2011-01-07 21:08:26 +00:00
Evan Cheng 21eedfb5a2 Unbreak build.
llvm-svn: 117155
2010-10-22 21:49:09 +00:00
Dan Gohman a94cc6dfe8 Make CodeGen TBAA-aware.
llvm-svn: 116890
2010-10-20 00:31:05 +00:00
Jakob Stoklund Olesen a4941690cc Shrink MachineOperand from 40 to 32 bytes on 64-bit hosts.
Pull an unsigned out of the Contents union such that it has the same size as two
pointers and no padding.

Arrange members such that the Contents union and all pointers can be 8-byte
aligned without padding.

This speeds up code generation by 0.8% on a 64-bit host. 32-bit hosts should be
unaffected.

llvm-svn: 116857
2010-10-19 20:56:32 +00:00
Chris Lattner 886250c8f0 convert a couple more places to use the new getStore()
llvm-svn: 114463
2010-09-21 18:51:21 +00:00
Chris Lattner 50287ea65a add some accessors
llvm-svn: 114409
2010-09-21 06:43:24 +00:00
Chris Lattner 82fd06d3ce it's more elegant to put the "getConstantPool" and
"getFixedStack" on the MachinePointerInfo class.  While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.

llvm-svn: 114406
2010-09-21 06:22:23 +00:00
Chris Lattner de93bb065d add some helpful accessors.
llvm-svn: 114400
2010-09-21 05:39:30 +00:00
Chris Lattner 00ca0b8e98 start pushing MachinePointerInfo out through the MachineMemOperand interface
to the MachineFunction construction methods.

llvm-svn: 114390
2010-09-21 04:32:08 +00:00
Chris Lattner 187f653418 refactor the Value*/offset pair from MachineMemOperand out to a new
MachinePointerInfo struct, no functionality change.

This also adds an assert to MachineMemOperand::MachineMemOperand
that verifies that the Value* is either null or is an IR pointer type.

llvm-svn: 114389
2010-09-21 04:23:39 +00:00
Oscar Fuentes 40b31ad3ee Prefix `next' iterator operation with `llvm::'.
Fixes potential ambiguity problems on VS 2010.

Patch by nobled!

llvm-svn: 110029
2010-08-02 06:00:15 +00:00
Jakob Stoklund Olesen 0ff2c110ad Print out the regclass of any virtual registers used by a machine instruction.
llvm-svn: 109608
2010-07-28 18:35:46 +00:00
Jakob Stoklund Olesen ac0a210789 Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG.
llvm-svn: 107602
2010-07-04 23:24:23 +00:00
Dale Johannesen 4d887f7ca7 Propagate the AlignStack bit in InlineAsm's to the
PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not.  gcc consistently
does not do this for GCC-style asms; Apple gcc inconsistently
sometimes does it for asm blocks.  There is no
convenient place to put a bit in either the SDNode or
the MachineInstr form, so I've added an extra operand
to each; unlovely, but it does allow for expansion for
more bits, should we need it.  PR 5125.  Some
existing testcases are affected.
The operand lists of the SDNode and MachineInstr forms
are indexed with awesome mnemonics, like "2"; I may
fix this someday, but not now.  I'm not making it any
worse.  If anyone is inspired I think you can find all
the right places from this patch.

llvm-svn: 107506
2010-07-02 20:16:09 +00:00
Devang Patel c728518bfe Print InlinedAt location.
llvm-svn: 107208
2010-06-29 21:51:32 +00:00
Dan Gohman 8693650422 Teach regular and fast isel to set dead flags on unused implicit defs
on calls and similar instructions.

llvm-svn: 106353
2010-06-18 23:28:01 +00:00
Jakob Stoklund Olesen a8ad97743d Slightly change the meaning of the reMaterialize target hook when the original
instruction defines subregisters.

Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.

Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:

  %reg1234:foo = FLAP %reg1234<imp-def>

will reMaterialize(%reg3333, bar) like this:

  %reg3333:bar-foo = FLAP %reg333:bar<imp-def>

Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.

llvm-svn: 105358
2010-06-02 22:47:25 +00:00
Jakob Stoklund Olesen 7b0ac865a4 Properly compose subregister indices when coalescing.
The comment about ordering of subreg indices is no longer true.
This exposed a bug in the new substVirtReg method that is also fixed.

llvm-svn: 105294
2010-06-01 22:39:25 +00:00
Jakob Stoklund Olesen 64824ea99f Add a TargetRegisterInfo::composeSubRegIndices hook with a default
implementation that is correct for most targets. Tablegen will override where
needed.

Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing
subreg indices when sustituting registers.

llvm-svn: 104985
2010-05-28 18:18:53 +00:00
Jakob Stoklund Olesen 1ad0d5e25b Print symbolic SubRegIndex names on machine operands.
llvm-svn: 104628
2010-05-25 19:49:38 +00:00
Evan Cheng 3858451e09 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377
2010-05-21 20:53:24 +00:00
Jakob Stoklund Olesen 7d7f604321 Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction
reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

llvm-svn: 104372
2010-05-21 20:02:01 +00:00
Jakob Stoklund Olesen b4e1687270 Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read."
This reverts r104322. I think it was causing miscompilations.

llvm-svn: 104323
2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen 8e8e090301 Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.
This correctly handles partial redefines and undef uses.

llvm-svn: 104322
2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen 1f3801062d If the first definition of a virtual register is a partial redef, add an
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

llvm-svn: 104320
2010-05-21 16:32:16 +00:00
Jakob Stoklund Olesen 5d4c134a94 Add MachineInstr::readsVirtualRegister() in preparation for proper handling of
partial redefines.

We are going to treat a partial redefine of a virtual register as a
read-modify-write:

  %reg1024:6 = OP

Unless the register is fully clobbered:

  %reg1024:6 = OP, %reg1024<imp-def>

MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.

llvm-svn: 104149
2010-05-19 20:36:22 +00:00
Dan Gohman c90f51c00b Teach MachineLICM and MachineSink how to clear kill flags conservatively
when they move instructions.

llvm-svn: 103737
2010-05-13 20:34:42 +00:00
Evan Cheng d4d1a51895 Pretty print DBG_VALUE machine instructions.
Before:
DBG_VALUE %RSI, 0, !-1; dbg:SimpleRegisterCoalescing.cpp:2707
Now:
DBG_VALUE %RSI, 0, !"this"; dbg:SimpleRegisterCoalescing.cpp:2707

llvm-svn: 102518
2010-04-28 20:03:13 +00:00
Bob Wilson d8eeb12120 Use getNumImplicitDefs() and getNumImplicitUses().
llvm-svn: 100850
2010-04-09 04:46:43 +00:00
Bob Wilson 406f270148 Fix up some comments.
llvm-svn: 100849
2010-04-09 04:34:03 +00:00
Evan Cheng b083c47c21 Coalescer should not delete copy instructions whose defs are partially dead. e.g.
%RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def>

llvm-svn: 100804
2010-04-08 20:02:37 +00:00
Chris Lattner f839ee0c13 fix a latent bug my inline asm stuff exposed:
MachineOperand::isIdenticalTo wasn't handling metadata operands.

llvm-svn: 100636
2010-04-07 18:03:19 +00:00
Chris Lattner bd009d6d6d stop using DebugLoc::getUnknownLoc()
llvm-svn: 100215
2010-04-02 20:17:23 +00:00
Chris Lattner 915c5f9862 Switch the code generator (except the JIT) onto the new DebugLoc
representation.  This eliminates the 'DILocation' MDNodes for 
file/line/col tuples from -O0 -g codegen.

This remove the old DebugLoc class, making it a typedef for DebugLoc,
I'll rename NewDebugLoc next.

I didn't update the JIT to use the new apis, so it will continue to
work, but be as slow as before.  Someone should eventually do this
or, better yet, rip out the JIT debug info stuff and build the JIT
on top of MC.

llvm-svn: 100209
2010-04-02 19:42:39 +00:00
Chris Lattner 6c604e3f94 add support for MCSymbols as operands to MachineInstrs.
llvm-svn: 98433
2010-03-13 08:14:18 +00:00
Devang Patel 3b548aa8e2 Avoid using DIDescriptor.isNull().
This is a first step towards eliminating checks in Descriptor constructors.

llvm-svn: 97975
2010-03-08 20:52:55 +00:00
Devang Patel bc97f6b757 Revert r97947.
llvm-svn: 97963
2010-03-08 19:20:38 +00:00
Devang Patel fe28599f6f Avoid using DIDescriptor.isNull().
This is a first step towards eliminating unncessary constructor checks in light weight DIDescriptor wrappers.

llvm-svn: 97947
2010-03-08 18:25:48 +00:00
Evan Cheng 59d27fe597 Move MachineInstrExpressionTrait::getHashValue() out of line so it can skip over only virtual register defs. This matches what isEqual() is doing.
llvm-svn: 97680
2010-03-03 23:37:30 +00:00
Evan Cheng 0f260e1785 Fix funky indentation and add comments.
llvm-svn: 97670
2010-03-03 21:54:14 +00:00
Evan Cheng e9c46c25a1 - Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).

llvm-svn: 97628
2010-03-03 01:44:33 +00:00
Evan Cheng 62e795ab8c Swap parameters of isSafeToMove and isSafeToReMat for consistency.
llvm-svn: 97578
2010-03-02 19:03:01 +00:00
David Greene 3a0412f122 Add non-temporal flags to MachineMemOperand.
llvm-svn: 96226
2010-02-15 16:48:31 +00:00
Dan Gohman 4a618827de Fix "the the" and similar typos.
llvm-svn: 95781
2010-02-10 16:03:48 +00:00
Dale Johannesen d40d42c9e5 Add isDebug argument to ChangeToRegister; this prevents
the field from being used uninitialized later in some cases.

llvm-svn: 95735
2010-02-10 00:41:49 +00:00
Chris Lattner b06015aa69 move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
2010-02-09 19:54:29 +00:00
Jakob Stoklund Olesen e8800b8d7c Identify predicate and optional-def operands when printing machine
instructions.

llvm-svn: 93925
2010-01-19 22:08:34 +00:00
Devang Patel c0e17df3ce Replace DebugLocTuple with DILocation.
llvm-svn: 93630
2010-01-16 06:09:35 +00:00
Dale Johannesen 7b1a7ed330 Further progration of metadata operands. The
dumper doesn't really do what I want yet, but
at least it doesn't crash now.

llvm-svn: 93272
2010-01-13 00:00:24 +00:00
Jakob Stoklund Olesen 7725526de1 Add <imp-def> and <imp-kill> operands when replacing virtual sub-register defs and kills.
An instruction like this:

  %reg1097:1<def> = VMOVSR %R3<kill>, 14, %reg0

Must be replaced with this when substituting physical registers:

  %S0<def> = VMOVSR %R3<kill>, 14, %reg0, %D0<imp-def>

llvm-svn: 92812
2010-01-06 00:29:28 +00:00
David Greene 29388d6a6f Change errs() to dbgs().
llvm-svn: 92545
2010-01-04 23:48:20 +00:00
Chris Lattner 5a409bd17a snip one more #include from Metadata.h
llvm-svn: 92214
2009-12-28 08:30:43 +00:00
Bill Wendling ec030f2f01 Remove dead store.
llvm-svn: 92159
2009-12-25 13:45:50 +00:00
Bill Wendling 49fac47c83 Remove dead store from copy-pasto.
llvm-svn: 92158
2009-12-25 13:44:36 +00:00
Jim Grosbach 2a282f2f86 Add @earlyclobber TableGen constraint
llvm-svn: 91554
2009-12-16 19:43:02 +00:00
Evan Cheng 5c668a2259 Follow up to 90488. Turn a check into an assertion.
llvm-svn: 90815
2009-12-07 23:10:34 +00:00
Dan Gohman 33004b6302 Don't print the debug directory; it's often long and uninteresting. Omit
the column number if it is not known. Handle the case of a missing filename
better.

llvm-svn: 90630
2009-12-05 00:20:51 +00:00
Evan Cheng 8a19371370 Watch out for PHI instruction with no source operands.
llvm-svn: 90488
2009-12-03 21:50:58 +00:00
Evan Cheng 7145382389 Fill out codegen SSA updater. It's not yet tested.
llvm-svn: 90395
2009-12-03 02:31:43 +00:00
Dan Gohman 461b937053 Devang pointed out that this code should use DIScope instead of
DICompileUnit. This code now prints debug filenames successfully.

llvm-svn: 90181
2009-12-01 00:45:56 +00:00
Dan Gohman 2e3f187cbd Print the debug info line and column in MachineInstr::print even when there's
no filename. This situation is apparently fairly common right now.

llvm-svn: 89701
2009-11-23 21:29:08 +00:00
Dan Gohman 9b5eea30f7 Initialize the new AsmPrinterFlags field to 0, fixing uses of
uninitialized memory.

llvm-svn: 88985
2009-11-16 22:49:38 +00:00
Dan Gohman 2745d19287 Print "..." instead of all the uninteresting register clobbers on call
instructions. This makes CodeGen dumps significantly less noisy.

Example before:
  BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,dead>, %D31<imp-def,dead>, %CPSR<imp-def,dead>, %FPSCR<imp-def,dead>

Same example after:
  BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %LR<imp-def,dead>, %CPSR<imp-def,dead>, ...

llvm-svn: 86583
2009-11-09 19:38:45 +00:00
Dan Gohman 0080ee2d91 Use WriteAsOperand to print GlobalAddress MachineOperands. This
prints them with the leading '@'.

llvm-svn: 86261
2009-11-06 18:03:10 +00:00
Dan Gohman 34341e69c4 Make -print-machineinstrs more readable.
- Be consistent when referring to MachineBasicBlocks: BB#0.
 - Be consistent when referring to virtual registers: %reg1024.
 - Be consistent when referring to unknown physical registers: %physreg10.
 - Be consistent when referring to known physical registers: %RAX
 - Be consistent when referring to register 0: %reg0
 - Be consistent when printing alignments: align=16
 - Print jump table contents.
 - Don't print host addresses, in general.
 - and various other cleanups.

llvm-svn: 85682
2009-10-31 20:19:03 +00:00
Dan Gohman 6c9388011b Initial target-independent CodeGen support for BlockAddresses.
llvm-svn: 85556
2009-10-30 01:27:03 +00:00
Evan Cheng f781bd8947 Need a comma after imp-use.
llvm-svn: 84749
2009-10-21 07:56:02 +00:00
Evan Cheng 70b1fa5a24 Print earlyclobber for implicit-defs as well.
llvm-svn: 84152
2009-10-14 23:37:31 +00:00
Devang Patel d7ebfe3963 s/DebugLoc.CompileUnit/DebugLoc.Scope/g
s/DebugLoc.InlinedLoc/DebugLoc.InlinedAtLoc/g

llvm-svn: 84054
2009-10-13 23:28:53 +00:00
Dan Gohman 87b02d5bbc Factor out LiveIntervalAnalysis' code to determine whether an instruction
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.

This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.

llvm-svn: 83687
2009-10-09 23:27:56 +00:00
Dan Gohman e19c1810d7 isTriviallyReMaterializable checks the
TargetInstrDesc::isRematerializable flag, so it isn't necessary to do
this check in its callers.

llvm-svn: 83671
2009-10-09 21:02:10 +00:00
Dan Gohman be8137b0b4 Replace TargetInstrInfo::isInvariantLoad and its target-specific
implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.

llvm-svn: 83475
2009-10-07 17:38:06 +00:00
Chris Lattner fdd8790718 strength reduce a ton of type equality tests to check the typeid (Through
the new predicates I added) instead of going through a context and doing a
pointer comparison.  Besides being cheaper, this allows a smart compiler
to turn the if sequence into a switch.

llvm-svn: 83297
2009-10-05 05:54:46 +00:00
Devang Patel b296942f6d Remove std::string uses from DebugInfo interface.
llvm-svn: 83083
2009-09-29 18:40:58 +00:00
Dan Gohman 5a6b11cb71 Move MachineMemOperand::getAlignment out of line, to avoid needing
MathExtras.h in MachineMemOperand.h.

llvm-svn: 82822
2009-09-25 23:33:20 +00:00
Dan Gohman 48b185d6f7 Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.

llvm-svn: 82794
2009-09-25 20:36:54 +00:00
Dan Gohman c0353bfff5 Give MachineMemOperand an operator<<, factoring out code from
two different places for printing MachineMemOperands.

Drop the virtual from Value::dump and instead give Value a
protected virtual hook that can be overridden by subclasses
to implement custom printing. This lets printing be more
consistent, and simplifies printing of PseudoSourceValue
values.

llvm-svn: 82599
2009-09-23 01:33:16 +00:00
Dan Gohman e7c8242baa Change MachineMemOperand's alignment value to be the alignment of
the base pointer, without the offset. This matches MemSDNode's
new alignment behavior, and holds more interesting information.

llvm-svn: 82473
2009-09-21 19:47:04 +00:00
Jim Grosbach 9632c14949 grammar
llvm-svn: 82150
2009-09-17 17:57:26 +00:00
Chris Lattner 471ba48cb9 remove some uses of llvm/Support/Streams.h
llvm-svn: 79842
2009-08-23 08:43:55 +00:00
Chris Lattner a6f074fb3a remove various std::ostream version of printing methods from
MachineInstr and MachineOperand.  This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)

llvm-svn: 79813
2009-08-23 03:41:05 +00:00
Owen Anderson 55f1c09e31 Push LLVMContexts through the IntegerType APIs.
llvm-svn: 78948
2009-08-13 21:58:54 +00:00
Jakob Stoklund Olesen f465f06aa4 Don't tamper with <undef> operands in MachineInstr::addRegisterKilled.
For an undef operand, MO.getReg() is meaningless and we should not use it.
Undef operands should be skipped entirely.

llvm-svn: 78095
2009-08-04 20:09:25 +00:00
Jakob Stoklund Olesen 5d8ace0902 Fix Bug 4657: register scavenger asserts with subreg lowering
When LowerSubregsInstructionPass::LowerInsert eliminates an INSERT_SUBREG
instriction because it is an identity copy, make sure that the same registers
are alive before and after the elimination.

When the super-register is marked <undef> this requires inserting an
IMPLICIT_DEF instruction to make sure the super register is live.

Fix a related bug where a kill flag on the inserted sub-register was not transferred properly.

Finally, clear the undef flag in MachineInstr::addRegisterKilled. Undef implies dead and kill implies live, so they cant both be valid.

llvm-svn: 77989
2009-08-03 20:08:18 +00:00
Jakob Stoklund Olesen c59cd9bcd0 Never add a kill flag to a constrained physical register in a two-addr instruction.
llvm-svn: 77906
2009-08-02 19:13:03 +00:00
Evan Cheng 4a04041056 Fix a typo.
llvm-svn: 77369
2009-07-28 21:49:18 +00:00
Jakob Stoklund Olesen aba695c7d0 Fix http://llvm.org/bugs/show_bug.cgi?id=4583
Inline asm instructions may have additional <imp-def,kill> register operands.
These operands are not marked with a flag like the normal asm operands, so we
must not assert that there is a flag.

llvm-svn: 76373
2009-07-19 19:09:59 +00:00
Jakob Stoklund Olesen 070fab8a1f Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands.
The inline asm operands must be parsed from the first flag, you cannot assume
that an immediate operand preceeding a register use operand is the flag.
PowerPC "m" operands are represented as (flag, imm, reg) triples.
isRegTiedToDefOperand() would incorrectly interpret the imm as the flag.

llvm-svn: 76101
2009-07-16 20:58:34 +00:00
Torok Edwin fbcc663cbf llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640
2009-07-14 16:55:14 +00:00
Torok Edwin 56d0659726 assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.

llvm-svn: 75379
2009-07-11 20:10:48 +00:00
Evan Cheng 0dc101b897 Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.

llvm-svn: 74518
2009-06-30 08:49:04 +00:00
Chris Lattner fd682802e3 Rearrange some stuff in MachineOperand and add a new TargetFlags field.
llvm-svn: 74087
2009-06-24 17:54:48 +00:00
Evan Cheng 38f2453817 Fix support for inline asm input / output operand tying when operand spans across multiple registers (e.g. two i64 operands in 32-bit mode).
llvm-svn: 74053
2009-06-24 02:05:51 +00:00
Dan Gohman d9ef48a73e Remove some unnecessary #includes.
llvm-svn: 72948
2009-06-05 16:32:58 +00:00
Argyrios Kyrtzidis a5037484a4 Make DebugLoc independent of DwarfWriter.
-Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable*
-Remove DwarfWriter::getOrCreateSourceID
-Make necessary changes for the above (fix callsites, etc.)

llvm-svn: 70520
2009-04-30 23:22:31 +00:00
Jakob Stoklund Olesen 1971dc7007 MachineInstr::isRegTiedTo{Use,Def}Operand can safely be made const.
llvm-svn: 70408
2009-04-29 20:57:16 +00:00
Dan Gohman 37608532c4 Fix MachineInstr::getNumExplicitOperands to count
variadic operands correctly. Patch by Jakob Stoklund Olesen!

llvm-svn: 69190
2009-04-15 17:59:11 +00:00
Dan Gohman 89892b05c7 Give RemoveRegOperandFromRegInfo a comment and move the
code out of line.

llvm-svn: 69124
2009-04-15 01:17:37 +00:00
Chris Lattner 66ab904f5a ignore register zero in isRegTiedToUseOperand, following the example of
isRegTiedToDefOperand.  Thanks to Bob for pointing this out!

llvm-svn: 68734
2009-04-09 23:33:34 +00:00
Bob Wilson 51856173c8 Fix pr3954. The register scavenger asserts for inline assembly with
register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714
2009-04-09 17:16:43 +00:00
Chris Lattner a725028d41 reg0 references are not real registers. This fixes a crash on the
attached testcase.

llvm-svn: 68712
2009-04-09 16:50:43 +00:00
Evan Cheng 968c3b0d6e Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
llvm-svn: 67512
2009-03-23 08:01:15 +00:00
Evan Cheng 1361cbbb0b Added MachineInstr::isRegTiedToDefOperand to check for two-addressness.
llvm-svn: 67335
2009-03-19 20:30:06 +00:00
Bill Wendling 1a0a3d0ff5 Print out debug info when printing the machine instruction.
llvm-svn: 65067
2009-02-19 21:44:55 +00:00
Dale Johannesen 4e04ef3c55 Add a DebugLoc field and some simple accessors.
llvm-svn: 63152
2009-01-27 23:20:29 +00:00
Dan Gohman 072e52f170 Use isTerminator() instead of isBranch()||isReturn() in
several places. isTerminator() returns true for a superset
of cases, and includes things like FP_REG_KILL, which are
nither return or branch but aren't safe to move/remat/etc.

llvm-svn: 61373
2008-12-23 17:28:50 +00:00
Dan Gohman 0ab1144c79 Print subreg information in MachineInstr::dump.
llvm-svn: 61213
2008-12-18 21:51:27 +00:00
Dan Gohman 9356d8f74d Minor code simplification.
llvm-svn: 60804
2008-12-09 22:45:08 +00:00
Dan Gohman d24be45d99 Drop the reg argument to isRegReDefinedByTwoAddr, which was redundant.
llvm-svn: 60586
2008-12-05 05:45:42 +00:00
Dan Gohman 0b2732598c Add more const qualifiers. This fixes build breakage from r59540.
llvm-svn: 59542
2008-11-18 19:49:32 +00:00
Dan Gohman 0d9d8ae487 Make some methods const.
llvm-svn: 59540
2008-11-18 19:04:29 +00:00
Mon P Wang dfcc1ff8f8 Added missing print functions that take a raw_ostream
llvm-svn: 57339
2008-10-10 01:43:55 +00:00
Dan Gohman 0d1e9a8e04 Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.

llvm-svn: 57006
2008-10-03 15:45:36 +00:00
Dan Gohman 88536398ff Fix a think-o in isSafeToMove. This fixes it from thinking that
volatile memory references are safe to move.

llvm-svn: 56948
2008-10-02 15:04:30 +00:00
Dale Johannesen c36660d756 Next round of earlyclobber handling. Approach the
RA problem by expanding the live interval of an
earlyclobber def back one slot.  Remove
overlap-earlyclobber throughout.  Remove 
earlyclobber bits and their handling from
live internals.

llvm-svn: 56539
2008-09-24 01:07:17 +00:00
Dan Gohman 7c59ed6ff8 Add a method to MachineInstr for testing whether it makes
any volatile memory references.

llvm-svn: 56528
2008-09-24 00:06:15 +00:00
Dale Johannesen f8610ebebc Add a bit to mark operands of asm's that conflict
with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.

llvm-svn: 56290
2008-09-17 21:13:11 +00:00
Dale Johannesen c0d712d9ed adjust last patch per review feedback
llvm-svn: 56194
2008-09-14 01:44:36 +00:00
Dan Gohman 38453eebdc Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189
2008-09-13 17:58:21 +00:00
Dale Johannesen 1f3ab86804 Pass "earlyclobber" bit through to machine
representation; coalescer and RA need to know
about it.  No functional change.

llvm-svn: 56161
2008-09-12 17:49:03 +00:00
Dan Gohman c7367b4546 Fix addRegisterDead and addRegisterKilled to be more thorough
when searching for redundant subregister dead/kill bits.

Previously it was common to see instructions marked like this:
  "RET %EAX<imp-use,kill>, %AX<imp-use,kill>"

With this change, addRegisterKilled continues scanning after
finding the %EAX operand, so it proceeds to discover the
redundant %AX kill and eliminates it, producing this:
  "RET %EAX<imp-use,kill>"

This currently has no effect on the generated code.

llvm-svn: 55698
2008-09-03 15:56:16 +00:00
Evan Cheng 542ac62971 Fold isRematerializable checks into isSafeToReMat.
llvm-svn: 55563
2008-08-30 09:07:18 +00:00
Evan Cheng f016b263e2 Move the check whether it's worth remating to caller.
llvm-svn: 55434
2008-08-27 20:58:54 +00:00
Evan Cheng 57dc078570 Refactor isSafeToReMat out of 2addr pass.
llvm-svn: 55430
2008-08-27 20:33:50 +00:00
Chris Lattner a078d83e17 simplify PseudoSourceValue printing a bit. Unnest all of PseudoSourceValue.cpp from the llvm namespace.
llvm-svn: 55293
2008-08-24 20:37:32 +00:00
Evan Cheng 72e7d91591 Print PseudoSourceValue.
llvm-svn: 55291
2008-08-24 18:51:20 +00:00
Dan Gohman 2da2bedc72 Change the FoldingSetNodeID usage for objects which carry
alignment and volatility information, such as loads and
stores, to reduce the number of integer values added to
the FoldingSetNodeID.

llvm-svn: 55058
2008-08-20 15:58:01 +00:00
Owen Anderson 96631091df Move MachineInstr::getOpcode inline.
llvm-svn: 54807
2008-08-14 23:25:30 +00:00