49e55b8059
Add ELF relocation types for Mips.
...
Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141935
2011-10-14 02:43:18 +00:00
769fc971b4
Fixup enumerations.
...
Patch by Jack Carter at Mips.
llvm-svn: 141934
2011-10-14 02:38:56 +00:00
4e2bfe0770
Add more Mips relocation types.
...
Patch by Jack Carter at Mips.
llvm-svn: 141932
2011-10-14 02:17:30 +00:00
d9444d455e
Ban rematerializable instructions with side effects.
...
TableGen infers unmodeled side effects on instructions without a
pattern. Fix some instruction definitions where that was overlooked.
Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.
llvm-svn: 141929
2011-10-14 01:00:49 +00:00
eafa9d50c2
V_SET0 has no side effects.
...
TableGen will mark any pattern-less instruction as having unmodeled side
effects. This is extra bad for V_SET0 which gets rematerialized a lot.
This was part of the cause for PR11125, but the real bug was fixed
in r141923.
llvm-svn: 141924
2011-10-14 00:39:50 +00:00
7fb5632e73
Add value numbers when spilling dead defs.
...
When spilling around an instruction with a dead def, remember to add a
value number for the def.
The missing value number wouldn't normally create problems since there
would be an incoming live range as well. However, due to another bug
we could spill a dead V_SET0 instruction which doesn't read any values.
The missing value number caused an empty live range to be created which
is dangerous since it doesn't interfere with anything.
This fixes part of PR11125.
llvm-svn: 141923
2011-10-14 00:34:31 +00:00
b46345d7c1
Avoid undefined behavior in negation in LSR. Patch by Ahmed Charles.
...
Someone more familiar with LSR should double-check that the extra cast is actually doing the right thing in the overflow cases; I'm not completely confident that's that case.
llvm-svn: 141916
2011-10-13 23:48:33 +00:00
a7ad9f3932
Fix undefined shift. Patch by Ahmed Charles.
...
llvm-svn: 141914
2011-10-13 23:36:06 +00:00
a5abd03a8d
Simplify assertion, and avoid undefined shift. Based on patch by Ahmed Charles.
...
llvm-svn: 141912
2011-10-13 23:27:48 +00:00
a7a90bfdab
Support/Windows: Add support modifying memory permissions on Windows. Patch by Aaron Ballman!
...
llvm-svn: 141910
2011-10-13 23:16:01 +00:00
92734d6f46
Fix undefined shifts and abs in Alpha backend. Based on patch by Ahmed Charles.
...
llvm-svn: 141909
2011-10-13 23:13:35 +00:00
0084615924
Support/Windows: Add efficent RW mutex on Windows. Patch by Aaron Ballman!
...
llvm-svn: 141907
2011-10-13 23:10:56 +00:00
91fc0905a2
Fixed typo.
...
llvm-svn: 141906
2011-10-13 23:04:49 +00:00
53ba208c72
Avoid undefined behavior in signed integer negation. Patch by Ahmed Charles.
...
llvm-svn: 141905
2011-10-13 22:49:56 +00:00
aa6ec39056
Simplify and avoid undefined shift. Based on patch by Ahmed Charles.
...
llvm-svn: 141903
2011-10-13 22:40:23 +00:00
834bd602e6
ELF: Fix the section that relocations apply to. Add test to verify. Patch by Danil Malyshev!
...
llvm-svn: 141901
2011-10-13 22:30:10 +00:00
51862b3890
llvm-object: Add inline relocation information to disassembly.
...
llvm-svn: 141897
2011-10-13 22:17:18 +00:00
c1702c8f22
Enhance the memdep interface so that users can tell the difference between a dependency which cannot be calculated and a path reaching the entry point of the function. This patch introduces isNonFuncLocal, which replaces isUnknown in some cases.
...
Patch by Xiaoyi Guo.
llvm-svn: 141896
2011-10-13 22:14:57 +00:00
870c1a3f15
Reapply r141870, SCEV expansion of post-inc.
...
Speculatively reapply to see if this test case still crashes on
linux. I may have fixed it in my last checkin.
llvm-svn: 141895
2011-10-13 21:55:29 +00:00
76933f4c0b
Don't forget to reconstruct D after changing the scope that we're
...
looking at.
llvm-svn: 141892
2011-10-13 21:43:44 +00:00
742549f8ef
Update IntrinsicsXCore.td with the normal LLVM notice at the top of the file.
...
llvm-svn: 141889
2011-10-13 21:08:11 +00:00
8f67d47d0d
llvm-objdump: Fix whitespace.
...
llvm-svn: 141886
2011-10-13 20:37:20 +00:00
ee84f64f0b
llvm-objdump: Fix dumping of multiple symbols with the same address.
...
This happens in COFF because there is a symbol for the beginning of each
section.
llvm-svn: 141885
2011-10-13 20:37:08 +00:00
9a28851e52
COFF: Implement sectionContainsSymbol for relocatable files only.
...
llvm-svn: 141884
2011-10-13 20:36:54 +00:00
7e442569dc
Fix memory corruption I introduced a few checkins ago.
...
Self-review easily caught this obvious bug.
llvm-svn: 141880
2011-10-13 18:49:23 +00:00
d5a9a3afaf
configure: [cygming] Set --disable-embed-stdcxx by default on --enable-shared.
...
Many distros provide stdc++.dll recently. --enable-embed-stdcxx might confuse people.
llvm-svn: 141875
2011-10-13 18:04:52 +00:00
44f76eafae
SETEND is not allowed in an IT block.
...
llvm-svn: 141874
2011-10-13 17:58:39 +00:00
41c253c35c
Revert r141870. The test case crashes on linux with data corruption. A deeper issue was exposed.
...
llvm-svn: 141873
2011-10-13 17:58:24 +00:00
9423f99d68
docs/CMake.html: Clarify LLVM_LIT_TOOLS_DIR as :PATH.
...
llvm-svn: 141872
2011-10-13 17:36:02 +00:00
6b1ff2c3b4
Fix incorrect ELF typedefs.
...
llvm-svn: 141871
2011-10-13 17:33:52 +00:00
e15d6e14e3
LSR: Reuse the post-inc expansion of expressions.
...
This avoids unnecessary expansion of expressions and allows the SCEV
expander to work on expression DAGs, not just trees.
Fixes PR11090.
llvm-svn: 141870
2011-10-13 17:31:47 +00:00
4072bfe713
build: Remove some stray LLVMC configure variables.
...
llvm-svn: 141869
2011-10-13 17:27:34 +00:00
1393ec29af
SCEV: Rewrite TrandformForPostIncUse to handle expression DAGs, not
...
just expression trees.
Partially fixes PR11090. Test case will be with the full fix.
llvm-svn: 141868
2011-10-13 17:21:09 +00:00
adfe72b33c
Slightly more useful tracing.
...
llvm-svn: 141867
2011-10-13 17:06:38 +00:00
f07d898ae1
Force CPU type on test so it doesn't accidentally emit movbe instead of bswap on Intel Atom CPUs.
...
llvm-svn: 141863
2011-10-13 14:27:54 +00:00
3815de8d50
Mark 'branch indirect' instruction as an indirect branch.
...
Not having it confused assembly printing of jumptables.
llvm-svn: 141862
2011-10-13 11:40:03 +00:00
25f6d3e321
More closely follow libgcc, which has code after the `ret' instruction to
...
release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.
llvm-svn: 141859
2011-10-13 08:24:19 +00:00
063f55ffdd
Revert r141854 because it was causing failures:
...
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
llvm-svn: 141857
2011-10-13 07:48:07 +00:00
22a690e3db
Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I.
...
llvm-svn: 141856
2011-10-13 07:42:32 +00:00
86f7d3556c
Use an existing method.
...
llvm-svn: 141855
2011-10-13 07:36:41 +00:00
8cc9388073
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
...
llvm-svn: 141854
2011-10-13 07:09:14 +00:00
2fdcb1f045
Add 'implicit EFLAGS' to patterns for popcnt and lzcnt
...
llvm-svn: 141853
2011-10-13 06:18:52 +00:00
d3043965b9
Elf_Word is not POD! Stop using it in a DenseMap.
...
llvm-svn: 141851
2011-10-13 03:30:21 +00:00
594a545821
If MI is deleted then remove it from the set. If a new MI is created, it could
...
have the same address as the one we deleted, and we don't want that in the set
yet. Noticed by inspection.
llvm-svn: 141849
2011-10-13 02:16:18 +00:00
404feb9973
Tabs to spaces.
...
llvm-svn: 141844
2011-10-13 01:09:50 +00:00
8488225984
Add missing braces to pacify GCC's -Wparentheses.
...
llvm-svn: 141842
2011-10-13 00:54:59 +00:00
f9799f8181
Add missing ELF constants.
...
llvm-svn: 141840
2011-10-13 00:16:25 +00:00
068dc91de9
Also inflate register classes around inline asm.
...
Now that MI->getRegClassConstraint() can also handle inline assembly,
don't bail when recomputing the register class of a virtual register
used by inline asm.
This fixes PR11078.
llvm-svn: 141836
2011-10-12 23:37:40 +00:00
35b362fab2
Add MachineInstr::getRegClassConstraint().
...
Most instructions have some requirements for their register operands.
Usually, this is expressed as register class constraints in the
MCInstrDesc, but for inline assembly the constraints are encoded in the
flag words.
llvm-svn: 141835
2011-10-12 23:37:36 +00:00
1e73716eae
Extract a method for finding the inline asm flag operand.
...
llvm-svn: 141834
2011-10-12 23:37:33 +00:00
24abd9d9b6
Encode register class constreaints in inline asm instructions.
...
The inline asm operand constraint is initially encoded in the virtual
register for the operand, but that register class may change during
coalescing, and the original constraint is lost.
Encode the original register class as part of the flag word for each
inline asm operand. This makes it possible to recover the actual
constraint required by inline asm, just like we can for normal
instructions.
llvm-svn: 141833
2011-10-12 23:37:29 +00:00
212e447967
Attempt to fix MSVC build.
...
llvm-svn: 141831
2011-10-12 23:14:41 +00:00
3e5409df77
We need to verify that the machine instruction we're using as a replacement for
...
our current machine instruction defines a register with the same register class
as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it
would ICE because a tail call was expecting one register class but was given
another. (The machine instruction verifier catches this situation.)
<rdar://problem/10270968>
llvm-svn: 141830
2011-10-12 23:03:40 +00:00
979009ea61
Use a utility from MathExtras to clarify a check and avoid undefined behavior. Based on patch by Ahmed Charles.
...
llvm-svn: 141829
2011-10-12 22:46:45 +00:00
000721f058
The VMAs stored in the symbol table of a MachO file are absolute addresses, not offsets from the section.
...
llvm-svn: 141828
2011-10-12 22:37:10 +00:00
66443ce9bc
Use unsigned multiply to hash integers, so we don't end up with undefined behavior for large signed integers. Based on patch by Ahmed Charles.
...
llvm-svn: 141827
2011-10-12 22:25:45 +00:00
850f7b3cdc
Removed colons from some target datalayout strings in test, since they don't match the required format.
...
llvm-svn: 141825
2011-10-12 22:24:17 +00:00
34e1707fbb
Don't label a STAB debugging symbol as a function symbol.
...
llvm-svn: 141824
2011-10-12 22:23:12 +00:00
fb02ecde5e
sectionContainsSymbol needs to be based on VMA's rather than section indices to properly account for files with segment load commands that contain no sections.
...
llvm-svn: 141822
2011-10-12 22:21:32 +00:00
154a967c23
Fix a couple hash functions so that they do not depend on undefined shifts. Based on patch by Ahmed Charles.
...
llvm-svn: 141820
2011-10-12 22:00:26 +00:00
a098a891ab
ARM addrmode5 represents the 'U' bit of the encoding backwards.
...
The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.
llvm-svn: 141819
2011-10-12 21:59:02 +00:00
d433042388
Fix APFloat::getSmallestNormalized so the shift doesn't depend on undefined behavior. Patch from Ahmed Charles.
...
llvm-svn: 141818
2011-10-12 21:56:19 +00:00
c53220134a
Fix APFloat::getLargest so that it actually returns the correct value. Found by accident while reviewing a patch to nearby code.
...
llvm-svn: 141816
2011-10-12 21:51:36 +00:00
f903c154c7
Section indices in MachO symbol tables begin at 1, not 0.
...
llvm-svn: 141815
2011-10-12 21:43:24 +00:00
e7c0c499b8
Finish supporting cpp #file/line comments in assembler for error messages. So
...
for cpp pre-processed assembly we give correct filename and line numbers when
reporting errors in assembly files when using clang and -integrated-as on .s
files. rdar://8998895
llvm-svn: 141814
2011-10-12 21:38:39 +00:00
b35afcaa56
Disable machine LICM speculation check (for profitability) until I have time to investigate the regressions.
...
llvm-svn: 141813
2011-10-12 21:33:49 +00:00
2dffcebf77
To find the exiting VN of a LiveInterval from a block, use the previous slot
...
rather than the previous index. If a block has a single instruction, the
previous index may be in a different basic block.
I have no clue how this used to work on all of test-suite, because now this
failure is seen quite often when trying to compile code with -strong-phi-elim.
This fixes PR10252.
llvm-svn: 141812
2011-10-12 21:24:54 +00:00
54a20ed0f1
Thumb2 assembly parsing and encoding for LDC/STC.
...
llvm-svn: 141811
2011-10-12 20:54:17 +00:00
f895efaa45
Hoist vector.size() computation out of the loop. No functionality change.
...
llvm-svn: 141807
2011-10-12 20:20:48 +00:00
8007320902
addrmode2 is gone from these, so no need for the reg0 operand.
...
llvm-svn: 141794
2011-10-12 18:11:24 +00:00
84cf2b8c98
ARM encoding tests for STC.
...
llvm-svn: 141787
2011-10-12 17:36:13 +00:00
483995875f
ARM parsing and encoding for the <option> form of LDC/STC instructions.
...
llvm-svn: 141786
2011-10-12 17:34:41 +00:00
d74c0e7c14
80 columns.
...
llvm-svn: 141781
2011-10-12 16:36:01 +00:00
6966411f45
Tidy up. Formatting.
...
llvm-svn: 141780
2011-10-12 16:34:37 +00:00
de239d2647
Fix a thinko that Nick noticed. The previous code actually worked as
...
intended, but only by accident.
llvm-svn: 141779
2011-10-12 15:56:56 +00:00
9bfcf77638
lib/Object/ELFObjectFile.cpp: Fix undefined behavior for MC/ELF/many-section.s not to fail (on msvc).
...
DenseMap::lookup(k) would return "default constructor value" when k was not met. It would be useless when value type were POD.
llvm-svn: 141774
2011-10-12 10:28:55 +00:00
918cea2c27
Expand the check for a landing pad so that it looks at the basic block's
...
containing loop's header to see if that's a landing pad. If it is, then we don't
want to hoist instructions out of the loop and above the header.
llvm-svn: 141767
2011-10-12 02:58:01 +00:00
35163e21dc
Use an existing function.
...
llvm-svn: 141763
2011-10-12 01:24:51 +00:00
3261c0fa6e
Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.
...
llvm-svn: 141761
2011-10-12 01:05:13 +00:00
c57febff4a
Fix encoding of 32-bit integer instructions. Change names of operands and nodes.
...
Remove unused classes.
llvm-svn: 141757
2011-10-12 00:56:06 +00:00
7c8798baea
Make this use a public accessor too.
...
llvm-svn: 141752
2011-10-12 00:38:05 +00:00
c585de670f
Add missing space.
...
llvm-svn: 141750
2011-10-12 00:14:31 +00:00
064c1c0e77
Fix indent in comment.
...
llvm-svn: 141749
2011-10-12 00:14:12 +00:00
af1389546e
Fix r141744.
...
1. The speculation check may not have been performed if the BB hasn't had a load
LICM candidate.
2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the
instruction even if it's in high register pressure situation.
llvm-svn: 141747
2011-10-12 00:09:14 +00:00
39c31a77b8
Fix -widen-vmovs liveness issues.
...
When widening a copy, we are reading a larger register that may not be
live. Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.
We now widen:
%S6<def> = COPY %S4<kill>, %D3<imp-def>
into:
%D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>
This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.
Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.
llvm-svn: 141746
2011-10-12 00:06:23 +00:00
f192ca0761
Refine r141689 with a tri-state variable.
...
Also teach MachineLICM to avoid "speculation" when register pressure is high.
llvm-svn: 141744
2011-10-11 23:48:44 +00:00
0f4ecf7548
Change name of class to ArithOverflowR.
...
llvm-svn: 141743
2011-10-11 23:43:48 +00:00
8f0d549c4c
Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical
...
instructions with two register operands derive from it.
llvm-svn: 141742
2011-10-11 23:38:52 +00:00
2d3ea9b2f2
Make this test more specific. There are 3 stats that matched "machine-licm".
...
llvm-svn: 141741
2011-10-11 23:34:31 +00:00
4035859cb8
Use public accessors on the scope that is returned.
...
llvm-svn: 141739
2011-10-11 23:19:35 +00:00
8d4f74a6b1
Fix comment.
...
llvm-svn: 141737
2011-10-11 23:12:12 +00:00
ae5a9d6578
Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit
...
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.
llvm-svn: 141736
2011-10-11 23:05:46 +00:00
7bd0ea3487
target data is a contract with the code generator, not the "processor"
...
llvm-svn: 141734
2011-10-11 23:02:17 +00:00
487974042e
improve some of the documentation around target data layout strings.
...
llvm-svn: 141733
2011-10-11 23:01:39 +00:00
6647b83087
Add a new wrapper node for a DILexicalBlock that encapsulates it and a
...
file. Since it should only be used when necessary propagate it through
the backend code generation and tweak testcases accordingly.
This helps with code like in clang's test/CodeGen/debug-info-line.c where
we have multiple #line directives within a single lexical block and want
to generate only a single block that contains each file change.
Part of rdar://10246360
llvm-svn: 141729
2011-10-11 22:59:11 +00:00
57d1692750
Formatting.
...
llvm-svn: 141728
2011-10-11 22:59:04 +00:00
cbce39c8b9
Spacing.
...
llvm-svn: 141727
2011-10-11 22:58:58 +00:00
579ff6c39c
N.B. This is with the new EH scheme:
...
The blocks with invokes have branches to the dispatch block, because that more
correctly models the behavior of the CFG. The dispatch of course has edges to
the landing pads. Those landing pads could contain invokes, which then have
branches back to the dispatch. This creates a loop. The machine LICM pass looks
at this loop and thinks it can hoist elements out of it. But because the
dispatch is an alternate entry point into the program, the hoisted instructions
won't be executed.
I wasn't able to get a testcase which was small and could reproduce all of the
time. The function_try_block.cpp in llvm-test was where this showed up.
llvm-svn: 141726
2011-10-11 22:42:31 +00:00
1c18465859
Fix function isUnalignedLoadStore.
...
llvm-svn: 141722
2011-10-11 22:04:01 +00:00
9398141c48
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
...
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
llvm-svn: 141721
2011-10-11 21:55:36 +00:00
10ae11fd57
Remove unused PatLeaf.
...
llvm-svn: 141720
2011-10-11 21:53:08 +00:00
453ac88b56
Change the names of 64-bit logical instructions so that they match the names of
...
the real instructions.
llvm-svn: 141718
2011-10-11 21:48:01 +00:00
265328baf6
Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...
...
llvm-svn: 141716
2011-10-11 21:40:47 +00:00
46a7994ac9
Remove redundancy in setcc patterns using multiclass.
...
llvm-svn: 141715
2011-10-11 21:40:01 +00:00
1a761dcfbd
Fix PR11106 by correcting a typo that has been in the code for over a year. This
...
would have never worked, since the element type of a vector type is never a
vector type. Also fix the conditional to be more direct in checking whether
EltTy is a vector type.
llvm-svn: 141713
2011-10-11 21:26:40 +00:00
8c1c51045d
Use sltiu instead of sltu when a register operand and immediate are compared.
...
llvm-svn: 141708
2011-10-11 20:44:43 +00:00
8c799c9826
Update test for r141704.
...
llvm-svn: 141705
2011-10-11 20:18:50 +00:00
12b2889989
ARM addressing mode cleanup for LDC/STC.
...
We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.
llvm-svn: 141704
2011-10-11 20:17:35 +00:00
037fc9311a
Clean up a few references to System/. We still have docs/SystemLibrary.html
...
lying around...
llvm-svn: 141703
2011-10-11 20:02:52 +00:00
55dbf03e40
Support/DataTypes.h: Clean up some types and add matching (but presumably
...
unused) code from .cmake to DataTypes.h.in so that the files are essentially in
sync module differences in autoconf/cmake replacement syntax.
llvm-svn: 141702
2011-10-11 20:02:49 +00:00
6878b1f233
Remove extra semicolon.
...
llvm-svn: 141699
2011-10-11 19:53:40 +00:00
7148bce86e
Add patterns for conditional branches with 64-bit register operands.
...
llvm-svn: 141696
2011-10-11 19:09:09 +00:00
f75add6236
Add support for 64-bit set-on-less-than instructions.
...
llvm-svn: 141695
2011-10-11 18:53:46 +00:00
4b6ac98fcf
Add support for conditional branch instructions with 64-bit register operands.
...
llvm-svn: 141694
2011-10-11 18:49:17 +00:00
453d401a51
Add dominance check for the instruction being hoisted.
...
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.
llvm-svn: 141689
2011-10-11 18:09:58 +00:00
ff2c52ce63
Fixed docs to reflect the proper default value and behaviour of the natural stack alignment.
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llvm-svn: 141687
2011-10-11 17:50:14 +00:00
27c579dba4
Expose MachOObjectFile externally, like we do for COFF. First step in reducing the amount of special-purpose code needed for llvm-objdump.
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llvm-svn: 141684
2011-10-11 17:32:27 +00:00
a95ec99a96
ARM parse alignment specifier for NEON load/store instructions.
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llvm-svn: 141682
2011-10-11 17:29:55 +00:00
1cb28fdd54
Mention the cmake build guide on the main docs page.
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llvm-svn: 141674
2011-10-11 16:35:07 +00:00
871dff76df
ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity.
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llvm-svn: 141671
2011-10-11 15:59:20 +00:00
3283793c9a
Add support for legalization of vector SHL/SRA/SRL instructions
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llvm-svn: 141667
2011-10-11 14:36:35 +00:00
e8ae98a8d9
Implement the emitFrameIndexDebugValue and getDebugValueLocation hooks.
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This fixes an assert due to the operands of the DBG_VALUE instruction not
being as expected (PR11105).
llvm-svn: 141666
2011-10-11 12:55:35 +00:00
68591286bc
Fix a iterator out of bounds error, that triggers rarely.
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llvm-svn: 141665
2011-10-11 12:55:18 +00:00
bd926cbdb5
llvm-objdump.cpp: Use PRIx64 as format specifier for int64_t.
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llvm-svn: 141664
2011-10-11 12:51:50 +00:00
c5554c9de3
Add -D__STDC_FORMAT_MACROS to use PRIx64.
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llvm-svn: 141663
2011-10-11 12:51:44 +00:00
e63cd198ba
cmake/modules/HandleLLVMOptions.cmake: Reorder __STDC_CONSTANT_MACROS and __STDC_LIMIT_MACROS.
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llvm-svn: 141662
2011-10-11 12:51:36 +00:00
198fe81571
Add support for legalization of vector trunc-store where the saved scalar type is illegal (for example, v2i16 on systems where the smallest store size is i32)
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llvm-svn: 141661
2011-10-11 11:25:16 +00:00
b521b6037b
Cleanup the trunc-store legalization code and add asserts.
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llvm-svn: 141659
2011-10-11 10:04:25 +00:00
c8a78ded33
Update to a newer doxygen version. PR8214. Patch by Jeremy Huddleston.
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llvm-svn: 141657
2011-10-11 07:25:38 +00:00
63bc541196
Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as modifying EFLAGS.
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llvm-svn: 141656
2011-10-11 07:13:09 +00:00
ffc3bd0e08
Minor modifications to make the Hello World example resemble the Hello World
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pass in the tree. Also some minor formatting changes.
PR9413
llvm-svn: 141655
2011-10-11 07:03:52 +00:00
0fbca75c17
Make Ivy Bridge 16-bit floating point conversion instructions require AVX.
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llvm-svn: 141654
2011-10-11 07:01:37 +00:00
3e01bd3b60
Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take
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that into account and test for no U's showing up in the middle, which is what
we really wanted to test for.
llvm-svn: 141653
2011-10-11 06:58:11 +00:00
603cc851f8
Test case for X86 LZCNT instruction selection.
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llvm-svn: 141652
2011-10-11 06:47:01 +00:00
271064e873
Add X86 LZCNT instruction. Including instruction selection support.
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llvm-svn: 141651
2011-10-11 06:44:02 +00:00
b4d076e37e
Use the proper name for "externally visible" linkage -- 'external'. This is the
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keyword in LLVM for externally visible linkage.
PR10636
llvm-svn: 141649
2011-10-11 06:41:28 +00:00
05d9151d2c
Reword the SetVector description to reflect reality.
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Patch by Michael Ilseman!
llvm-svn: 141648
2011-10-11 06:33:56 +00:00
ab3a9b3baf
Add a test for PR10565.
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llvm-svn: 141647
2011-10-11 06:10:37 +00:00
d7515ccc47
Remove a lot of the fancy scalar replacement code for dealing with llvm-gcc's
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lowering of NEON code. It provides little-to-no benefit now and only introduces
additional complexity.
llvm-svn: 141646
2011-10-11 06:10:30 +00:00
288ff0ec82
Test simplification that Ana Pazos noticed.
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llvm-svn: 141644
2011-10-11 04:43:15 +00:00
a697852386
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
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llvm-svn: 141642
2011-10-11 04:34:23 +00:00
29e7b315ac
Also create a shndx even if there are no symbols. This lets us test
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.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.
llvm-svn: 141641
2011-10-11 03:54:50 +00:00
ba38717f34
test/CodeGen/X86/movbe.ll: Give explicit -mtriple=x86_64-linux, to unbreak win32 hosts.
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llvm-svn: 141640
2011-10-11 03:41:03 +00:00
43f01cae95
Reapply r141605 with fixes for appropriate handling of reserved section numbers
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in st_shndx fields.
llvm-svn: 141639
2011-10-11 03:18:58 +00:00
7adc4370e0
Add support for .symtab_shnidx. Unfortunately, doing this required breaking a
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layer of abstraction around SymbolRef where you can read its private
SymbolPimpl member.
llvm-svn: 141636
2011-10-11 02:57:48 +00:00
ecbe22bb8d
Add experimental -enable-lsr-phielim option.
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I'm not sure we will need it in the long run, but the option is
currently useful for checking if the output of LSR is "clean".
llvm-svn: 141634
2011-10-11 02:30:45 +00:00
f9201c572e
Move replaceCongruentIVs into SCEVExapander and bias toward "expanded"
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IVs.
Indvars previously chose randomly between congruent IVs. Now it will
bias the decision toward IVs that SCEVExpander likes to create. This
was not done to fix any problem, it's just a welcome side effect of
factoring code.
llvm-svn: 141633
2011-10-11 02:28:51 +00:00
8782734bcc
Test cases for 64-bit load and store instructions.
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llvm-svn: 141631
2011-10-11 01:52:31 +00:00
44c78f809b
Added a testcase for r141599, rdar://problem/10063881.
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llvm-svn: 141628
2011-10-11 01:32:10 +00:00
b6d72cbeb9
Make changes necessary for supporting floating point load and store instructions
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that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
llvm-svn: 141623
2011-10-11 01:12:52 +00:00
Akira Hatanaka