Commit Graph

69592 Commits

Author SHA1 Message Date
Stepan Dyatkovskiy 5c2cc2506d MergeFunctions Pass, introduced total ordering among function attributes.
This patch belongs to patch series that improves MergeFunctions
performance time from O(N*N) to O(N*log(N)).

llvm-svn: 208953
2014-05-16 08:55:34 +00:00
Zoran Jovanovic b397fea9ab [mips][mips64r6] Add Floating Point Fused Multiply Add Subtract
Differential Revision: http://reviews.llvm.org/D3727

llvm-svn: 208952
2014-05-16 08:42:27 +00:00
Saleem Abdulrasool 056fc3da4a ARM: add some integer/floating point conversion libcalls
Add some Windows on ARM specific library calls.  These are provided by msvcrt,
and can be used to perform integer to floating-point conversions (and
vice-versa) mirroring similar functions in the RTABI.

llvm-svn: 208949
2014-05-16 05:41:33 +00:00
Juergen Ributzka 34390c70a5 Add C API for thread yielding callback.
Sometimes a LLVM compilation may take more time then a client would like to
wait for. The problem is that it is not possible to safely suspend the LLVM
thread from the outside. When the timing is bad it might be possible that the
LLVM thread holds a global mutex and this would block any progress in any other
thread.

This commit adds a new yield callback function that can be registered with a
context. LLVM will try to yield by calling this callback function, but there is
no guaranteed frequency. LLVM will only do so if it can guarantee that
suspending the thread won't block any forward progress in other LLVM contexts
in the same process.

Once the client receives the call back it can suspend the thread safely and
resume it at another time.

Related to <rdar://problem/16728690>

llvm-svn: 208945
2014-05-16 02:33:15 +00:00
Justin Bogner a119f32344 ProfileData: Allow multiple profiles in RawInstrProfReader
Allow multiple raw profiles to coexist in a single .profraw file,
given the following conditions:

- Zero padding at the end of or between profiles will be skipped.
- Each profile must start with a valid header.
- Mixing endianness or pointer sizes in concatenated profiles files is
  not allowed.

This is needed to handle cases where a program's shared libraries are
profiled as well as the main executable itself, as we'll need to emit
each executable's counters. Combining the tables in the runtime would
be expensive for the instrumented program.

rdar://16918688

llvm-svn: 208938
2014-05-16 00:38:00 +00:00
Eric Christopher c21d3d5f90 Remove the Options query functions and just access our Options directly.
llvm-svn: 208937
2014-05-16 00:32:52 +00:00
Reid Kleckner d20c970aac musttail: Fix the verification of alignment attributes
Previously this would fail with an assertion failure when trying to add
an alignment attribute without a value.

llvm-svn: 208935
2014-05-15 23:58:57 +00:00
Jiangning Liu 932e1c3924 Implement global merge optimization for global variables.
This commit implements two command line switches -global-merge-on-external
and -global-merge-aligned, and both of them are false by default, so this
optimization is disabled by default for all targets.

For ARM64, some back-end behaviors need to be tuned to get this optimization
further enabled.

llvm-svn: 208934
2014-05-15 23:45:42 +00:00
David Blaikie 962c9a2d54 DebugInfo: Follow up to r208930, comment usage of 'using' to bring in base class overload.
Code review feedback from Eric Christopher.

llvm-svn: 208933
2014-05-15 23:29:53 +00:00
Eric Christopher 5d376066df Move more MC options into the MCTargetOptions structure.
No functional change.

llvm-svn: 208932
2014-05-15 23:27:49 +00:00
Eric Christopher 98dcb8c6b1 Remove unused llvm namespace bool variable.
llvm-svn: 208931
2014-05-15 23:27:44 +00:00
David Blaikie bc094f387b DebugInfo: Don't put fission type units in comdat sections.
Since type units in the dwo file are handled by a debug aware tool, they
don't need to leverage the ELF comdat grouping to implement
deduplication. Avoid creating all the .group sections for these as a
space optimization.

llvm-svn: 208930
2014-05-15 23:18:15 +00:00
Reed Kotler 6280d9711d Finish materialize for ints
Summary: We add code to materialize all integer literals.

Test Plan: simplestorei.ll

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3596

llvm-svn: 208923
2014-05-15 21:54:15 +00:00
Matt Arsenault d504a74e3c Use range for
llvm-svn: 208922
2014-05-15 21:44:05 +00:00
Alexey Samsonov dce67348a8 [DWARF parser] Use enums instead of bitfields in DILineInfoSpecifier.
It is more appropriate than the current situation, when one flag
(AbsoluteFilePath) is relevant only if another flag is set.

This refactoring would also simplify fetching the short function name
(stored in DW_AT_name) instead of a linkage name returned currently.

No functionality change.

llvm-svn: 208921
2014-05-15 21:24:32 +00:00
Reid Kleckner 900d46ff39 Don't insert lifetime.end markers between a musttail call and ret
The allocas going out of scope are immediately killed by the return
instruction.

This is a resend of r208912, which was committed accidentally.

Reviewers: chandlerc

Differential Revision: http://reviews.llvm.org/D3792

llvm-svn: 208920
2014-05-15 21:10:46 +00:00
Reid Kleckner b16564109b Revert "Don't insert lifetime.end markers between a musttail call and ret"
This reverts commit r208912.

It was committed accidentally without review.

llvm-svn: 208914
2014-05-15 20:41:05 +00:00
Reid Kleckner 6af21245eb Remove unused variable in inliner
We have to iterate over all the calls that were inlined to find out if
any were musttail.

Sink another variable down to where its used.

llvm-svn: 208913
2014-05-15 20:39:42 +00:00
Reid Kleckner 26ab7ead45 Don't insert lifetime.end markers between a musttail call and ret
The allocas going out of scope are immediately killed by the return
instruction.

Reviewers: chandlerc

Differential Revision: http://reviews.llvm.org/D3630

llvm-svn: 208912
2014-05-15 20:39:13 +00:00
David Blaikie 4c6d987b06 DebugInfo: Simplify retrieving filename/directory name for line table entry building.
llvm-svn: 208911
2014-05-15 20:18:50 +00:00
Reid Kleckner f0915aa0e6 Teach the inliner how to preserve musttail invariants
The interesting case is what happens when you inline a musttail call
through a musttail call site.  In this case, we can't break perfect
forwarding or allow any stack growth.

Instead of merging control flow from the inlined return instruction
after a musttail call into the body of the caller, leave the inlined
return instruction in the caller so that the musttail call stays in the
tail position.

More work is required in http://reviews.llvm.org/D3630 to handle the
case where the inlined function has dynamic allocas or byval arguments.

Reviewers: chandlerc

Differential Revision: http://reviews.llvm.org/D3491

llvm-svn: 208910
2014-05-15 20:11:28 +00:00
David Blaikie 6c21716439 DebugInfo: Add FIXME regarding DILexicalBlock uniquing fields.
llvm-svn: 208909
2014-05-15 20:09:55 +00:00
Simon Atanasyan 8d59c8da41 [obj2yaml][ELF] Do not print empty Link and Info fields for ELF sections.
llvm-svn: 208905
2014-05-15 18:04:02 +00:00
Juergen Ributzka bcbed0a549 Revert "[PM] Add pass run listeners to the pass manager."
Revert the current implementation and C API. New implementation and C APIs are
in the works.

llvm-svn: 208904
2014-05-15 17:49:20 +00:00
Bradley Smith 597122b026 [ARM64] Improve diagnostics for Cn operands in SYS instructions
llvm-svn: 208902
2014-05-15 16:28:32 +00:00
Andrea Di Biagio d621120533 [X86] Teach the backend how to fold SSE4.1/AVX/AVX2 blend intrinsics.
Added target specific combine rules to fold blend intrinsics according
to the following rules:
 1) fold(blend A, A, Mask) -> A;
 2) fold(blend A, B, <allZeros>) -> A;
 3) fold(blend A, B, <allOnes>) -> B.

Added two new tests to verify that the new folding rules work for all
the optimized blend intrinsics.

llvm-svn: 208895
2014-05-15 15:18:15 +00:00
Zoran Jovanovic d6879febdc [mips][mips64r6] Add CLASS.fmt instructions
Differential Revision: http://reviews.llvm.org/D3712

llvm-svn: 208894
2014-05-15 15:16:36 +00:00
Zoran Jovanovic bdf1cd374f [mips][mips64r6] Add RINT.fmt instructions
Differential Revision: http://reviews.llvm.org/D3711

llvm-svn: 208892
2014-05-15 15:04:37 +00:00
Zoran Jovanovic 702d27e4db [mips][mips64r6] Add SELEQZ/SELNEZ.fmt instructions
Differential Revision: http://reviews.llvm.org/D3710

llvm-svn: 208891
2014-05-15 14:58:42 +00:00
Zoran Jovanovic 11d4ce1788 [mips][mips64r6] Add MAX/MIN/MAXA/MINA.fmt instructions
Differential Revision: http://reviews.llvm.org/D3709

llvm-svn: 208890
2014-05-15 14:54:06 +00:00
Tom Stellard 436780bebb R600/SI: Stop using VSrc_* as the default register class for types.
We now use SReg_* for integer types and VReg_* for floating-point types.
This should help simplify the SIFixSGPRCopies pass and no longer causes
ISel to insert a COPY after termiator instuctions that output a value.

This change is covered by exisitng tests.

llvm-svn: 208888
2014-05-15 14:41:57 +00:00
Tom Stellard a568738b47 R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopies
This prevents a future commit from regressing the load-i1.ll test.

llvm-svn: 208887
2014-05-15 14:41:55 +00:00
Tom Stellard 73b98ed8cf R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0
llvm-svn: 208886
2014-05-15 14:41:54 +00:00
Tom Stellard 365a2b49f2 R600/SI: Use VALU instructions for i1 ops
llvm-svn: 208885
2014-05-15 14:41:50 +00:00
Tim Northover 60091cfeb9 TableGen: use correct MIOperand when printing aliases
Previously, TableGen assumed that every aliased operand consumed precisely 1
MachineInstr slot (this was reasonable because until a couple of days ago,
nothing more complicated was eligible for printing).

This allows a couple more ARM64 aliases to print so we can remove the special
code.

On the X86 side, I've gone for explicit AT&T size specifiers as the default, so
turned off a few of the aliases that would have just started printing.

llvm-svn: 208880
2014-05-15 13:36:01 +00:00
Daniel Sanders e17212d621 [mips][mips64r6] Add bitswap, and dbitswap
Summary: Depends on D3728

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3729

llvm-svn: 208877
2014-05-15 12:18:23 +00:00
Jay Foad 5a29c367f7 Instead of littering asserts throughout the code after every call to
computeKnownBits, consolidate them into one assert at the end of
computeKnownBits itself.

llvm-svn: 208876
2014-05-15 12:12:55 +00:00
Tim Northover 2509a3fc64 ARM64: print correct aliases for NEON mov & mvn instructions
In all cases, if a "mov" alias exists, it is the canonical form of the
instruction. Now that TableGen can support aliases containing syntax variants,
we can enable them and improve the quality of the asm output.

llvm-svn: 208874
2014-05-15 12:11:02 +00:00
Daniel Sanders 01124a0132 [mips][mips64r6] Add align and dalign
Summary: Depends on D3689

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D3728

llvm-svn: 208872
2014-05-15 12:06:36 +00:00
Tim Northover d8d65a69cf TableGen/ARM64: print aliases even if they have syntax variants.
To get at least one use of the change (and some actual tests) in with its
commit, I've enabled the AArch64 & ARM64 NEON mov aliases.

llvm-svn: 208867
2014-05-15 11:16:32 +00:00
Tim Northover dd8fca5136 ARM64: add correct vector registers during asm parsing
Previously, we ignored the difference between V64 and V128 when parsing
assembly: they both got mapped to registers in the FPR128 class. This is
basically harmless at the moment because they both print and encode the same
way. However, it will affect the printing of aliases.

llvm-svn: 208866
2014-05-15 11:16:19 +00:00
Bradley Smith 5c44b08912 [ARM64] Improve load/store diagnostics and forbid 32-bit register addresses
llvm-svn: 208864
2014-05-15 11:08:30 +00:00
Bradley Smith e0483f9cd1 [ARM64] Parse fixed vector lanes properly so that diagnostics can be emitted
llvm-svn: 208863
2014-05-15 11:07:57 +00:00
Bradley Smith c294914adc [ARM64] Add/Fixup diagnostics for floating point immediates
llvm-svn: 208862
2014-05-15 11:07:28 +00:00
Bradley Smith 3d1a9ef162 [ARM64] Add condition code operand type such that proper diagnostics can be emitted
llvm-svn: 208861
2014-05-15 11:06:51 +00:00
Bradley Smith 13a76e5b88 [ARM64] Add more simple diagnostics for immediate/shift ranges
llvm-svn: 208860
2014-05-15 11:06:16 +00:00
Daniel Sanders b59e1a41f4 [mips][mips64r6] Add addiupc, aluipc, and auipc
Summary:
No support for symbols in place of the immediate yet since it requires new
relocations.

Depends on D3671

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3689

llvm-svn: 208858
2014-05-15 10:45:58 +00:00
Daniel Sanders a3412b13d4 [mips][mips64r6] Add aui, daui, dahi, and dati
Summary: Depends on D3671

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3759

llvm-svn: 208857
2014-05-15 10:27:19 +00:00
Chandler Carruth a0e5695ad9 Teach the constant folder to look through bitcast constant expressions
much more effectively when trying to constant fold a load of a constant.
Previously, we only handled bitcasts by trying to find a totally generic
byte representation of the constant and use that. Now, we look through
the bitcast to see what constant we might fold the load into, and then
try to form a constant expression cast of the found value that would be
equivalent to loading the value.

You might wonder why on earth this actually matters. Well, turns out
that the Itanium ABI causes us to create a single array for a vtable
where the first elements are virtual base offsets, followed by the
virtual function pointers. Because the array is homogenous the element
type is consistently i8* and we inttoptr the virtual base offsets into
the initial elements.

Then constructors bitcast these pointers to i64 pointers prior to
loading them. Boom, no more constant folding of virtual base offsets.
This is the first fix to LLVM to address the *insane* performance Eric
Niebler discovered with Clang on his range comprehensions[1]. There is
more to come though, this doesn't *really* fix the problem fully.

[1]: http://ericniebler.com/2014/04/27/range-comprehensions/

llvm-svn: 208856
2014-05-15 09:56:28 +00:00
Daniel Sanders 19627f470b [mips][mips64r6] Test that branch likelies are not accepted on MIPS64r6.
Summary:
They aren't implemented for any ISA at the moment.

Depends on D3670

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3671

llvm-svn: 208855
2014-05-15 09:47:43 +00:00