to reflect the new license.
We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.
Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.
llvm-svn: 351636
When clang is running on windows, /dev/null is not available. Use nul as empty input file instead.
Differential Revision: https://reviews.llvm.org/D56225
llvm-svn: 350885
AMDGPU backend will switch to code object version 3 by default.
Since HIP runtime is not ready, disable it until the runtime is ready.
Differential Revision: https://reviews.llvm.org/D53325
llvm-svn: 344630
No longer use irif amdgcn library, instead we will use the previous fence functions from new hip.amdgcn.bc bitcode library. Update hip-device-libs.hip test as well.
llvm-svn: 344281
This patch renames -f{no-}cuda-rdc to -f{no-}gpu-rdc and keeps the original
options as aliases. When -fgpu-rdc is off,
clang will assume the device code in each translation unit does not call
external functions except those in the device library, therefore it is possible
to compile the device code in each translation unit to self-contained kernels
and embed them in the host object, so that the host object behaves like
usual host object which can be linked by lld.
The benefits of this feature is: 1. allow users to create static libraries which
can be linked by host linker; 2. amortized device code linking time.
This patch modifies HIP action builder to insert actions for linking device
code and generating HIP fatbin, and pass HIP fatbin to host backend action.
It extracts code for constructing command for generating HIP fatbin as
a function so that it can be reused by early finalization. It also modifies
codegen of HIP host constructor functions to embed the device fatbin
when it is available.
Differential Revision: https://reviews.llvm.org/D52377
llvm-svn: 343611
AMDGPU target need -fvisibility hidden option for clang to
work around a limitation of no PLT support, otherwise there is compilation
error at -O0.
Differential Revision: https://reviews.llvm.org/D51434
llvm-svn: 341077
Summary:
HIP should link the bitcodes with caller functions before callee functions. Also added lit test to check the ordering of the linked bitcodes is matches.
Reviewers: yaxunl, b-sumner
Reviewed By: yaxunl, b-sumner
Subscribers: cfe-commits, yaxunl, b-sumner, scchan
Differential Revision: https://reviews.llvm.org/D48667
llvm-svn: 335774
Summary:
Use oclc_daz_opt_on.amdgcn.bc bitcode when option fcuda-flush-denormal-to-zero is enabled, otherwise use oclc_daz_opt_off.amdgcn.bc bitcode. Added lit tests to verify that the correct bitcode is linked when -fcuda-flush-denormal-to-zero option is enabled or disabled.
Reviewers: yaxunl, scchan, b-sumner
Reviewed By: yaxunl, scchan, b-sumner
Subscribers: cfe-commits, yaxunl
Differential Revision: https://reviews.llvm.org/D48493
llvm-svn: 335765
Summary:
The hc.amdgcn.bc and hip.amdgcn.bc are removed in VDI build and no longer needed.
Reviewers: yaxunl
Reviewed By: yaxunl
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D48455
llvm-svn: 335634
This patch adds HIP toolchain to support HIP language mode. It includes:
Create specific compiler jobs for HIP.
Choose specific libraries for HIP.
With contribution from Greg Rodgers.
Differential Revision: https://reviews.llvm.org/D45212
llvm-svn: 333484
Chandler Carruth