Commit Graph

119 Commits

Author SHA1 Message Date
Rui Ueyama 5ba7266761 Simplify PPC64::calcEFlags().
In this file we only have to handle the v2 ABI, so what we need to do
is to just make sure that all object files have v2 or unspecified version
number.

Differential Revision: https://reviews.llvm.org/D48112

llvm-svn: 336372
2018-07-05 16:58:42 +00:00
Zaara Syeda de54f584cc [PPC64] Add support for R_PPC64_GOT_DTPREL16* relocations
The local dynamic TLS access on PPC64 ELF v2 ABI uses R_PPC64_GOT_DTPREL16*
relocations when a TLS variables falls outside 2 GB of the thread storage
block. This patch adds support for these relocations by adding a new RelExpr
called R_TLSLD_GOT_OFF which emits a got entry for the TLS variable relative
to the dynamic thread pointer using the relocation R_PPC64_DTPREL64. It then
evaluates the R_PPC64_GOT_DTPREL16* relocations as the got offset for the
R_PPC64_DTPREL64 got entries.

Differential Revision: https://reviews.llvm.org/D48484

llvm-svn: 335732
2018-06-27 13:55:41 +00:00
Zaara Syeda 1cdd816c12 [PPC64] Add TLS global dynamic to local exec relaxation
This patch adds the target call back relaxTlsGdToLe to support TLS relaxation
from global dynamic to local exec model.

The relaxation performs the following transformation:
addis r3, r2, x@got@tlsgd@ha --> nop
addi r3, r3, x@got@tlsgd@l   --> addis r3, r13, x@tprel@ha
bl __tls_get_addr(x@tlsgd)   --> nop
nop                          --> addi r3, r3, x@tprel@l

Differential Revision: https://reviews.llvm.org/D48082

llvm-svn: 335730
2018-06-27 13:27:29 +00:00
Sean Fertile f60cb34c91 [PPC64] Thread-local storage general-dynamic to initial-exec relaxation.
Patch adds support for relaxing the general-dynamic tls sequence to
initial-exec.

the relaxation performs the following transformation:
addis r3, r2, x@got@tlsgd@ha --> addis r3, r2, x@got@tprel@ha
addi r3, r3, x@got@tlsgd@l   --> ld r3, x@got@tprel@l(r3)
bl __tls_get_addr(x@tlsgd)   --> nop
nop                          --> add r3, r3, r13

and instead of emitting a DTPMOD64/DTPREL64 pair for x, we emit a single
R_PPC64_TPREL64.

Differential Revision: https://reviews.llvm.org/D48090

llvm-svn: 335651
2018-06-26 19:38:18 +00:00
Fangrui Song 4ff63648ad [ELF][X86_64] Use R_GOTREL_FROM_END instead of R_GOTREL for R_X86_64_GOTOFF64
Summary:
R_X86_64_GOTOFF64: S + A - GOT
R_X86_64_GOTPC{32,64}: GOT + A - P (R_GOTONLY_PC_FROM_END)

R_X86_64_GOTOFF64 should use R_GOTREL_FROM_END so that in conjunction with
R_X86_64_GOTPC{32,64}, the `GOT` term is neutralized. This also matches
the handling of R_386_GOTOFF (S + A - GOT).

Reviewers: ruiu, espindola

Subscribers: emaste, arichardson, llvm-commits

Differential Revision: https://reviews.llvm.org/D48095

llvm-svn: 334672
2018-06-13 23:29:28 +00:00
Rui Ueyama 1ebde333e8 Remove needless bitwise-AND.
Because applyMask ignores upper bits, we don't need to mask them.

llvm-svn: 334647
2018-06-13 19:58:33 +00:00
Rui Ueyama 3cc4a0825b Make a function non-member because it doesn't depend on any class.
llvm-svn: 334646
2018-06-13 19:50:10 +00:00
Rui Ueyama 803ffdbc7b Apply clang-format.
llvm-svn: 334645
2018-06-13 19:49:58 +00:00
Sid Manning 95b0c2e1e3 Add Hexagon Support
Differential Revision: https://reviews.llvm.org/D47791

llvm-svn: 334637
2018-06-13 18:45:25 +00:00
Rui Ueyama 92b931d519 Use shorter names for #lo, #hi, #ha, etc. NFC.
Since these functions are file-local, the new names shouldn't be ambiguous.

Differential Revision: https://reviews.llvm.org/D48093

llvm-svn: 334564
2018-06-13 00:50:17 +00:00
Rui Ueyama 864289990a Handle R_X86_64_GOTOFF64.
R_X86_64_GOTOFF64 is a relocation type to set to a distance betwween
a symbol and the beginning of the .got section. Previously, we always
created a dynamic relocation for the relocation type even though it
can be resolved at link-time.

Creating a dynamic relocation for R_X86_64_GOTOFF64 caused link failure
for some programs that do have a relocation of the type in a .text
section, as text relocations are prohibited in most configurations.

Differential Revision: https://reviews.llvm.org/D48058

llvm-svn: 334534
2018-06-12 20:27:16 +00:00
Fangrui Song 3773c196fc [ELF][PPC64] Support R_PPC64_DTPREL64 which may be emitted in .rela.debug_addr
llvm-svn: 334533
2018-06-12 20:26:49 +00:00
Fangrui Song aa473c5387 [ELF] Support R_X86_64_GOTPC{32,64}
Reviewers: ruiu, grimar, espindola

Subscribers: emaste, arichardson, llvm-commits

Differential Revision: https://reviews.llvm.org/D47098

llvm-svn: 334532
2018-06-12 20:18:41 +00:00
Sean Fertile e6b2e06f28 [PPC64] Support R_PPC64_DTPREL relocations.
Patch adds support for most of the dynamic thread pointer based relocations
for local-dynamic tls. The HIGH and HIGHA versions are missing becuase they
are not supported by the llvm integrated assembler yet.

llvm-svn: 334465
2018-06-12 01:47:02 +00:00
Konstantin Zhuravlyov d70c367267 AMDGPU/LLD: Handle R_AMDGPU_REL64 relocation
Requires r334443 from llvm

Differential Revision: https://reviews.llvm.org/D47734

llvm-svn: 334444
2018-06-11 21:42:53 +00:00
Zaara Syeda 4455b37666 [PPC64] Add support for local-exec TLS model
This patch adds the relocations needed support the local-exec TLS model:

R_PPC64_TPREL16
R_PPC64_TPREL16_HA
R_PPC64_TPREL16_LO
R_PPC64_TPREL16_HI
R_PPC64_TPREL16_DS
R_PPC64_TPREL16_LO_DS
R_PPC64_TPREL16_HIGHER
R_PPC64_TPREL16_HIGHERA
R_PPC64_TPREL16_HIGHEST
R_PPC64_TPREL16_HIGHESTA

Differential Revision: https://reviews.llvm.org/D47598

llvm-svn: 334304
2018-06-08 17:04:09 +00:00
Zaara Syeda e4da09f920 [PPC64] Add support for initial-exec TLS model
This patch adds the relocations needed support the initial-exec TLS model:
R_PPC64_GOT_TPREL16_HA
R_PPC64_GOT_TPREL16_LO_DS
R_PPC64_GOT_TPREL16_DS
R_PPC64_GOT_TPREL16_HI
R_PPC64_TLS

Differential Revision: https://reviews.llvm.org/D47455

llvm-svn: 333769
2018-06-01 15:20:56 +00:00
Sean Fertile 1a8343fce3 [PPC64] Support R_PPC64_GOT_TLSLD16 relocations.
Add support for the R_PPC64_GOT_TLSLD16 relocations used to build the address of
the tls_index struct used in local-dynamic tls.

Differential Revision: https://reviews.llvm.org/D47538

llvm-svn: 333681
2018-05-31 18:44:12 +00:00
Sean Fertile fb613e552a Rename R_TLSGD/R_TLSLD to add _GOT_FROM_END. NFC.
getRelocTargetVA for R_TLSGD and R_TLSLD RelExprs calculate an offset from the
end of the got, so adjust the names to reflect this.

Differential Revision: https://reviews.llvm.org/D47379

llvm-svn: 333674
2018-05-31 18:07:06 +00:00
Sean Fertile ef0f7496d1 [PPC64] Support General-Dynamic tls.
Adds handling of all the relocation types for general-dynamic thread local
storage.

Differential Revision: https://reviews.llvm.org/D47325

llvm-svn: 333420
2018-05-29 14:34:38 +00:00
Rui Ueyama 1fa3c728b9 Fix retpoline PLT for x86-64 when used for >4GB address.
Previously, we wrote only the least significant 32 bits.

llvm-svn: 333313
2018-05-25 21:14:45 +00:00
Rui Ueyama 95d6ca52ac Add a comment for retpoline PLT.
llvm-svn: 333312
2018-05-25 21:02:47 +00:00
Rui Ueyama 7ae70fc14a Fix a bug that we truncated GOTPLT entries to 32 bits.
llvm-svn: 333294
2018-05-25 18:26:14 +00:00
Sean Fertile fd69969e54 [PPC64] Set the IRelative relocation type.
Set the IRelative relocation type and extend the related test to verify.
Differential Revision: https://reviews.llvm.org/D46877

llvm-svn: 333203
2018-05-24 16:32:14 +00:00
Benjamin Kramer 5455038d98 [lld] Make helpers static. NFC.
llvm-svn: 332408
2018-05-15 22:01:54 +00:00
Zaara Syeda 6b8b868db5 [ELF][PPC64] Fix getRelExpr for R_PPC64_REL64
The relocation R_PPC64_REL64 should return R_PC for getRelExpr since it
computes S + A - P.

Differential Revision: https://reviews.llvm.org/D46766

llvm-svn: 332259
2018-05-14 16:39:45 +00:00
Zaara Syeda c87e16718f [ELF][PPC64] Fix getRelExpr for R_PPC64_REL32
The relocation R_PPC64_REL32 should return R_PC for getRelExpr since it
computes S + A - P.

Differential Revision: https://reviews.llvm.org/D46586

llvm-svn: 332252
2018-05-14 15:26:44 +00:00
Sean Fertile 49914cc807 [PPC64] Add lazy symbol resolution stubs.
Adds support for .glink resolver stubs from the example implementation in the V2
ABI (Section 4.2.5.3. Procedure Linkage Table). The stubs are written to the
PltSection, and the sections are renamed to match the PPC64 ABI:
    .got.plt --> .plt    Type = SHT_NOBITS
    .plt     --> .glink

And adds the DT_PPC64_GLINK dynamic tag to the dynamic section when the plt is
not empty.

Differential Revision: https://reviews.llvm.org/D45642

llvm-svn: 331840
2018-05-09 02:07:53 +00:00
Sean Fertile d2e887d2f6 [PPC64] Emit plt call stubs to the text section rather then the plt section.
On PowerPC calls to functions through the plt must be done through a call stub
that is responsible for:
1) Saving the toc pointer to the stack.
2) Loading the target functions address from the plt into both r12 and the
   count register.
3) Indirectly branching to the target function.

Previously we have been emitting these call stubs to the .plt section, however
the .plt section should be reserved for the lazy symbol resolution stubs. This
patch moves the call stubs to the text section by moving the implementation from
writePlt to the thunk framework.

Differential Revision: https://reviews.llvm.org/D46204

llvm-svn: 331607
2018-05-06 19:13:29 +00:00
Simon Atanasyan b6211d9084 [ELF][MIPS] Reorganize isMipsPIC routine. NFC
llvm-svn: 331555
2018-05-04 20:48:53 +00:00
Zaara Syeda edc7a8c1e5 [PPC64] Remove support for ELF V1 ABI in LLD - buildbot fix
Fix buildbot error, failure to build with msvc due to error C2446
Use switch instead of ternary operator.

Differential Revision: https://reviews.llvm.org/D46316

llvm-svn: 331534
2018-05-04 16:04:04 +00:00
Zaara Syeda f61b0733a8 [PPC64] Remove support for ELF V1 ABI in LLD
The current support for V1 ABI in LLD is incomplete.
This patch removes V1 ABI support and changes the default behavior to V2 ABI,
issuing an error when using the V1 ABI. It also updates the testcases to V2
and removes any V1 specific tests.

Differential Revision: https://reviews.llvm.org/D46316

llvm-svn: 331529
2018-05-04 15:09:49 +00:00
Peter Smith e72d3d32bb [ELF][AArch64] Implement the AArch64 TLSLD_LDST_LO12 family of relocs
Implement the following relocations for AArch64:
R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC

These are specified in ELF for the 64-bit Arm Architecture.

Fixes pr36727

Differential Revision: https://reviews.llvm.org/D46255

llvm-svn: 331511
2018-05-04 08:53:34 +00:00
Simon Atanasyan bc4da23133 [ELF][MIPS] Check that a section has a valid reference to a file in the isMipsPIC routine
llvm-svn: 331470
2018-05-03 17:33:10 +00:00
Peter Smith 2e54353b86 [LLD][AArch64] Simplify relocations sharing same encoding [NFC]
The code to encode the result in relocateOne for the relocations:
R_AARCH64_LD64_GOT_LO12_NC
R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
R_AARCH64_TLSDESC_LD64_LO12

is equivalent to that for R_AARCH64_LDST64_ABS_LO12_NC. This is described
in the ABI as "Set the LD/ST immediate field bits [11:3] of X. No overflow
check; check that X&7 =0.
    
Differential Revision: https://reviews.llvm.org/D46247

llvm-svn: 331452
2018-05-03 12:59:52 +00:00
Rafael Espindola a59aacf52b Fix trap instruction on pp64.
The test was passing on a big endian host, but just because od with x4
was compensating for it.

llvm-svn: 330386
2018-04-20 01:21:24 +00:00
George Rimar f9936e1fc9 [ELF] - Eliminate Target::isPicRel method.
As was mentioned in comments for D45158,
isPicRel's name does not make much sense,
because what this method does is checks if
we need to create the dynamic relocation or not.

Instead of renaming it to something different,
we can 'isPicRel' completely.

We can reuse the getDynRel method.
They are logically very close, getDynRel can just return
R_*_NONE in case no dynamic relocation should be produced
and that would simplify things and avoid functionality
correlation/duplication with 'isPicRel'.

The patch does this change.

Differential revision: https://reviews.llvm.org/D45248

llvm-svn: 329275
2018-04-05 12:07:20 +00:00
George Rimar 785a79133b [ELF] - X86_64: Use white list for relocations checked by isPicRel.
isPicRel is used to check if we want to create the dynamic relocations.
Not all of the dynamic relocations we create are passing through this
check, but those that are, probably better be whitelisted.

Differential revision: https://reviews.llvm.org/D45252

llvm-svn: 329203
2018-04-04 15:21:21 +00:00
George Rimar bc1d58a6b1 [ELF] - Relax checks for R_386_8/R_386_16 relocations.
This fixes PR36927.

The issue is next. Imagine we have -Ttext 0x7c and code below.

.code16
.global _start
_start:
movb $_start+0x83,%ah

So we have R_386_8 relocation and _start at 0x7C.
Addend is 0x83 == 131. We will sign extend it to 0xffffffffffffff83.

Now, 0xffffffffffffff83 + 0x7c gives us 0xFFFFFFFFFFFFFFFF.
Techically 0x83 + 0x7c == 0xFF, we do not exceed 1 byte value, but
currently LLD errors out, because we use checkUInt<8>.

Let's try to use checkInt<8> now and the following code to see if it can help (no):
main.s:
.byte foo

input.s:
.globl foo
.hidden foo
foo = 0xff

Here, foo is 0xFF. And addend is 0x0. Final value is 0x00000000000000FF.
Again, it fits one byte well, but with checkInt<8>,
we would error out it, so we can't use it.

What we want to do is to check that the result fits 1 byte well.
Patch changes the check to checkIntUInt to fix the issue.

Differential revision: https://reviews.llvm.org/D45051

llvm-svn: 329061
2018-04-03 12:19:04 +00:00
George Rimar c6735c23d2 [ELF] - X86_64: don't allow 8/16 bit dynamic relocations.
Having 8/16 bits dynamic relocations is incorrect.

Both gold and bfd (built from latest sources) disallow
that too.

Differential revision: https://reviews.llvm.org/D45158

llvm-svn: 329059
2018-04-03 11:58:23 +00:00
Rafael Espindola 3e7d6fc2c6 Define TrapInst for ppc64.
This is nice for testing since it is the first TrapInst whose bytes
are not all the same.

llvm-svn: 329014
2018-04-02 21:11:13 +00:00
Sean Fertile 227d4399bf [PPC64] Minor changes for Plt relocations.
The Plt relative relocations are R_PPC64_JMP_SLOT in the V2 abi, and we only
reserve 2 double words instead of 3 at the start of the array of PLT entries for
lazy linking.

Differential Revision: https://reviews.llvm.org/D44951

llvm-svn: 329006
2018-04-02 19:47:21 +00:00
Sean Fertile af95629deb [PPC64] Write plt stubs for ElfV2 abi
Add the default version of a plt stub for the V2 Elf abi.

Differential Revision: https://reviews.llvm.org/D44850

llvm-svn: 329004
2018-04-02 19:17:12 +00:00
Rui Ueyama f001ead490 Do not use template for check{Int,UInt,IntUInt,Alignment}.
Template is just unnecessary.

Differential Revision: https://reviews.llvm.org/D45063

llvm-svn: 328843
2018-03-29 22:40:52 +00:00
Andrew Ng fe1d346f99 [ELF] Fix X86 & X86_64 PLT retpoline padding
The PLT retpoline support for X86 and X86_64 did not include the padding
when writing the header and entries. This issue was revealed when linker
scripts were used, as this disables the built-in behaviour of filling
the last page of executable segments with trap instructions. This
particular behaviour was hiding the missing padding.

Added retpoline tests with linker scripts.

Differential Revision: https://reviews.llvm.org/D44682

llvm-svn: 328777
2018-03-29 14:03:01 +00:00
Zaara Syeda 5dd6bd9631 [ELF][PPC64] Fix getRelExpr for R_PPC64_REL16_LO and R_PPC64_REL16_HA
The relocations R_PPC64_REL16_LO and R_PPC64_REL16_HA should return R_PC
for getRelExpr since they compute #lo(S + A – P) and #ha(S + A – P).

Differential Revision: https://reviews.llvm.org/D44648

llvm-svn: 328103
2018-03-21 15:04:04 +00:00
Zaara Syeda 52ed6eb8d9 [ELF] Add basic support for PPC LE
This patch adds changes to start supporting the Power 64-Bit ELF V2 ABI.
This includes:
- Changing the ElfSym::GlobalOffsetTable to be named .TOC.
- Creating a GotHeader so the first entry in the .got is .TOC.
- Setting the e_flags to be 1 for ELF V1 and 2 for ELF V2

Differential Revision: https://reviews.llvm.org/D44483

llvm-svn: 327871
2018-03-19 17:40:14 +00:00
Peter Smith 3d044f57d4 [ELF] Recommit 327248 with Arm using the .got for _GLOBAL_OFFSET_TABLE_
This is the same as 327248 except Arm defining _GLOBAL_OFFSET_TABLE_ to
be the base of the .got section as some existing code is relying upon it.

For most Targets the _GLOBAL_OFFSET_TABLE_ symbol is expected to be at
the start of the .got.plt section so that _GLOBAL_OFFSET_TABLE_[0] =
reserved value that is by convention the address of the dynamic section.
Previously we had defined _GLOBAL_OFFSET_TABLE_ as either the start or end
of the .got section with the intention that the .got.plt section would
follow the .got. However this does not always hold with the current
default section ordering so _GLOBAL_OFFSET_TABLE_[0] may not be consistent
with the reserved first entry of the .got.plt.

X86, X86_64 and AArch64 will use the .got.plt. Arm, Mips and Power use .got

Fixes PR36555

Differential Revision: https://reviews.llvm.org/D44259

llvm-svn: 327823
2018-03-19 06:52:51 +00:00
Peter Collingbourne 5c902845e5 Revert r327248, "For most Targets the _GLOBAL_OFFSET_TABLE_ symbol is expected to be at"
This change broke ARM code that expects to be able to add
_GLOBAL_OFFSET_TABLE_ to the result of an R_ARM_REL32.

I will provide a reproducer on llvm-commits.

llvm-svn: 327688
2018-03-16 01:01:44 +00:00
Rafael Espindola 74acdfa691 Reduce code duplication a bit.
The code for computing the offset of an entry in the plt is simple,
but it was duplicated in quite a few places.

llvm-svn: 327536
2018-03-14 17:41:34 +00:00