434d4599d4
[AArch64] Implement vector splitting on UADDV.
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Summary: Fixes PR25056.
Reviewers: mcrosier, junbuml, jmolloy
Subscribers: aemerson, rengolin, llvm-commits
Differential Revision: http://reviews.llvm.org/D13466
llvm-svn: 250520
2015-10-16 15:38:25 +00:00
0aace13d18
Improve ISel across lane float min/max reduction
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In vectorized float min/max reduction code, the final "reduce" step
is sub-optimal. In AArch64, this change wll combine :
svn0 = vector_shuffle t0, undef<2,3,u,u>
fmin = fminnum t0,svn0
svn1 = vector_shuffle fmin, undef<1,u,u,u>
cc = setcc fmin, svn1, ole
n0 = extract_vector_elt cc, #0
n1 = extract_vector_elt fmin, #0
n2 = extract_vector_elt fmin, #1
result = select n0, n1,n2
into :
result = llvm.aarch64.neon.fminnmv t0
This change extends r247575.
llvm-svn: 249834
2015-10-09 14:11:25 +00:00
34b9bd0435
Improve ISel using across lane min/max reduction
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In vectorized integer min/max reduction code, the final "reduce" step
is sub-optimal. In AArch64, this change wll combine :
%svn0 = vector_shuffle %0, undef<2,3,u,u>
%smax0 = smax %0, svn0
%svn3 = vector_shuffle %smax0, undef<1,u,u,u>
%sc = setcc %smax0, %svn3, gt
%n0 = extract_vector_elt %sc, #0
%n1 = extract_vector_elt %smax0, #0
%n2 = extract_vector_elt $smax0, #1
%result = select %n0, %n1, n2
becomes :
%1 = smaxv %0
%result = extract_vector_elt %1, 0
This change extends r246790.
llvm-svn: 247575
2015-09-14 16:19:52 +00:00
Simon Pilgrim