aabe06d92a
Reorganization: Move the Spiller out of VirtRegMap.cpp into its own files. No (intended) functionality change.
...
llvm-svn: 66720
2009-03-11 22:31:21 +00:00
c544cb0eca
Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
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llvm-svn: 62600
2009-01-20 19:12:24 +00:00
8f79775a66
Make linear scan's trivial coalescer slightly more aggressive.
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llvm-svn: 62547
2009-01-20 00:16:18 +00:00
906152a20f
Tidy up #includes, deleting a bunch of unnecessary #includes.
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llvm-svn: 61715
2009-01-05 17:59:02 +00:00
ce3ccc1ea0
- More pre-split fixes: spill slot live interval computation bug; restore point bug.
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- If a def is spilt, remember its spill index to allow its reuse.
llvm-svn: 58375
2008-10-29 08:39:34 +00:00
938e201528
- Rewrite code that update register live interval that's split.
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- Create and update spill slot live intervals.
- Lots of bug fixes.
llvm-svn: 58367
2008-10-29 05:06:14 +00:00
d0d0317b9a
Committing a good chunk of the pre-register allocation live interval splitting pass. It's handling simple cases and appear to do good things. Next: avoid splitting an interval multiple times; renumber registers when possible; record stack slot live intervals for coloring; rematerialize defs when possible.
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llvm-svn: 58044
2008-10-23 20:43:13 +00:00
9c4b7d5c4f
Fix command-line option printing to print two spaces where needed,
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instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.
llvm-svn: 57521
2008-10-14 20:25:08 +00:00
1d338fc6a4
Add an option to enable StrongPHIElimination, for ease of testing.
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llvm-svn: 57259
2008-10-07 20:22:28 +00:00
9156bd2f48
Re-apply 56835 along with header file changes.
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llvm-svn: 56848
2008-09-30 15:44:16 +00:00
2b9adce1d0
Revert commit 56835 since it breaks the build.
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"If a re-materializable instruction has a register
operand, the spiller will change the register operand's
spill weight to HUGE_VAL to avoid it being spilled.
However, if the operand is already in the queue ready
to be spilled, avoid re-materializing it".
llvm-svn: 56837
2008-09-30 10:00:30 +00:00
9469049f7d
If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it.
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llvm-svn: 56835
2008-09-30 06:36:58 +00:00
c36660d756
Next round of earlyclobber handling. Approach the
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RA problem by expanding the live interval of an
earlyclobber def back one slot. Remove
overlap-earlyclobber throughout. Remove
earlyclobber bits and their handling from
live internals.
llvm-svn: 56539
2008-09-24 01:07:17 +00:00
9af7b3daec
Teach coalescer about earlyclobber bits.
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Check bits for preferred register.
llvm-svn: 56384
2008-09-20 02:03:04 +00:00
c042000649
Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on.
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llvm-svn: 56381
2008-09-20 01:28:05 +00:00
436aae627d
Make earlyclobber stuff work when virtual regs
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have previously been assigned conflicting physreg.
llvm-svn: 56364
2008-09-19 18:52:31 +00:00
e519bd4183
Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis
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and redo as linked list walk. Logic moved into RA.
Per review feedback.
llvm-svn: 56326
2008-09-19 01:02:35 +00:00
3d9416cf24
Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo.
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llvm-svn: 56314
2008-09-18 22:38:47 +00:00
f8610ebebc
Add a bit to mark operands of asm's that conflict
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with an earlyclobber operand elsewhere. Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way
that conflicts with an earlyclobber. See also comments.
llvm-svn: 56290
2008-09-17 21:13:11 +00:00
53b728c27c
Fix PR2757. Ignore liveinterval register allocation preference if the preference register is not in the right register class. This can happen due to sub-register coalescing.
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llvm-svn: 56006
2008-09-09 20:22:01 +00:00
a79db30d28
Tidy up several unbeseeming casts from pointer to intptr_t.
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llvm-svn: 55779
2008-09-04 17:05:41 +00:00
d669b9b671
Convert several std::vectors over to SmallVector, and use reserve() as appropriate for cases where std::vector is still used.
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llvm-svn: 54820
2008-08-15 18:49:41 +00:00
99e911fb16
Get rid of a use of std::map.
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llvm-svn: 54770
2008-08-13 23:36:23 +00:00
51f689a652
Make the allocation of LiveIntervals explicit, rather than holding them in the r2iMap_ by value. This will prevent references to them from being invalidated
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if the map is changed.
llvm-svn: 54763
2008-08-13 21:49:13 +00:00
7c800ad977
Fix a compile-time regression introduced by my heuristic-changing patch. I forgot
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to multiply the instruction count by a constant factor in a few places, which
caused the register allocator to require many more iterations.
llvm-svn: 53959
2008-07-23 19:47:27 +00:00
029182f3a3
Change the heuristics used in the coalescer, register allocator, and within
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live intervals itself to use an instruction count approximation that is
not affected by inserting empty indices.
llvm-svn: 53937
2008-07-22 22:46:49 +00:00
9cc3f68ab1
A brief survey of priority_queue usage in the tree turned this up
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as a questionable case, but the code isn't actually needed.
llvm-svn: 52657
2008-06-23 23:51:16 +00:00
efc67e78d7
Enhanced heuristic to determine the *best* register to spill. Instead of picking the register with the lowest spill weight. Consider (up to) 2 additional registers with spill weights that are close to the lowest spill weight. The one with fewest defs and uses that conflicts with the current interval (weighted by loop depth) is the spill candidate.
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This is not always a win, but there are much more wins than loses and wins tend to be more noticeable.
llvm-svn: 52554
2008-06-20 21:45:16 +00:00
6d7a144453
Refine stack slot interval weight computation.
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llvm-svn: 52040
2008-06-06 07:54:39 +00:00
12a0222a01
Add a stack slot coloring pass. Not yet enabled.
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llvm-svn: 51934
2008-06-04 09:18:41 +00:00
305d268ac3
Do not add empty live intervals to handled_. They should never be undone for backtracking.
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llvm-svn: 49544
2008-04-11 17:55:47 +00:00
6d07b625aa
Special handling of zero-sized live intervals.
...
llvm-svn: 49167
2008-04-03 16:40:27 +00:00
6e225173c5
Add an assertion to catch register of illegal class.
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llvm-svn: 48751
2008-03-24 23:28:21 +00:00
e21a68bca7
Undo tweak. It had no obvious benefit.
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llvm-svn: 48341
2008-03-13 17:42:48 +00:00
e88a625ecd
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
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llvm-svn: 48218
2008-03-11 07:19:34 +00:00
850e143cbf
Temporarily revert 48175.
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llvm-svn: 48204
2008-03-11 00:27:34 +00:00
7abdb438a1
If the register allocator ran out of registers, just abort for now.
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llvm-svn: 48175
2008-03-10 21:27:20 +00:00
d6bd311506
Use a smallvector for inactiveCounts and initialize it lazily
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instead of init'ing it maximally to zeros on entry. getFreePhysReg
is pretty hot and only a few elements are typically used. This speeds
up linscan by 5% on 176.gcc.
llvm-svn: 47631
2008-02-26 22:08:41 +00:00
d7a258d325
Rename PrintableName to Name.
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llvm-svn: 47629
2008-02-26 21:47:57 +00:00
c24ea4fb41
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
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would have been a Godsend here!
llvm-svn: 47625
2008-02-26 21:11:01 +00:00
18991d78fa
Fix newly-introduced 4.3 warnings
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llvm-svn: 47375
2008-02-20 12:07:57 +00:00
3a4be0fdef
Rename MRegisterInfo to TargetRegisterInfo.
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llvm-svn: 46930
2008-02-10 18:45:23 +00:00
0c209430b4
Don't recalculate the loop info and loop dominators analyses if they're
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preserved.
llvm-svn: 45596
2008-01-04 20:54:55 +00:00
a10fff51d9
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
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that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
llvm-svn: 45467
2007-12-31 04:13:23 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
303417d242
Switch over to MachineLoopInfo.
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llvm-svn: 44838
2007-12-11 02:09:15 +00:00
8e22379303
Live interval splitting:
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When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
llvm-svn: 44198
2007-11-17 00:40:40 +00:00
b3712f8146
Adding debug output during coalescing.
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llvm-svn: 44154
2007-11-15 02:06:30 +00:00
8269925b1e
Need to increment the iterator.
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llvm-svn: 44153
2007-11-15 00:40:48 +00:00
be51f28e2b
Refactor some code.
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llvm-svn: 44010
2007-11-12 06:35:08 +00:00
5c1b044899
If an interval is being undone clear its preference as well since the source interval may have been undone as well.
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llvm-svn: 43670
2007-11-04 08:32:21 +00:00
66298e226f
There are times when the coalescer would not coalesce away a copy but the copy
...
can be eliminated by the allocator is the destination and source targets the
same register. The most common case is when the source and destination registers
are in different class. For example, on x86 mov32to32_ targets GR32_ which
contains a subset of the registers in GR32.
The allocator can do 2 things:
1. Set the preferred allocation for the destination of a copy to that of its source.
2. After allocation is done, change the allocation of a copy destination (if
legal) so the copy can be eliminated.
This eliminates 443 extra moves from 403.gcc.
llvm-svn: 43662
2007-11-03 07:20:12 +00:00
0dde6e5761
Apply Chris' suggestions.
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llvm-svn: 43069
2007-10-17 06:53:44 +00:00
a6fd8bc97e
Clean up code that calculate MBB live-in's.
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llvm-svn: 43061
2007-10-17 02:12:22 +00:00
8f644cef0f
Some clean up.
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llvm-svn: 43043
2007-10-16 21:09:14 +00:00
89d5916921
Some clean up.
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llvm-svn: 42898
2007-10-12 08:45:27 +00:00
65d2a697dc
Pluggable coalescers inplementation.
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llvm-svn: 41743
2007-09-06 16:18:45 +00:00
33820da1da
Re-implement trivial rematerialization. This allows def MIs whose live intervals that are coalesced to be rematerialized.
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llvm-svn: 41060
2007-08-13 23:45:17 +00:00
02f6e9b621
Factor live variable analysis so it does not do register coalescing
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simultaneously. Move that pass to SimpleRegisterCoalescing.
This makes it easier to implement alternative register allocation and
coalescing strategies while maintaining reuse of the existing live
interval analysis.
llvm-svn: 37520
2007-06-08 17:18:56 +00:00
31fd60ba0c
Change names from RA to something unique to get rid of naming conflicts with
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certain linkers...
llvm-svn: 36944
2007-05-08 19:02:46 +00:00
8c78a0bff0
Drop 'const'
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llvm-svn: 36662
2007-05-03 01:11:54 +00:00
e95c6ad802
Use 'static const char' instead of 'static const int'.
...
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
llvm-svn: 36652
2007-05-02 21:39:20 +00:00
09f162ca6a
Do not use typeinfo to identify pass in pass manager.
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llvm-svn: 36632
2007-05-01 21:15:47 +00:00
0ba174534c
Match MachineFunction::UsedPhysRegs changes.
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llvm-svn: 36452
2007-04-25 22:13:27 +00:00
11dc5abde1
Clean up.
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llvm-svn: 36431
2007-04-25 07:18:20 +00:00
b881bdabd9
Copy coalescing change to prevent a physical register from being pin to a
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long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
first (if available) to create identify moves that can be eliminated.
llvm-svn: 36218
2007-04-17 20:32:26 +00:00
0e3278e505
First cut trivial re-materialization support.
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llvm-svn: 35208
2007-03-20 08:13:50 +00:00
220a7af107
Only add liveinterval to livein set if it isn't assigned a stack slot.
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llvm-svn: 34593
2007-02-25 09:39:02 +00:00
f7ed82da10
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
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llvm-svn: 34428
2007-02-19 21:49:54 +00:00
da81bf4d3e
For PR1207:
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Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
llvm-svn: 34399
2007-02-19 03:20:00 +00:00
a3d3599210
Do not add livein's to entry MBB twice.
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llvm-svn: 34382
2007-02-17 11:11:27 +00:00
7238410766
Add live-ins to every BB.
...
llvm-svn: 34342
2007-02-16 09:05:02 +00:00
aee775a6b7
Eliminate static ctors from Statistics
...
llvm-svn: 32698
2006-12-19 22:41:21 +00:00
700b873130
Detemplatize the Statistic class. The only type it is instantiated with
...
is 'unsigned'.
llvm-svn: 32279
2006-12-06 17:46:33 +00:00
979804d800
eliminate fp statistic
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llvm-svn: 32251
2006-12-06 01:48:55 +00:00
cc08c83186
Unbreak VC++ build.
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llvm-svn: 32113
2006-12-02 02:22:01 +00:00
d108b9a60d
Replace std::cerr uses of the "DEBUG" macro with "DOUT" instead. Removes
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a #include of iostream.
llvm-svn: 31800
2006-11-17 00:50:36 +00:00
61feeb90f9
Remove redundant <cmath>.
...
llvm-svn: 31561
2006-11-08 19:16:44 +00:00
6a9342166b
Use correct value for float HUGH_VAL.
...
llvm-svn: 31500
2006-11-07 12:25:45 +00:00
a916192267
LinearScanner hotspot.
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llvm-svn: 31153
2006-10-24 14:35:25 +00:00
3d27be1333
s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|
...
llvm-svn: 29911
2006-08-27 12:54:02 +00:00
29e635d3c9
Final polish on machine pass registries.
...
llvm-svn: 29471
2006-08-02 12:30:23 +00:00
95eda5b1f3
Introducing plugable register allocators and instruction schedulers.
...
llvm-svn: 29434
2006-08-01 14:21:23 +00:00
c496b418b5
Reduce number of exported symbols
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llvm-svn: 29220
2006-07-20 17:28:38 +00:00
e097e6f7c7
Shave another 27K off libllvmgcc.dylib with visibility hidden
...
llvm-svn: 28973
2006-06-28 22:17:39 +00:00
a726fc6dbf
If the register allocator cannot find a register to spill, try the aliases. If
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that still fails (because all the register spill weights are inf), just grab
one.
llvm-svn: 28262
2006-05-12 19:07:46 +00:00
db6aa4896b
Backing out previous check-in.
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llvm-svn: 28219
2006-05-11 07:28:16 +00:00
6ad040a6bc
If the live interval legnth is essentially zero, i.e. in every live range
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the use follows def immediately, it doesn't make sense to spill it and
hope it will be easier to allocate for this LI.
llvm-svn: 28217
2006-05-10 22:30:41 +00:00
b6e2d0027a
Add some comments.
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llvm-svn: 27133
2006-03-25 23:00:56 +00:00
2988921dc4
Code cleanups, no functionality change
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llvm-svn: 26328
2006-02-23 06:44:17 +00:00
de02d7727f
Add explicit #includes of <iostream>
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llvm-svn: 25515
2006-01-22 23:41:00 +00:00
e47d9d0e92
HB is *the* code janitor.
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llvm-svn: 25031
2005-12-28 04:55:42 +00:00
f28b3bd8b4
I think I know what you meant here, but just to be safe I'll let you
...
do it. :)
<_sabre_> excuses excuses
llvm-svn: 24471
2005-11-21 14:09:40 +00:00
2ea5c99eca
Add section switching to common code generator code. Add a couple of
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asserts.
llvm-svn: 24445
2005-11-21 07:06:27 +00:00
b1f8982ff0
Expose the LiveInterval interfaces as public headers.
...
llvm-svn: 23400
2005-09-21 04:19:09 +00:00
4d602bed10
When checking the fixed intervals, don't forget to check for register aliases.
...
This fixes PR621 and Regression/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll
llvm-svn: 23158
2005-08-30 21:03:36 +00:00
22e91cc3b5
Keep track of which registers are related to which other registers.
...
Use this information to avoid doing expensive interval intersections for
registers that could not possible be interesting. This speeds up linscan
on ia64 compiling kc++ in release mode from taking 7.82s to 4.8s(!), total
itanium llc time on this program is 27.3s now. This marginally speeds up
PPC and X86, but they appear to be limited by other parts of linscan, not
this code.
On this program, on itanium, live intervals now takes 41% of llc time.
llvm-svn: 22986
2005-08-23 22:27:31 +00:00
834a2316a3
Try to avoid scanning the fixed list. On architectures with a non-stupid
...
number of regs (e.g. most riscs), many functions won't need to use callee
clobbered registers. Do a speculative check to see if we can get a free
register without processing the fixed list (which has all of these). This
saves a lot of time on machines with lots of callee clobbered regs (e.g.
ppc and itanium, also x86).
This reduces ppc llc compile time from 184s -> 172s on kc++. This is probably
worth FAR FAR more on itanium though.
llvm-svn: 22972
2005-08-22 20:59:30 +00:00
95a157ae1a
Move some code in the register assignment case that only needs to happen if
...
we spill out of the fast path. The scan of active_ and the calls to
updateSpillWeights don't need to happen unless a spill occurs. This reduces
debug llc time of kc++ with ppc from 187.3s to 183.2s.
llvm-svn: 22971
2005-08-22 20:20:42 +00:00
83b821b584
Speed up this loop a bit, based on some observations that Nate made, and
...
add some comments. This loop really needs to be reevaluated!
llvm-svn: 22966
2005-08-22 16:55:22 +00:00
Owen Anderson