llvm-project

Commit Graph

Author	SHA1	Message	Date
Tim Northover	f02287db27	ARM: permit bare dmb/dsb/isb aliases on Cortex-M0 Cortex-M0 supports these 32-bit instructions despite being Thumb1 only (mostly). We knew about that but not that the aliases without the default "sy" operand were also permitted. llvm-svn: 194094	2013-11-05 21:36:02 +00:00
Tim Northover	f86d1f0b77	ARM: allow cortex-m0 to use hint instructions The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 llvm-svn: 192097	2013-10-07 11:10:47 +00:00

Author

SHA1

Message

Date

Tim Northover

f02287db27

ARM: permit bare dmb/dsb/isb aliases on Cortex-M0

Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.

llvm-svn: 194094

2013-11-05 21:36:02 +00:00

Tim Northover

f86d1f0b77

ARM: allow cortex-m0 to use hint instructions

The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have
been ported across to the v6M architecture. Fortunately, v6M seems to sit
nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it
fairly easily.

rdar://problem/15144406

llvm-svn: 192097

2013-10-07 11:10:47 +00:00

2 Commits