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21 Commits

Author SHA1 Message Date
Jim Grosbach 6068d0014a ARM assembly two-operand forms for VRSHL. 
rdar://11252521

llvm-svn: 154840
 2012-04-16 18:03:16 +00:00
Jim Grosbach 9bfe7054af Tidy up. Test formatting. 
llvm-svn: 154839
 2012-04-16 18:03:14 +00:00
Jim Grosbach 15c6884a4b ARM assembly aliases for two-operand V[R]SHR instructions. 
rdar://11189467

llvm-svn: 154087
 2012-04-05 07:23:53 +00:00
Jim Grosbach 3cfef8d467 NEON Two-operand assembly aliases for VSRA. 
llvm-svn: 148821
 2012-01-24 17:55:36 +00:00
Jim Grosbach 7ae12cc546 NEON Two-operand assembly aliases for VSLI. 
llvm-svn: 148819
 2012-01-24 17:49:15 +00:00
Jim Grosbach 7b6f0f67aa NEON Two-operand assembly aliases for VSRI. 
llvm-svn: 148818
 2012-01-24 17:46:58 +00:00
Jim Grosbach 1395b67e3b Tidy up. 
llvm-svn: 148817
 2012-01-24 17:46:54 +00:00
Jim Grosbach ba7d6ed05d ARM VSHR implied destination operand form aliases. 
llvm-svn: 146192
 2011-12-08 22:06:06 +00:00
Jim Grosbach 3a97d946d2 Tidy up a bit. 
llvm-svn: 146190
 2011-12-08 22:04:40 +00:00
Jim Grosbach 00326406d4 ARM NEON two-operand aliases for VSHL(immediate). 
llvm-svn: 146125
 2011-12-08 01:30:04 +00:00
Jim Grosbach f10a635eb4 ARM NEON two-operand aliases for VSHL(register). 
llvm-svn: 146123
 2011-12-08 01:12:35 +00:00
Bill Wendling 5e57137e87 * Correct encoding for VSRI. 
* Add tests for VSRI and VSLI.

llvm-svn: 127297
 2011-03-09 00:33:17 +00:00
Bill Wendling a7f303de71 Correct the encoding for VRSRA and VSRA instructions. 
llvm-svn: 127294
 2011-03-09 00:00:35 +00:00
Bill Wendling e313f16ad9 * Fix VRSHR and VSHR to have the correct encoding for the immediate. 
* Update the NEON shift instruction test to expect what 'as' produces.

llvm-svn: 127293
 2011-03-08 23:48:09 +00:00
Bill Wendling a259686db1 A few more tests for instruction encodings. 
llvm-svn: 127209
 2011-03-08 02:51:48 +00:00
Bill Wendling 77ad1dc56d Rename the narrow shift right immediate operands to "shr_imm*" operands. Also 
expand the testing of the narrowing shift right instructions.

No functionality change.

llvm-svn: 127193
 2011-03-07 23:38:41 +00:00
Bill Wendling 3b1459b810 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

llvm-svn: 126723
 2011-03-01 01:00:59 +00:00
Bob Wilson c3ff538dcf Fix misspelled target triples in MC/ARM test commands. 
llvm-svn: 121901
 2010-12-15 22:14:01 +00:00
Owen Anderson cd9da22f68 Use ARM-style comment syntax. 
llvm-svn: 117941
 2010-11-01 18:33:37 +00:00
Jim Grosbach 0190a649e8 Mark ARM subtarget features that are available for the assembler. 
llvm-svn: 117929
 2010-11-01 16:59:54 +00:00
Owen Anderson fccb9d032f Convert this test to .s form. 
llvm-svn: 117900
 2010-11-01 05:23:58 +00:00