Commit Graph

143113 Commits

Author SHA1 Message Date
Daniel Sanders 21ac840fca [aarch64][globalisel] Move getValueMapping/getCopyMapping to AArch64GenRegisterBankInfo. NFC.
Summary:
We did lose a little specificity in the assertion messages for the
PartialMappingIdx enumerators in this change but this was necessary to
avoid unnecessary use of 'public:' and we haven't lost anything that
can't be discovered easily in lldb. Once this is tablegen-erated we could
also safely remove the assertions.

Depends on D27976

Reviewers: t.p.northover, ab, rovka, qcolombet

Subscribers: aditya_nandakumar, aemerson, rengolin, vkalintiris, dberris, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D27978

llvm-svn: 291900
2017-01-13 11:50:34 +00:00
Daniel Sanders f81cf47e65 [aarch64][globalisel] Refactor getRegBankBaseIdxOffset() to remove the power-of-2 assumption. NFC
Summary:
We don't exploit it yet though

Depends on D27976

Reviewers: t.p.northover, ab, rovka, qcolombet

Subscribers: aditya_nandakumar, aemerson, rengolin, vkalintiris, dberris, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D27977

llvm-svn: 291899
2017-01-13 11:23:37 +00:00
Sam Parker 770ceb69ba [ARM] Enable objdump to construct triple for ARM
Now that The ARMAttributeParser has been moved into the library,
it has been modified so that it can parse the attributes without
printing them and stores them in a map. ELFObjectFile now queries
the attributes to fill out the architecture details of a provided
triple for 'arm' and 'thumb' targets. llvm-objdump uses this new
functionality.

Differential Revision: https://reviews.llvm.org/D28281

llvm-svn: 291898
2017-01-13 11:04:21 +00:00
Daniel Sanders 438a1ecc2c [aarch64][globalisel] Move data into <Target>GenRegisterBankInfo. NFC.
Summary: Depends on D27809

Reviewers: t.p.northover, rovka, qcolombet, ab

Subscribers: aditya_nandakumar, aemerson, rengolin, vkalintiris, dberris, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D27976

llvm-svn: 291897
2017-01-13 10:53:57 +00:00
Sam Parker 34315eec58 [ARM] Moved ARMAttributeParser to Support
Moved ARMAttributeParser out of llvm-readobj and into the support
library.

Differential Revision: https://reviews.llvm.org/D28227

llvm-svn: 291896
2017-01-13 10:50:01 +00:00
Diana Picus a2c59149e1 [ARM] CodeGen: Replace AddDefaultT1CC and AddNoT1CC. NFC
For AddDefaultT1CC, we add a new helper t1CondCodeOp, which creates the
appropriate register operand. For AddNoT1CC, we use the existing condCodeOp
helper - we only had two uses of AddNoT1CC, so at this point it's probably not
worth having yet another helper just for them.

Differential Revision: https://reviews.llvm.org/D28603

llvm-svn: 291894
2017-01-13 10:37:37 +00:00
Diana Picus 8a73f5562f [ARM] CodeGen: Remove AddDefaultCC. NFC.
Replace all uses of AddDefaultCC with add(condCodeOp()).
The transformation has been done automatically with a custom tool based on Clang
AST Matchers + RefactoringTool.

Differential Revision: https://reviews.llvm.org/D28557

llvm-svn: 291893
2017-01-13 10:18:01 +00:00
Diana Picus 116bbab4e4 [CodeGen] Rename MachineInstrBuilder::addOperand. NFC
Rename from addOperand to just add, to match the other method that has been
added to MachineInstrBuilder for adding more than just 1 operand.

See https://reviews.llvm.org/D28057 for the whole discussion.

Differential Revision: https://reviews.llvm.org/D28556

llvm-svn: 291891
2017-01-13 09:58:52 +00:00
Diana Picus 4f8c3e1882 [ARM] CodeGen: Remove AddDefaultPred. NFC.
Replace all uses of AddDefaultPred with MachineInstrBuilder::add(predOps()).
This makes the code building MachineInstrs more readable, because it allows us
to write code like:

MIB.addSomeOperand(blah)
   .add(predOps())
   .addAnotherOperand(blahblah)

instead of

AddDefaultPred(MIB.addSomeOperand(blah))
    .addAnotherOperand(blahblah)

This commit also adds the predOps helper in the ARM backend, as well as the add
method taking a variable number of operands to the MachineInstrBuilder.

The transformation has been done mostly automatically with a custom tool based
on Clang AST Matchers + RefactoringTool.

Differential Revision: https://reviews.llvm.org/D28555

llvm-svn: 291890
2017-01-13 09:37:56 +00:00
Michael Zuckerman 558a4d8419 [X86][AVX512] Adding missing shuffle lowering to blend mask instructions
Some shuffles can be lowered to blend mask instruction (VPBLENDMB/VPBLENDMW/VPBLENDMD/VPBLENDMQ) .
In this patch, I added new pattern match for this case.

Reviewers:
1. craig.topper
2. guyblank
3. RKSimon
4. igorb     

Differential Revision: https://reviews.llvm.org/D28483

llvm-svn: 291888
2017-01-13 09:06:00 +00:00
Tobias Grosser 190d4e5fa2 RegionPass: Set isExecuted flag correctly
This was forgotten in r291882. Without this fix, the Polly build bots are
broken.

llvm-svn: 291887
2017-01-13 09:00:17 +00:00
NAKAMURA Takumi fd3e6d857e DWARFDie.h: Move a class declaration out of the method description since r291861. [-Wdocumentation]
llvm-svn: 291886
2017-01-13 08:20:18 +00:00
Craig Topper 1ec84c2a18 [AVX-512] Remove unmasked BLENDM instructions from the wrong load folding table. The unmasked versions read memory from operand 2, but were in the operand 3 table.
These aren't the most interesting set of blendm instructions as the unmasked version isn't useful. We were also missing the B and W forms. I'll add the masked versions of all sizes in a future patch.

llvm-svn: 291885
2017-01-13 07:28:56 +00:00
Craig Topper 46b6ecf41e [X86] Move some entries in the load folding tables to move appropriate grouping. NFC
llvm-svn: 291884
2017-01-13 07:28:53 +00:00
Craig Topper eec4890346 [IR] Don't call assertModuleIsMaterialized in release builds
Summary:
To fix a release vs debug build linking error, r259695 made the body of assertModuleIsMaterialized empty if Value.cpp gets compiled in a release build. This way any code compiled as a debug build can still link against a release version of the function.

This patch takes this a step farther and removes all calls to it from Value.h in any code that includes it in a relase build.

This shrinks the opt binary on my macbook build by 17240 bytes.

Reviewers: rafael

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D28191

llvm-svn: 291883
2017-01-13 06:26:18 +00:00
Serge Pavlov d409411ef1 Track validity of pass results
Running tests with expensive checks enabled exhibits some problems with
verification of pass results.

First, the pass verification may require results of analysis that are not
available. For instance, verification of loop info requires results of dominator
tree analysis. A pass may be marked as conserving loop info but does not need to
be dependent on DominatorTreePass. When a pass manager tries to verify that loop
info is valid, it needs dominator tree, but corresponding analysis may be
already destroyed as no user of it remained.

Another case is a pass that is skipped. For instance, entities with linkage
available_externally do not need code generation and such passes are skipped for
them. In this case result verification must also be skipped.

To solve these problems this change introduces a special flag to the Pass
structure to mark passes that have valid results. If this flag is reset,
verifications dependent on the pass result are skipped.

Differential Revision: https://reviews.llvm.org/D27190

llvm-svn: 291882
2017-01-13 06:09:54 +00:00
Easwaran Raman b035f914e4 ProfileSummaryInfo improvements.
* Add is{Hot|Cold}CallSite methods
* Fix a bug in isHotBB where it was looking for MD_prof on a return instruction
* Use MD_prof data only if sample profiling was used to collect profiles.
* Add an unit test to ProfileSummaryInfo

Differential Revision: https://reviews.llvm.org/D28584

llvm-svn: 291878
2017-01-13 01:34:00 +00:00
NAKAMURA Takumi db08e83280 Revert r291503, "Lift the 10-type limit for AlignedCharArrayUnion", and followings.
r291503, "Lift the 10-type limit for AlignedCharArrayUnion"
  r291514, "Fix MSVC build of AlignedCharArrayUnion"
  r291515, "Revert the attempt to optimize the constexpr functions. MSVC does not handle this yet"
  r291519, "Try once again to fix the MSVC build of AlignedCharArrayUnion"

They has been failing on i686-linux.

llvm-svn: 291875
2017-01-13 01:13:10 +00:00
Eugene Zelenko 8187c192c6 [PowerPC] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 291872
2017-01-13 00:58:58 +00:00
Greg Clayton 7150343fbc Fix buildbots.
llvm-svn: 291864
2017-01-13 00:23:59 +00:00
NAKAMURA Takumi c433de7c8b xray-account: Avoid std::errc::bad_message to appease mingw.
llvm-svn: 291863
2017-01-13 00:17:15 +00:00
Adam Nemet 6117caab58 Move test of lazy BFI with ORE to a generic directory
llvm-svn: 291862
2017-01-13 00:16:23 +00:00
Greg Clayton 0e62ee7d60 Add the ability to iterate across all attributes in a DIE.
Differential Revision: https://reviews.llvm.org/D28386

llvm-svn: 291861
2017-01-13 00:13:42 +00:00
Evgeniy Stepanov f01c70fec0 [asan] Don't overalign global metadata.
Other than on COFF with incremental linking, global metadata should
not need any extra alignment.

Differential Revision: https://reviews.llvm.org/D28628

llvm-svn: 291859
2017-01-12 23:26:20 +00:00
Evgeniy Stepanov 5d31d08a21 [asan] Refactor instrumentation of globals.
llvm-svn: 291858
2017-01-12 23:03:03 +00:00
Zachary Turner 44a643c60c [llvm-pdbdump] Add a compact dump mode.
Differential Revision: https://reviews.llvm.org/D28545

llvm-svn: 291849
2017-01-12 22:28:15 +00:00
Teresa Johnson 83aaf358fd [ThinLTO] Import static functions from the same module as caller
Summary:
We can sometimes end up with multiple copies of a local function that
have the same GUID in the index. This happens when there are local
functions with the same name that are in different source files with the
same name (but in different directories), and they were compiled in
their own directory so had the same path at compile time.

In this case make sure we import the copy in the caller's module. While
it isn't a correctness problem (the renamed reference which is based on the
module IR hash will be unique since the module must have had an
externally visible function that was imported), importing the wrong copy
will result in lost performance opportunity since it won't be referenced
and inlined.

Reviewers: mehdi_amini

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D28440

llvm-svn: 291841
2017-01-12 22:04:45 +00:00
Hans Wennborg 669f0d7582 Clear the release notes for 5.0.0
llvm-svn: 291836
2017-01-12 21:50:22 +00:00
Chris Bieneman 07088c1060 [ObjectYAML] Pull yaml2dwarf out of yaml2obj for reuse
This patch pulls the yaml2dwarf code out of yaml2obj into a new set of DWARF emitter functions in the DWARFYAML namespace. This will enable the YAML->DWARF code to be used inside DWARF tests by populating the DWARFYAML structs and calling the Emitter functions.

llvm-svn: 291828
2017-01-12 21:35:21 +00:00
Hans Wennborg 6d9e2c4a9c Bump trunk version to 5.0.0svn
llvm-svn: 291815
2017-01-12 21:22:36 +00:00
Robert Lougher b0124c1eb8 [DebugInfo] Remove redundant check in SimplifyCFG; NFC.
llvm-svn: 291813
2017-01-12 21:11:09 +00:00
Robert Lougher 426851e608 [DebugInfo] Handle same locations in DILocation::getMergedLocation
Revision 289661 introduced the function DILocation::getMergedLocation for
merging of debug locations. At the time is was simply a stub which always
returned no location. This patch modifies getMergedLocation to handle the
case where the two locations are the same or can't be discriminated.

Differential Revision: https://reviews.llvm.org/D28521

llvm-svn: 291809
2017-01-12 20:34:35 +00:00
Eli Friedman b5c3a0d1c3 [SCEV] Simplify SolveLinEquationWithOverflow a bit.
Cleanup in preparation for generalizing it.

llvm-svn: 291808
2017-01-12 20:21:00 +00:00
Nikolai Bozhenov f02ac0eeb2 [X86] Replace AND+IMM64 with SRL/SHL
Emit SHRQ/SHLQ instead of ANDQ with a 64 bit constant mask if the result
is unused and the mask has only higher/lower bits set. For example, with
this patch LLVM emits

  shrq $41, %rdi
  je

instead of

  movabsq $0xFFFFFE0000000000, %rcx
  testq   %rcx, %rdi
  je

This reduces number of instructions, code size and register pressure.
The transformation is applied only for cases where the mask cannot be
encoded as an immediate value within TESTQ instruction.

Differential Revision: https://reviews.llvm.org/D28198

llvm-svn: 291806
2017-01-12 19:54:27 +00:00
Nikolai Bozhenov 3db8bcdbba [X86] Modify BypassSlowDivision tests to match their new names (NFC)
- bypass-slow-division-32.ll:
  tests verifying correctness of divl-to-divb bypassing

- bypass-slow-division-64.ll:
  tests verifying correctness of divq-to-divl bypassing

- bypass-slow-division-tune.ll:
  tests verifying that bypassing is enabled only when appropriate

Differential Revision: https://reviews.llvm.org/D28551

llvm-svn: 291804
2017-01-12 19:48:01 +00:00
Marcello Maggioni a5f1ff1afa [llvm-config] Fix obviously wrong code in parsing DyLib components.
The code parsing the string was using the offset returned from
StringRef::find() wrong, assuming it was relative to the staring
offset that is passed to the function, but the returned offset
is always relative to the beginning of the line.

This causes odd behaviour while parsing the component string.
Spotted thanks to the newly added test:

tools/llvm-config/booleans.test

llvm-svn: 291803
2017-01-12 19:47:38 +00:00
Nikolai Bozhenov 6684aeb137 [X86] Rename tests for bypassing slow division (NFC)
For tests on bypassing slow division there's no need to be
Atom-specific. The patch renames all tests on division bypassing
and makes their names more consistent:

  atom-bypass-slow-division.ll -> bypass-slow-division-32.ll
  (tests verifying correctness of divl-to-divb bypassing)

  atom-bypass-slow-division-64.ll -> bypass-slow-division-64.ll
  (tests verifying correctness of divq-to-divl bypassing)

  slow-div.ll -> bypass-slow-division-tune.ll
  (tests verifying that bypassing is enabled only when appropriate)

Differential Revision: https://reviews.llvm.org/D28197

llvm-svn: 291802
2017-01-12 19:41:27 +00:00
Nikolai Bozhenov 6bdf92cec7 [X86] Tune bypassing of slow division for Intel CPUs
64-bit integer division in Intel CPUs is extremely slow, much slower
than 32-bit division. On the other hand, 8-bit and 16-bit divisions
aren't any faster. The only important exception is Atom where DIV8
is fastest. Because of that, the patch
1) Enables bypassing of 64-bit division for Atom, Silvermont and
   all big cores.
2) Modifies 64-bit bypassing to use 32-bit division instead of
   16-bit one. This doesn't make the shorter division slower but
   increases chances of taking it. Moreover, it's much more likely
   to prove at compile-time that a value fits 32 bits and doesn't
   require a run-time check (e.g. zext i32 to i64).

Differential Revision: https://reviews.llvm.org/D28196

llvm-svn: 291800
2017-01-12 19:34:15 +00:00
Nikolai Bozhenov 05b4095990 [X86] Update LLC tests for slow division bypassing (NFC)
Run update_llc_test_checks.py on

    CodeGen/X86/atom-bypass-slow-division.ll
    CodeGen/X86/atom-bypass-slow-division-64.ll
    CodeGen/X86/slow-div.ll

Differential Revision: https://reviews.llvm.org/D28469

llvm-svn: 291799
2017-01-12 19:29:18 +00:00
Matt Arsenault 45337df08f AMDGPU: Skip fneg/select combine if it can fold into other
llvm-svn: 291792
2017-01-12 18:58:15 +00:00
Matt Arsenault 31c039ef2e AMDGPU: Fold free fneg into sin
llvm-svn: 291790
2017-01-12 18:48:09 +00:00
Saleem Abdulrasool 555e5980a5 ARM: slightly more table driven libcall setup
Switch some additional library call setup to be table driven.  This
makes it more immediately obvious what the library call looks like.
This is important for ARM since the calling conventions for the builtins
change based on the target/libcall name.  NFC

llvm-svn: 291789
2017-01-12 18:46:11 +00:00
Robert Lougher 6717a6fe54 [DebugInfo] DILocation variable declaration should be const; NFC.
llvm-svn: 291787
2017-01-12 18:33:49 +00:00
Hans Wennborg 84da661509 Avoid std::errc::protocol_* to appease mingw
Like r291636 and r285261.

llvm-svn: 291786
2017-01-12 18:33:14 +00:00
Robert Lougher f5df7a18dd [DebugInfo] Add const to DILocation variable declaration; NFC.
llvm-svn: 291785
2017-01-12 18:29:28 +00:00
Matt Arsenault a8c325e2f5 AMDGPU: Fold fneg into fmul_legacy
llvm-svn: 291784
2017-01-12 18:26:30 +00:00
Hans Wennborg 1bcabc4918 Bump year to 2017 in LICENSE.txt
llvm-svn: 291782
2017-01-12 18:02:42 +00:00
Matt Arsenault ff7e5aadf5 AMDGPU: Fold fneg into rcp
llvm-svn: 291779
2017-01-12 17:46:35 +00:00
Matt Arsenault 4242d48c36 AMDGPU: Fold fneg into fp_round
llvm-svn: 291778
2017-01-12 17:46:33 +00:00
Matt Arsenault 98d2bf1024 AMDGPU: Fold fneg into fp_extend
llvm-svn: 291777
2017-01-12 17:46:28 +00:00