4dd515c04f
Dump with dbgs() instead of printf.
...
llvm-svn: 138749
2011-08-29 18:14:17 +00:00
6bb5b3cfcd
Make GCC happy by adding parens.
...
llvm-svn: 138748
2011-08-29 18:14:15 +00:00
6314343333
Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653.
...
llvm-svn: 138746
2011-08-29 17:59:41 +00:00
50e0170fa5
Move non-intruction patterns to a more appropriate place!
...
llvm-svn: 138744
2011-08-29 17:51:24 +00:00
f02d98d7c0
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
...
llvm-svn: 138739
2011-08-29 17:17:09 +00:00
0896621a50
Reapply r138695. Fix PassManager stack depths.
...
Patch by Xiaoyi Guo!
llvm-svn: 138737
2011-08-29 17:07:00 +00:00
516dbb24b5
Add AMDIL as valid target triple to LLVM.
...
Submitted by: Villmow, Micah <Micah.Villmow@amd.com>
llvm-svn: 138734
2011-08-29 15:44:55 +00:00
7ea09c9462
Remove premature previous commit.
...
llvm-svn: 138725
2011-08-28 14:52:51 +00:00
4d63542b82
Fix PR5329: pay attention to constructor/destructor priority
...
when outputting them. With this, the entire LLVM testsuite
passes when built with dragonegg.
llvm-svn: 138724
2011-08-28 13:17:22 +00:00
f786bae6ac
Encoding of instructions referencing segments has changed. Do what X86MCCodeEmitter does.
...
llvm-svn: 138723
2011-08-28 13:07:57 +00:00
52600ee8c3
Bitcasts are transitive. Bitcast-Bitcast-X becomes Bitcast-X.
...
llvm-svn: 138722
2011-08-28 11:51:08 +00:00
7bfd86d046
Fix integer overflow bug in raw_ostream::write. This showed up as a
...
non-deterministic crash in the test suite. Fixes PR10055!
llvm-svn: 138717
2011-08-28 03:30:02 +00:00
61a1ff543c
Silence GCC warnings and make an array const.
...
llvm-svn: 138706
2011-08-27 17:36:14 +00:00
5ff961c376
Report failure if there are less bytes than requested in a MemoryObject.
...
Before we just left the remaining bytes uninitialized. This is another step in making llvm valgrind-clean again.
llvm-svn: 138705
2011-08-27 07:45:46 +00:00
ba198e661e
Auto upgrade the old EH scheme to use the new one. This is on a trial basis. If
...
things to disasterously over night, this can be reverted.
llvm-svn: 138702
2011-08-27 06:11:03 +00:00
5c29ebae8e
Reverting r138695 to see if it fixes clang self host.
...
llvm-svn: 138701
2011-08-27 06:10:16 +00:00
032c60c1a0
Only delete instructions once.
...
llvm-svn: 138700
2011-08-27 06:10:02 +00:00
4707d37ac9
These splits should be done whether they are critical edges or not.
...
llvm-svn: 138697
2011-08-27 04:40:37 +00:00
b0cd1e65de
Fix PassManager stack depths.
...
Patch by Xiaoyi Guo!
llvm-svn: 138695
2011-08-27 02:11:03 +00:00
b205c029a4
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
...
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
6c70e58041
Correct encoding of BL with immediate offset.
...
llvm-svn: 138673
2011-08-26 22:54:51 +00:00
b9d4e37776
ARM assembly parsing tweak for pldw.
...
llvm-svn: 138669
2011-08-26 22:21:51 +00:00
240d20af79
Spelling fail.
...
llvm-svn: 138667
2011-08-26 21:47:57 +00:00
3d1eac85c3
Thumb2 assembler parsing and encoding of IT instruction.
...
This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.
llvm-svn: 138665
2011-08-26 21:43:41 +00:00
71fce2c84d
Update the dominator tree with the correct dominator for the new 'unwind' block.
...
llvm-svn: 138664
2011-08-26 21:36:12 +00:00
5e5704277f
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
...
llvm-svn: 138660
2011-08-26 21:21:21 +00:00
fee8eda35b
Split the landing pad block only if it's a critical edge. Also intelligently
...
split it in the other place where we're splitting critical edges.
llvm-svn: 138658
2011-08-26 21:18:55 +00:00
fd60f60ed1
Fix ARM codegen breakage caused by r138653.
...
llvm-svn: 138657
2011-08-26 21:12:37 +00:00
3cc90fe5a5
Whitespace and 80-col.
...
llvm-svn: 138654
2011-08-26 21:02:40 +00:00
16d33f36d5
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
...
llvm-svn: 138653
2011-08-26 20:43:14 +00:00
eed1e8905a
Don't sink landingpad instructions during ind-var simplification.
...
llvm-svn: 138651
2011-08-26 20:40:15 +00:00
5658b49f64
Update for feedback from Jim.
...
llvm-svn: 138642
2011-08-26 19:39:26 +00:00
aa38dbadca
ARMDisassembler: Always return a size, even when disassembling fails.
...
This should fix PR10772.
llvm-svn: 138636
2011-08-26 18:21:36 +00:00
a01bcbfc80
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
...
llvm-svn: 138635
2011-08-26 18:09:22 +00:00
db6f646ec3
Don't insert branch hint lables that are never used.
...
llvm-svn: 138630
2011-08-26 10:14:56 +00:00
149695627a
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
...
This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
llvm-svn: 138625
2011-08-26 06:19:51 +00:00
c66d50d1a2
Fix disassembling of VCVTSD2SI
...
llvm-svn: 138623
2011-08-26 04:49:29 +00:00
147d9cde78
LoopInfo::updateUnloop fix, and verify Block->Loop maps.
...
Fixes an oversight, and adds verification to catch it in the unloop.ll tests.
llvm-svn: 138622
2011-08-26 03:06:34 +00:00
452aae6202
Atomic load/store on ARM/Thumb.
...
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.
I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.
llvm-svn: 138621
2011-08-26 02:59:24 +00:00
0655b78ccc
Address review comments.
...
- Reword comments.
- Allow undefined behavior interfering with undefined behavior.
- Add address space checks.
llvm-svn: 138619
2011-08-26 02:25:55 +00:00
fb212a6309
SimplifyCFG: If we have a PHI node that can evaluate to NULL and do a load or store to the address returned by the PHI node then we can consider this incoming value as dead and remove the edge pointing there, unless there are instructions that can affect control flow executed in between.
...
In theory this could be extended to other instructions, eg. division by zero, but it's likely that it will "miscompile" some code because people depend on div by zero not trapping. NULL pointer dereference usually leads to a crash so we should be on the safe side.
This shrinks the size of a Release clang by 16k on x86_64.
llvm-svn: 138618
2011-08-26 01:22:29 +00:00
8ac2041a19
Look at only the terminators of the basic block. Also, if we're using the new EH
...
scheme, return 'true' so that it doesn't try to run the old EH scheme's fixup on
the new code.
llvm-svn: 138605
2011-08-25 23:48:11 +00:00
45449b1cba
Initial check in that will auto-upgrade the old EH scheme to the new EH scheme.
...
This upgrade suffers from the problems of the old EH scheme - i.e., that the
calls to llvm.eh.exception() and llvm.eh.selector() can wander off and get
lost. It makes a valiant effort to reclaim these little lost lambs.
This is a first draft, so it hasn't yet been hooked up to the parser.
llvm-svn: 138602
2011-08-25 23:22:40 +00:00
ed834810be
Do the same as r138461. Mark VZEROALL as clobbering all YMM registers
...
llvm-svn: 138592
2011-08-25 22:23:58 +00:00
64bfca1b60
Remove stray fullstop.
...
llvm-svn: 138589
2011-08-25 21:46:20 +00:00
8347b86293
Add support for AVX 256-bit version of MOVDDUP!
...
llvm-svn: 138588
2011-08-25 21:40:37 +00:00
388eacee2c
Make isMOVDDUP mask check more strict and update comments!
...
llvm-svn: 138587
2011-08-25 21:40:34 +00:00
5e30972cff
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
...
llvm-svn: 138575
2011-08-25 18:30:18 +00:00
5a122f37fe
Intel family 6 model 44 is Gulftown/Westmere-EP and doesn't have AVX.
...
llvm-svn: 138573
2011-08-25 18:05:56 +00:00
6446bf780a
ARM fix for missing implicit operands on ldmia_ret.
...
rdar://10005094: miscompile of 176.gcc
llvm-svn: 138568
2011-08-25 17:50:53 +00:00
f7ecc16c96
whitespace
...
llvm-svn: 138566
2011-08-25 17:40:54 +00:00
1c171b121a
Explicitly disallow predication in Thumb1 assembly.
...
llvm-svn: 138562
2011-08-25 17:23:55 +00:00
14380ff9a0
Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678.
...
llvm-svn: 138553
2011-08-25 08:11:01 +00:00
e1541838f9
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
...
llvm-svn: 138551
2011-08-25 06:57:46 +00:00
3fb137f7ef
LSR wants to split the landing pad's critical edge. Let it do it, but use the
...
proper function to do it.
llvm-svn: 138550
2011-08-25 05:55:40 +00:00
88e6d5945f
Initialize member variable.
...
llvm-svn: 138548
2011-08-25 04:04:18 +00:00
296256fb32
Add support for 256-bit versions of VSHUFPD and VSHUFPS.
...
llvm-svn: 138546
2011-08-25 02:58:26 +00:00
54366cc332
Add memory version of SHUFPD to mask decoding!
...
llvm-svn: 138545
2011-08-25 02:58:21 +00:00
9dad430486
Hide -global-merge option.
...
llvm-svn: 138540
2011-08-25 01:22:49 +00:00
07efd6f1e0
When inserting new instructions, use getFirstInsertionPt instead of
...
getFirstNonPHI so that it will skip over the landingpad instructions as well.
llvm-svn: 138537
2011-08-25 01:08:34 +00:00
f066b2fe99
Add a command line option to disable global merge pass.
...
llvm-svn: 138536
2011-08-25 01:00:36 +00:00
3ca20e64ac
Remove a out-of-place comment.
...
llvm-svn: 138534
2011-08-25 00:54:42 +00:00
50d74211df
Create a section for non-instructions patterns in the beginning of the
...
file, and move more code around!
llvm-svn: 138521
2011-08-24 23:18:11 +00:00
2fb51d38e6
Move code around!
...
llvm-svn: 138520
2011-08-24 23:18:09 +00:00
fb702fe8d6
Organize UNPCK* patterns, also add remaining for AVX.
...
llvm-svn: 138519
2011-08-24 23:18:06 +00:00
9ade17b7f2
Move remaining MOVDDUP patterns close to MOVDDUP defintion and duplicate
...
the missing ones for AVX.
llvm-svn: 138518
2011-08-24 23:18:04 +00:00
c1e1e7ab97
Organize and tidy up MOVDDUP section. Also update comments!
...
llvm-svn: 138517
2011-08-24 23:18:02 +00:00
813891a215
Move MOVHLPS patterns close to MOVHLPS definition, and duplicate the
...
pattern for 128-bit AVX mode.
llvm-svn: 138516
2011-08-24 23:17:59 +00:00
9566a66a7c
Move all PSHUF* patterns close to the PSHUF* definitions. Also be
...
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Remove old and now wrong comments!
llvm-svn: 138515
2011-08-24 23:17:57 +00:00
2953d7b320
Move all SHUFP* patterns close to the SHUFP* definitions. Also be
...
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Make the mask check more strict, to be
clear it won't be used to match to 256-bit versions!
llvm-svn: 138514
2011-08-24 23:17:55 +00:00
37612a3de3
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
...
llvm-svn: 138507
2011-08-24 22:40:22 +00:00
9c73a57b20
Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually.
...
llvm-svn: 138505
2011-08-24 22:33:28 +00:00
eee864520c
Some autoconf tests use module level inline asm to test compiler's handling of
...
.cfi_startproc. e.g. libffi:
$ cat confopt.c
asm (".cfi_startproc\n\t.cfi_endproc");
int main () { return 0; }
Teach MC / dwarf emission to handle these cfi directives which essentially
create an empty frame.
rdar://10017184
llvm-svn: 138504
2011-08-24 22:31:37 +00:00
21a60b6f90
ARM asm backend initialize isThumbMode based on target triple.
...
llvm-svn: 138501
2011-08-24 22:27:35 +00:00
838ed3af46
Thumb .n mnemonic qualifiers can be ignored for now.
...
We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.
llvm-svn: 138500
2011-08-24 22:19:48 +00:00
4b701af908
Thumb parsing and encoding for SUB (SP minu immediate).
...
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
llvm-svn: 138494
2011-08-24 21:42:27 +00:00
216cfaa808
Be careful not to walk off the end of the operand info list while updating VFP predicates.
...
llvm-svn: 138492
2011-08-24 21:35:46 +00:00
0a0b3071df
Thumb parsing and encoding support for ADD SP instructions.
...
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
llvm-svn: 138488
2011-08-24 21:22:15 +00:00
38cd821dc4
Fix whitespace.
...
llvm-svn: 138487
2011-08-24 21:17:30 +00:00
86c5cbe613
Skip the landingpad instruction when determining the insertion point.
...
llvm-svn: 138481
2011-08-24 21:06:46 +00:00
342e8df0e0
Basic x86 code generation for atomic load and store instructions.
...
llvm-svn: 138478
2011-08-24 20:50:09 +00:00
0902a68f69
Use getFirstInsertionPt instead of getFirstNonPHI so that it skips to the proper
...
insertion place.
llvm-svn: 138473
2011-08-24 20:28:43 +00:00
365af6f17b
Implement Constant::isAllOnesValue(). Fix ConstantFolding to use the new api.
...
llvm-svn: 138469
2011-08-24 20:18:38 +00:00
af2f827a2c
When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
...
rdar://10015134
llvm-svn: 138467
2011-08-24 20:06:14 +00:00
ce02840633
Mark VZEROALL as clobbering all YMM registers
...
llvm-svn: 138461
2011-08-24 18:48:33 +00:00
6ccd79f4d5
Add missing explicit writeback operand to tSTMIA_UPD.
...
rdar://10014745
llvm-svn: 138457
2011-08-24 18:19:42 +00:00
2bb4035707
Move TargetRegistry and TargetSelect from Target to Support where they belong.
...
These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
d3e65e702f
Fix a crashing bug in SplitBlock when it is called on a block with no
...
dominator information even though dominators were previously computed.
Patch by Nick Sumner.
llvm-svn: 138449
2011-08-24 18:07:01 +00:00
a281f2d07d
Thumb add SP assembly syntax fix.
...
llvm-svn: 138448
2011-08-24 18:04:27 +00:00
1b8457a84c
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
...
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
llvm-svn: 138445
2011-08-24 17:46:13 +00:00
523004145e
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
...
llvm-svn: 138443
2011-08-24 17:21:43 +00:00
dee9e8a37c
Tidy up. Trailing whitespace.
...
llvm-svn: 138437
2011-08-24 16:44:17 +00:00
6e3c83eb1c
Add Uses=[SP] to call instructions. This fixes a miscompilation with a
...
variable sized alloca.
llvm-svn: 138433
2011-08-24 13:32:43 +00:00
de92622aa5
Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.
...
llvm-svn: 138427
2011-08-24 06:14:18 +00:00
f4ee0c0db2
Add the sentinal "no handle" value to the ResumeInst.
...
A value of -1 at a call site tells the personality function that this call isn't
handled by the current function. Since the ResumeInsts are converted to calls to
_Unwind_SjLj_Resume, add a (volatile) store of -1 to its 'call site'.
llvm-svn: 138416
2011-08-24 00:00:23 +00:00
2d4f0bea57
Don't replace *all* uses with the new stuff.
...
This is not necessarily the first or dominating use of the EH values. The IR
breaks if it's not. So replace the specific value in the instruction with the
new value.
llvm-svn: 138406
2011-08-23 22:55:03 +00:00
01a325a40e
Look at the end of the entry block for an invoke.
...
The invoke could be at the end of the entry block. If it's the only one, then we
won't process all of the landingpad instructions correctly. This code is
currently ugly, but should be made much nicer once the new EH switch is thrown.
llvm-svn: 138397
2011-08-23 22:20:16 +00:00
9e9f2ce32d
Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit
...
permutations. Also tidy up some patterns and make them close to their
instruction definition!
llvm-svn: 138392
2011-08-23 22:06:37 +00:00
4eb0433672
A landingpad instruction is neither folded nor dead.
...
llvm-svn: 138387
2011-08-23 21:33:05 +00:00
51b554247d
Move ARM frame-unwinding EHABI handling a touch earlier.
...
It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.
llvm-svn: 138386
2011-08-23 21:32:34 +00:00
50b0f6669c
[SU]XT[BH] are only available on ARMv6 and up.
...
llvm-svn: 138373
2011-08-23 20:53:08 +00:00
43c322b5b2
Add some useful accessors to c++ api that appear to be missing from the c api
...
llvm-svn: 138371
2011-08-23 20:27:46 +00:00
4d6c9d711d
Some refactoring so TargetRegistry.h no longer has to include any files
...
from MC.
llvm-svn: 138367
2011-08-23 20:15:21 +00:00
7bc78f692c
Revert "Address Duncan's CR request:"
...
This reverts commit 20a05be15ea5271ab6185b83200fa88263362400. (svn rev 138340)
Conflicts:
test/Transforms/InstCombine/bitcast.ll
llvm-svn: 138366
2011-08-23 20:11:10 +00:00
5cc338da67
Thumb parsing and encoding for SVC.
...
llvm-svn: 138360
2011-08-23 19:49:10 +00:00
6b477b985b
Fix 80 col violations.
...
llvm-svn: 138356
2011-08-23 19:17:21 +00:00
4c8ff77f1b
PerformSubCombine to work on integers larger than i128. Fixes a crasher.
...
llvm-svn: 138354
2011-08-23 19:01:24 +00:00
505be75900
Thumb parsing and encoding for tSTRspi.
...
llvm-svn: 138348
2011-08-23 18:39:41 +00:00
d80d169a04
Thumb parsing and encoding for STM.
...
llvm-svn: 138345
2011-08-23 18:15:37 +00:00
169b2be611
Factor low reg checking into a helper function.
...
llvm-svn: 138344
2011-08-23 18:13:04 +00:00
924bcfc92f
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
...
llvm-svn: 138341
2011-08-23 17:51:38 +00:00
c78e6607b5
Address Duncan's CR request:
...
1. Cleanup the tests in ConstantFolding.cpp
2. Implement isAllOnes for Constant, ConstantFP, ConstantVector
llvm-svn: 138340
2011-08-23 17:48:43 +00:00
9b7bd15d0b
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
...
llvm-svn: 138339
2011-08-23 17:45:18 +00:00
e364ad540a
Clean up Thumb load/store multiple definitions.
...
There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.
llvm-svn: 138338
2011-08-23 17:41:15 +00:00
041dba6dec
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
...
llvm-svn: 138337
2011-08-23 17:37:32 +00:00
771ef8c66a
This patch adds support of le32 pseudo-cpu that stands for generic
...
32-bit little-endian CPU. Used by PNaCl and Emscripten.
llvm-svn: 138335
2011-08-23 16:59:00 +00:00
6612e35b0d
Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712.
...
llvm-svn: 138321
2011-08-23 04:36:33 +00:00
fd6cb64c48
lib/Support/Windows/Windows.h: Update required IE ver. 0x0600 should be enough for Windows XP.
...
llvm-svn: 138319
2011-08-23 03:49:11 +00:00
2a3ffb5d97
Introduce a pass to insert vzeroupper instructions to avoid AVX to
...
SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.
llvm-svn: 138317
2011-08-23 01:14:17 +00:00
3636be3c8f
Thumb parsing and encoding for SBC.
...
llvm-svn: 138311
2011-08-22 23:55:58 +00:00
c3c32d9e09
Thumb parsing and encoding for RSB.
...
llvm-svn: 138308
2011-08-22 23:47:13 +00:00
eb1367b2b8
Reject invalid imod values in t2CPS instructions.
...
llvm-svn: 138306
2011-08-22 23:44:04 +00:00
f0d2dfde4f
Split the landing pad's edge. Then for all uses of a landingpad instruction's
...
value, we insert a load of the exception object and selector object from memory,
which is where it actually resides. If it's used by a PHI node, we follow that
to where it is being used. Eventually, all landingpad instructions should have
no uses. Any PHI nodes that were associated with those landingpads should be
removed.
llvm-svn: 138302
2011-08-22 23:38:40 +00:00
1346d79b4b
t2SMLAD is a four-register instruction, not a three-register one.
...
llvm-svn: 138301
2011-08-22 23:31:45 +00:00
f94b7b7d57
Correct operand naming of t2USAT16 to allow proper decoding.
...
llvm-svn: 138300
2011-08-22 23:27:47 +00:00
bfeb4f78af
Revert r138278 now that r138289 has fixed the root issue.
...
llvm-svn: 138299
2011-08-22 23:25:48 +00:00
5e9989a920
Match operand naming to allow correct decoding of t2LDRSH_POST.
...
llvm-svn: 138298
2011-08-22 23:22:05 +00:00
38c59fcb08
Improve error checking for tPUSH and tPOP register lists.
...
llvm-svn: 138295
2011-08-22 23:17:34 +00:00
2844a81079
Match operand names to provide correct decoding for Thumb2 SMULL.
...
llvm-svn: 138294
2011-08-22 23:16:48 +00:00
a743409ec8
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
...
llvm-svn: 138292
2011-08-22 23:10:16 +00:00
b296790bb6
Add NativeClient support to Triple::ParseOS.
...
llvm-svn: 138291
2011-08-22 23:08:53 +00:00
6aa2744bed
Follow up to Jim's r138278. This fixes commuteInstruction so it handles two-address instructions correctly. I'll let Jim add a test case. :-)
...
llvm-svn: 138289
2011-08-22 23:04:56 +00:00
139acd21e6
Thumb assemmbly parsing diagnostic improvements for LDM.
...
llvm-svn: 138287
2011-08-22 23:01:07 +00:00
9dc808e74d
X86: Add some operand types required to identify calls.
...
llvm-svn: 138285
2011-08-22 22:55:32 +00:00
ca2ffad8b1
Temporarilly mark tMUL as not commutable.
...
It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.
llvm-svn: 138278
2011-08-22 22:00:18 +00:00
061738a680
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
...
llvm-svn: 138273
2011-08-22 21:34:00 +00:00
74f090d44c
Add support for breaking 256-bit int VETCC into two 128-bit ones,
...
avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.
llvm-svn: 138271
2011-08-22 20:31:04 +00:00
6e62ca940a
Add 128-bit AVX codegen for PCMP* family of integer instructions
...
llvm-svn: 138270
2011-08-22 20:31:00 +00:00
df698b032c
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
...
llvm-svn: 138269
2011-08-22 20:27:12 +00:00
5765f4c24c
Make DynamicLibrary thread-safe w/r/t call to dlerror() after dlopen(). PR10718
...
llvm-svn: 138260
2011-08-22 19:01:52 +00:00
5c932b24be
Tighten up ARM reglist validation a bit.
...
llvm-svn: 138258
2011-08-22 18:50:36 +00:00
3aaed0a14c
Some whitespace fixes and #include reordering.
...
llvm-svn: 138256
2011-08-22 18:44:49 +00:00
721c3704da
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
...
llvm-svn: 138255
2011-08-22 18:42:13 +00:00
97f73cb449
Be less redundant.
...
llvm-svn: 138252
2011-08-22 18:26:12 +00:00
ac92e77bb8
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
...
llvm-svn: 138251
2011-08-22 18:22:06 +00:00
6caa557ae6
Clean up predicates on ARM target instruction aliases.
...
llvm-svn: 138249
2011-08-22 18:04:24 +00:00
b49813206b
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
...
llvm-svn: 138246
2011-08-22 17:56:58 +00:00
4b8e8ce37f
Add a comment.
...
llvm-svn: 138243
2011-08-22 17:29:37 +00:00
56e1cef705
Constant pointers to objects don't need reference counting.
...
llvm-svn: 138242
2011-08-22 17:29:11 +00:00
58994ec9b9
PathV2: Handle more reserved filenames on windows.
...
Patch by Aaron Ballman!
llvm-svn: 138213
2011-08-20 21:36:38 +00:00
bd16424f91
Fix AsmParser binary precedence for shift operators.
...
rdar://9976729
llvm-svn: 138208
2011-08-20 16:24:13 +00:00
ad4a70ad3e
Add constant folding support for bitcasts of splat vectors to integers.
...
llvm-svn: 138206
2011-08-20 14:02:29 +00:00
1eae12cc9f
lib/Support/CrashRecoveryContext.cpp: Add Win32 support to CrashRecoveryContext. Thanks to Aaron Ballman!
...
llvm-svn: 138199
2011-08-20 06:35:36 +00:00
613655f89c
lib/Support/Windows/Windows.h: Require at least Windows XP(5.1) API. We will not support Windows 2000 any more.
...
llvm-svn: 138198
2011-08-20 06:35:31 +00:00
5800a8c3ad
Cast through intptr_t, ISO C++ requires it.
...
llvm-svn: 138186
2011-08-20 02:22:42 +00:00
61f92efb5c
Remove the VMOVQQ pseudo instruction.
...
llvm-svn: 138177
2011-08-20 00:52:40 +00:00
baf5538da9
Remove VMOVQQQQ pseudo instruction.
...
llvm-svn: 138174
2011-08-20 00:40:14 +00:00
59015c8b17
Add <imp-def> operands to QQ and QQQQ stack loads.
...
This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.
llvm-svn: 138164
2011-08-20 00:17:45 +00:00
be7625161e
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
...
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.
llvm-svn: 138163
2011-08-20 00:17:25 +00:00
38d813087e
If we're splitting the landing pad block and assigning it only one predecessor,
...
then don't split it a second time, since that block will be dead.
llvm-svn: 138153
2011-08-19 23:46:30 +00:00
59e27c5f12
Do not use named md nodes to track variables that are completely optimized. This does not scale while doing LTO with debug info. New approach is to include list of variables in the subprogram info directly.
...
llvm-svn: 138145
2011-08-19 23:28:12 +00:00
2597722e07
Thumb parsing and encoding support for NOP.
...
The irony is not lost that this is not a completely trivial patchset.
llvm-svn: 138143
2011-08-19 23:24:36 +00:00
419fd4f315
Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not
...
needed for Mips32.
llvm-svn: 138132
2011-08-19 22:59:00 +00:00
37aa348195
Thumb assembly parsing and encoding for NEG.
...
llvm-svn: 138131
2011-08-19 22:51:03 +00:00
68ed46ce9a
Roll back the rest of r126557. It's a hack that will break in some obscure cases.
...
llvm-svn: 138130
2011-08-19 22:39:31 +00:00
8022015a16
Fix NEG alias
...
llvm-svn: 138125
2011-08-19 22:30:58 +00:00
459422d750
Be more lenient on tied operand matching for MUL.
...
llvm-svn: 138124
2011-08-19 22:30:46 +00:00
d126347f32
Re-write part of VEX encoding logic, to be more easy to read! Also fix
...
a bug and add a testcase!
llvm-svn: 138123
2011-08-19 22:27:29 +00:00
066e9ec1e4
Update tests.
...
llvm-svn: 138116
2011-08-19 22:19:48 +00:00
8e048495c8
Thumb assembly parsing and encoding for MUL.
...
llvm-svn: 138108
2011-08-19 22:07:46 +00:00
26e19288be
The landingpad instruction isn't dead simply because it's value isn't used.
...
llvm-svn: 138102
2011-08-19 21:52:06 +00:00
c1348074ec
Eli points out that this is what report_fatal_error() is for.
...
llvm-svn: 138091
2011-08-19 21:45:19 +00:00
f86cd37bef
Thumb assembly parsing and encoding for MOV.
...
llvm-svn: 138076
2011-08-19 20:46:54 +00:00
dbb60f960a
Tidy up. Tab character.
...
llvm-svn: 138072
2011-08-19 20:30:19 +00:00
3f73184d90
This is not actually unreachable, so don't use llvm_unreachable for it. Since
...
the intent seems to be to terminate even in Release builds, just use abort()
directly.
If program flow ever reaches a __builtin_unreachable (which llvm_unreachable is
#define'd to on newer GCCs) then the program is undefined.
llvm-svn: 138068
2011-08-19 20:14:27 +00:00
9c92049069
Tab characters.
...
llvm-svn: 138066
2011-08-19 19:41:46 +00:00
5503c3a4e8
Thumb assembly parsing and encoding for LSL(immediate).
...
llvm-svn: 138063
2011-08-19 19:29:25 +00:00
7c4739da3c
Thumb assembly parsing and encoding for LDRSB and LDRSH.
...
llvm-svn: 138061
2011-08-19 19:17:58 +00:00
26d3587bd8
Thumb assembly parsing and encoding for LDRH.
...
llvm-svn: 138060
2011-08-19 18:55:51 +00:00
a32c753ebf
Thumb assembly parsing and encoding for LDRB.
...
llvm-svn: 138059
2011-08-19 18:49:59 +00:00
7b3379be20
Fixed a memory bug in the MCDisassembler where
...
MCParsedAsmOperand objects were being leaked.
llvm-svn: 138053
2011-08-19 18:23:06 +00:00
181d2f92b5
Thumb assembly parsing and encoding for LDR(literal).
...
llvm-svn: 138052
2011-08-19 18:20:48 +00:00
23983d6bd9
Thumb assembly parsing and encoding for LDR(immediate) form T2.
...
llvm-svn: 138050
2011-08-19 18:13:48 +00:00
7473329725
Use helper function to check for low registers.
...
llvm-svn: 138048
2011-08-19 17:57:22 +00:00
3fe94e3ef8
Thumb assembly parsing and encoding for LDR(immediate) form T1.
...
llvm-svn: 138047
2011-08-19 17:55:24 +00:00
e93807049b
Add explanatory comment.
...
llvm-svn: 138042
2011-08-19 16:52:32 +00:00
024d2614b6
Have SPU backend use the external TCE scheduler, if the library is loaded as a
...
module.
Patch by Pekka Jääskeläinen.
llvm-svn: 138037
2011-08-19 10:50:24 +00:00
ba6c2a52c7
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
...
llvm-svn: 138034
2011-08-19 05:28:50 +00:00
22241acc29
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
...
implementation!
llvm-svn: 138029
2011-08-19 02:23:56 +00:00
6949077f74
Add llc flags to disable machine DCE and CSE.
...
This is useful for unit tests.
llvm-svn: 138028
2011-08-19 02:05:35 +00:00
4938edb02c
Make a bunch of symbols private.
...
llvm-svn: 138025
2011-08-19 01:42:18 +00:00
5a656883b1
C API functions must be able to see their extern "C" definitions, or it will be impossible to call them from C.
...
llvm-svn: 138022
2011-08-19 01:36:54 +00:00
9eb77bf615
Don't treat a partial <def,undef> operand as a read.
...
Normally, a partial register def is treated as reading the
super-register unless it also defines the full register like this:
%vreg110:sub_32bit<def> = COPY %vreg77:sub_32bit, %vreg110<imp-def>
This patch also uses the <undef> flag on partial defs to recognize
non-reading operands:
%vreg110:sub_32bit<def,undef> = COPY %vreg77:sub_32bit
This fixes a subtle bug in RegisterCoalescer where LIS->shrinkToUses
would treat a coalesced copy as still reading the register, extending
the live range artificially.
My test case only works when I disable DCE so a dead copy is left for
RegisterCoalescer, so I am not including it.
<rdar://problem/9967101>
llvm-svn: 138018
2011-08-19 00:30:17 +00:00
b38940135b
Track a retain+release nesting level independently of the
...
known-incremented level, because the two concepts can be used
to prove the saftey of a retain+release removal in different
ways.
llvm-svn: 138016
2011-08-19 00:26:36 +00:00
c61f7659ba
Intelligently split the landing pad block.
...
We have to be careful when splitting the landing pad block, because the
landingpad instruction is required to remain as the first non-PHI of an invoke's
unwind edge. To retain this, we split the block into two blocks, moving the
predecessors within the loop to one block and the remaining predecessors to the
other. The landingpad instruction is cloned into the new blocks.
llvm-svn: 138015
2011-08-19 00:09:22 +00:00
ca7d309623
Add SplitLandingPadPredecessors().
...
SplitLandingPadPredecessors is similar to SplitBlockPredecessors in that it
splits the current block and attaches a set of predecessors to the new basic
block. However, it differs from SplitBlockPredecessors in that it's specifically
designed to handle landing pad blocks.
Two new basic blocks are created: one that is has the vector of predecessors as
its predecessors and one that has the remaining predecessors as its
predecessors. Those two new blocks then receive a cloned copy of the landingpad
instruction from the original block. The landingpad instructions are joined in a
PHI, etc. Like SplitBlockPredecessors, it updates the LLVM IR, AliasAnalysis,
DominatorTree, DominanceFrontier, LoopInfo, and LCCSA analyses.
llvm-svn: 138014
2011-08-19 00:05:40 +00:00
5647d84aa4
Re-encoded 128-bit AVX versions of SQRT, RSQRT, RCP have 3 operands
...
instead of 2. They were already defined this way in their regular
version, but not for the intrinsics versions (*_Int), and that would work
for assembly emission but not for object code, since a MachineOperand
would be missing. This commit fix PR10697.
Also removed the {VSQRT,VRSQRT,VRCP}r_Int forms and match the intrinsic
via INSERT_SUBREG+EXTRACT_SUBREG patterns. The same couldn't be done for
memory versions because sse_load_f32/sse_load_f64 operand need special
handling and don't work like regular "addr" operands.
There are right now 114 "*_Int" and 98 "Int_*" forms! I'm slowly
removing them as I step through, but hope we can get rid of these
someday, they are really annoying :)
llvm-svn: 138012
2011-08-18 23:59:21 +00:00
425b4dcc30
There is no need to add file as context for subroutine type. The subroutine type does not need any context.
...
llvm-svn: 138010
2011-08-18 23:50:57 +00:00
c8d4065781
add the comments of each declaration follow it, making it easier to read and compare to GCC's result.
...
llvm-svn: 138009
2011-08-18 23:43:14 +00:00
2b31c45e8e
Use 'getFirstInsertionPt' when trying to insert new instructions during LICM.
...
llvm-svn: 138008
2011-08-18 23:42:36 +00:00
fb4161ae88
Use subword loads instead of a 4-byte load when the size of a structure (or a
...
piece of it) that is being passed by value is smaller than a word.
llvm-svn: 138007
2011-08-18 23:39:37 +00:00
0ecbcbd12c
Eliminate unnecessary forwarding function.
...
llvm-svn: 138006
2011-08-18 23:17:55 +00:00
44306e2e5f
Add NativeClient operating system support.
...
This patch adds support of NativeClient (*-*-nacl) OS support to LLVM.
It's already supported in autoconf/config.sub.
The motivation for this change is to start upstreaming PNaCl work. The
whole set of patches include llvm backends (i686, x86_64, ARM),
llvm-gcc (probably, would not be upstreamed because it's deprecated)
and clang (the work has been just started, the amount of changes is
going to be low and the most of the work is expected to be done close
to the mainline).
llvm-svn: 138005
2011-08-18 22:54:21 +00:00
96b7ad2e17
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
...
Found by randomized testing.
llvm-svn: 138003
2011-08-18 22:47:44 +00:00
192a760b54
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
...
llvm-svn: 138000
2011-08-18 22:31:17 +00:00
a6576a146d
Add new DIE into the map asap.
...
llvm-svn: 137998
2011-08-18 22:21:50 +00:00
5d2db89ba6
Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.
...
llvm-svn: 137997
2011-08-18 22:15:25 +00:00
67d6f11974
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
...
Fixes a large class of disassembler crashes found by randomized testing.
llvm-svn: 137995
2011-08-18 22:11:02 +00:00
d7cbd4c518
FastISel: avoid function calls between the materialization of the constant and its use.
...
llvm-svn: 137993
2011-08-18 22:06:10 +00:00
90103ccc05
Thumb assembly parsing and encoding for LDM instruction.
...
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
llvm-svn: 137986
2011-08-18 21:50:53 +00:00
c57b58cc40
Make it clear that this code is iterating in reverse order through the array.
...
llvm-svn: 137985
2011-08-18 21:27:42 +00:00
b15d6eb93b
Revert r137871. The loop simplify pass should require all exits from a loop that
...
aren't from an indirect branch need to be dominated by the loop header.
llvm-svn: 137981
2011-08-18 21:10:01 +00:00
b267e2a7ec
Split out the updating of PHI nodes after splitting the BB into a separate
...
function.
llvm-svn: 137979
2011-08-18 20:51:04 +00:00
ec3823dcb7
Use this fantzy ArrayRef thing to pass in the list of predecessors.
...
llvm-svn: 137978
2011-08-18 20:39:32 +00:00
73d78b7ab1
Make IsShiftedMask a static function rather than defining it in an
...
anonymous namespace.
llvm-svn: 137975
2011-08-18 20:07:42 +00:00
74acf9f501
The edge from DISubprogram to DICompileUnit has been removed in recent versions
...
of debug info.
llvm-svn: 137972
2011-08-18 19:07:42 +00:00
4f240a1fd5
Thumb assembly parsing and encoding for CMP.
...
llvm-svn: 137963
2011-08-18 18:08:29 +00:00
6029135af9
Use static instead of anonymous namespace.
...
llvm-svn: 137959
2011-08-18 17:57:57 +00:00
8a6bed863a
Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.
...
llvm-svn: 137956
2011-08-18 17:51:36 +00:00
3048afb988
Rip out the old StructType APIs as warned about on llvmdev last week.
...
llvm-svn: 137953
2011-08-18 17:39:28 +00:00
f00b9ccd22
ARM Thumb blx instruction fixup has same data range as bl.
...
These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.
llvm-svn: 137947
2011-08-18 16:57:50 +00:00
8fa3f6a2b4
80 columns.
...
llvm-svn: 137946
2011-08-18 16:50:45 +00:00
2b8078a2cd
Clenup and fix encoding for Mips ins and ext instruction
...
llvm-svn: 137943
2011-08-18 16:30:49 +00:00
6ddb568ab8
Add missing 'break'.
...
llvm-svn: 137941
2011-08-18 16:08:39 +00:00
56f3b70225
Add intrinsics for SETEV, GETED, GETET.
...
llvm-svn: 137938
2011-08-18 13:00:48 +00:00
2f2e9c5057
Remove unused variable.
...
llvm-svn: 137933
2011-08-18 08:13:18 +00:00
0a693f47ee
Split out the analysis updating code into a helper function. No intended
...
functionality change.
llvm-svn: 137926
2011-08-18 05:25:23 +00:00
3c7d6eb64c
Cleanup vector logical ops in AVX and add use int versions for simple
...
v2i64
llvm-svn: 137919
2011-08-18 02:11:34 +00:00
53771ba07c
Dramatically speedup codegen prepare by a) avoiding use of dominator tree and b) doing a separate pass over dbg.value instructions.
...
llvm-svn: 137908
2011-08-18 00:50:51 +00:00
50aafeaa2c
Remove extraneous newline from operand print method. PR10569.
...
llvm-svn: 137900
2011-08-17 23:23:07 +00:00
23b729eeba
Clean up patterns for Thumb1 system instructions.
...
llvm-svn: 137897
2011-08-17 23:08:57 +00:00
eea541ce4e
Changed definition of EXT and INS per Bruno's comments.
...
llvm-svn: 137892
2011-08-17 22:59:46 +00:00
cbd4ab104b
Thumb assembly parsing and encoding for B.
...
llvm-svn: 137891
2011-08-17 22:57:40 +00:00
2b21d86cfe
Do not use DebugInfoFinder. Extract debug info directly from llvm.dbg.cu named mdnode.
...
llvm-svn: 137890
2011-08-17 22:49:38 +00:00
d3e8e29124
Thumb assembly parsing and encoding for ASR.
...
llvm-svn: 137889
2011-08-17 22:49:09 +00:00
9a468153e1
Atomic load/store handling for the passes using memdep (GVN, DSE, memcpyopt).
...
llvm-svn: 137888
2011-08-17 22:22:24 +00:00
1a87fcb9ba
Fix PR10688. Add support for spliting 256-bit vector shifts when the
...
shift amount is variable
llvm-svn: 137885
2011-08-17 22:12:20 +00:00
d14b70d00b
Tidy up. 80 columns.
...
llvm-svn: 137881
2011-08-17 21:58:18 +00:00
247fd3bf59
Add the support in code-gen for the landingpad instruction lowering.
...
The landingpad instruction is lowered into the EXCEPTIONADDR and EHSELECTION
SDNodes. The information from the landingpad instruction is harvested by the
'AddLandingPadInfo' function. The new EH uses the current EH scheme in the
back-end. This will change once we switch over to the new scheme. (Reviewed by
Jakob!)
llvm-svn: 137880
2011-08-17 21:56:44 +00:00
46dd413991
ARM clean up the imm_sr operand class representation.
...
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
llvm-svn: 137879
2011-08-17 21:51:27 +00:00
8bbcbedeaf
Disable PRE for landing pads.
...
PRE needs the landing pads to have their critical edges split. Doing this for a
landing pad is non-trivial. Abandon the attempt to perform PRE when we come
across a landing pad. (Reviewed by Owen!)
llvm-svn: 137876
2011-08-17 21:32:02 +00:00
a408e5bf31
Revert patch. Forgot a dependent commit.
...
llvm-svn: 137875
2011-08-17 21:28:05 +00:00
2a521948f0
Add the body of 'visitLandingPad'.
...
This generates the SDNodes for the new exception handling scheme. It takes the
two values coming from the landingpad instruction and assigns them to the
EXCEPTIONADDR and EHSELECTION nodes.
llvm-svn: 137873
2011-08-17 21:25:14 +00:00
79a6873d9c
Increment the insertion iterator to beyond the landingpad instruction.
...
llvm-svn: 137872
2011-08-17 21:21:31 +00:00
39257d6b5c
Don't optimize the landing pad exit block.
...
One way to exit the loop is through an unwind edge. However, that may involve
splitting the critical edge of the landing pad, which is non-trivial. Prevent
the transformation from rewriting the landing pad exit loop block.
llvm-svn: 137871
2011-08-17 21:20:43 +00:00
2dfbcc4506
Assert that we aren't trying to split the critical edge of a landing pad. Doing
...
so requires more care than this generic algorithm should handle.
llvm-svn: 137866
2011-08-17 21:04:05 +00:00
854fe433d4
Fix predicate for imm1_32
...
llvm-svn: 137865
2011-08-17 21:01:11 +00:00
e2a0404a69
Thumb assembly parsing and encoding for ADR.
...
llvm-svn: 137864
2011-08-17 20:37:40 +00:00
a9ee09f4be
Revert r137655. There is some question about whether the 'landingpad'
...
instruction should be marked as potentially reading and/or writing memory.
llvm-svn: 137863
2011-08-17 20:36:44 +00:00
3b5a69cc45
80 columns.
...
llvm-svn: 137857
2011-08-17 19:55:51 +00:00
8637523886
Tidy up.
...
llvm-svn: 137856
2011-08-17 19:53:53 +00:00
1cdd7fdf54
Modify for the new EH scheme.
...
Things are much saner now. We no longer need to modify the laning pads, because
of the invariants we impose upon them. The only thing DwarfEHPrepare needs to do
is convert the 'resume' instruction into a call to '_Unwind_Resume'.
llvm-svn: 137855
2011-08-17 19:48:49 +00:00
ad3cfe7933
Revert r137781; I agree with Duncan's comment that the situation in question is clearly impossible given the current structure of the code.
...
llvm-svn: 137853
2011-08-17 19:31:49 +00:00
b2e7558c40
Add support for half-word unaligned loads and stores.
...
llvm-svn: 137848
2011-08-17 18:49:18 +00:00
04bc405a29
Static fields require an out-of-line definition. Fix DynamicLibrary for real.
...
llvm-svn: 137844
2011-08-17 18:38:42 +00:00
187e1e46f9
Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.
...
llvm-svn: 137838
2011-08-17 18:14:48 +00:00
d7749be2d7
Silly mistake from r137777; restore significant isStructTy() checks. While here, be a bit more defensive
...
with unknown instructions.
Fixes PR10687.
llvm-svn: 137836
2011-08-17 18:10:43 +00:00
184b63d09c
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment.
...
llvm-svn: 137831
2011-08-17 17:45:08 +00:00
a4043c4b32
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
...
Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
be5e987379
Introduce matching patterns for vbroadcast AVX instruction. The idea is to
...
match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.
llvm-svn: 137810
2011-08-17 02:29:19 +00:00
6d33c7f303
Update comments about vector splat handling in x86
...
llvm-svn: 137808
2011-08-17 02:29:13 +00:00
ed786a346e
Now that we have a canonical way to handle 256-bit splats:
...
vinsertf128 $1 + vpermilps $0, remove the old code that used to first
do the splat in a 128-bit vector and then insert it into a larger one.
This is better because the handling code gets simpler and also makes a
better room for the upcoming vbroadcast!
llvm-svn: 137807
2011-08-17 02:29:10 +00:00
5360f88355
Add support for ext and ins.
...
llvm-svn: 137804
2011-08-17 02:05:42 +00:00
1a3ca9201a
Unbork Windows build. Thanks, Francois.
...
llvm-svn: 137798
2011-08-17 00:59:50 +00:00
a19917da7c
Use DynamicLibrary instances as a way to get symbols from a specific library. Preparation for upcoming (preliminary) support for plugins for the static analyzer.
...
llvm-svn: 137791
2011-08-17 00:29:32 +00:00
e9ab47a72a
Thumb ADD(immediate) parsing support.
...
llvm-svn: 137788
2011-08-16 23:57:34 +00:00
91a8f9be20
Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
...
llvm-svn: 137787
2011-08-16 23:45:44 +00:00
55919a9ed7
Extend the undef ^ undef idiom once more. No testcase: I can't figure out how to actually trigger the codepath in question at the moment, but it might get exposed in the future.
...
llvm-svn: 137781
2011-08-16 22:38:34 +00:00
b7fa2c0a53
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
...
llvm-svn: 137779
2011-08-16 22:20:01 +00:00
eb1bb4e419
Until now all debug info MDNodes referred to a root MDNode, a compile unit. This simplified handling of these needs in dwarf writer. However, one side effect of this is that during link time optimization all these MDNodes are _not_ uniqued. In other words there will be N number of MDNodes describing "int", "char" and all other types, which would suddenly grow when each object file starts using libraries like STL.
...
MDNodes graph structure such that compiler unit keeps track of important MDNodes and update dwarf writer to process mdnodes top-down instead of bottom up.
llvm-svn: 137778
2011-08-16 22:09:43 +00:00
0793eb4c46
A bunch of misc fixes to SCCPSolver::ResolvedUndefsIn, including a fix to stop
...
making random bad assumptions about instructions which are not explicitly listed.
Includes fix for rdar://9956541, a version of "undef ^ undef should return
0 because it's easier than arguing with users".
llvm-svn: 137777
2011-08-16 22:06:31 +00:00
64610e52e7
Add missing exit for 'case'.
...
llvm-svn: 137774
2011-08-16 21:42:31 +00:00
58ffdccab1
Thumb assembly parsing and encoding for ADD(register) instruction.
...
llvm-svn: 137759
2011-08-16 21:34:08 +00:00
d7c6c9141a
The resume instruction may throw. Return 'true' in this case.
...
llvm-svn: 137757
2011-08-16 21:15:50 +00:00
7283da9bb2
Move some logic into a helper function and expand the commentary.
...
llvm-svn: 137756
2011-08-16 21:12:37 +00:00
56f2f21254
Minor bug in SCCP found by inspection. (I don't think it's possible to hit this with a normal pass pipeline, but fixing for completeness.)
...
llvm-svn: 137755
2011-08-16 21:12:35 +00:00
3e941aee69
ARM thumb assembly parsing for arithmetic flag setting instructions.
...
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
llvm-svn: 137746
2011-08-16 20:45:50 +00:00
8ddfc09e7a
Use the getFirstInsertionPt() method instead of getFirstNonPHI + an 'isa<>'
...
check for a LandingPadInst.
llvm-svn: 137745
2011-08-16 20:45:24 +00:00
ee1c2d2437
Add getFirstInsertionPt() method.
...
getFirstInsertionPt() returns an iterator to the first insertion point in a
basic block. This is after all PHIs and any other instruction which is required
to be at the top of the basic block (like LandingPadInst).
llvm-svn: 137744
2011-08-16 20:42:52 +00:00
55d875fa1c
I think there was some confusion about what I meant. :-) Replacing the comment.
...
llvm-svn: 137743
2011-08-16 20:41:17 +00:00
345768c9ff
Remove unused Target argument from AsmParser construction methods.
...
The argument is unused, and is a layering violation in any case.
llvm-svn: 137735
2011-08-16 18:33:49 +00:00
2e99f1b3aa
Instead of always leaving the work to the generic legalizer when
...
there is no support for native 256-bit shuffles, be more smart in some
cases, for example, when you can extract specific 128-bit parts and use
regular 128-bit shuffles for them. Example:
For this shuffle:
shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32>
<i32 1, i32 0, i32 7, i32 6>
This was expanded to:
vextractf128 $1, %ymm1, %xmm2
vpextrq $0, %xmm2, %rax
vmovd %rax, %xmm1
vpextrq $1, %xmm2, %rax
vmovd %rax, %xmm2
vpunpcklqdq %xmm1, %xmm2, %xmm1
vpextrq $0, %xmm0, %rax
vmovd %rax, %xmm2
vpextrq $1, %xmm0, %rax
vmovd %rax, %xmm0
vpunpcklqdq %xmm2, %xmm0, %xmm0
vinsertf128 $1, %xmm1, %ymm0, %ymm0
ret
Now we get:
vshufpd $1, %xmm0, %xmm0, %xmm0
vextractf128 $1, %ymm1, %xmm1
vshufpd $1, %xmm1, %xmm1, %xmm1
vinsertf128 $1, %xmm1, %ymm0, %ymm0
llvm-svn: 137733
2011-08-16 18:21:54 +00:00
927840458e
Remove unnecessary version check.
...
llvm-svn: 137728
2011-08-16 17:41:41 +00:00
45e50d8a0b
ARM .align NOP padding uses different encoding pre-ARMv6.
...
Patch by Kristof Beyls and James Malloy.
llvm-svn: 137723
2011-08-16 17:06:20 +00:00
b66b866f46
Revert r137562 because it caused PR10674
...
llvm-svn: 137719
2011-08-16 14:34:29 +00:00
719a72f34c
Add a mechanism for optimisation plugins to register passes that all front ends can use without needing to be aware of the plugin (or the plugin be aware of the front end).
...
Before 3.0, I'd like to add a mechanism for automatically loading a set of plugins from a config file. API suggestions welcome...
llvm-svn: 137717
2011-08-16 13:58:41 +00:00
be33e8d58d
A few places where we want to skip the landingpad instruction for insertion.
...
llvm-svn: 137712
2011-08-16 04:52:55 +00:00
2263c10946
Fix handling of double precision loads and stores when Mips1 is targeted.
...
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.
Without the changes made in this patch, llc produces code that has the same
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.
llvm-svn: 137711
2011-08-16 03:51:51 +00:00
77f1fd5e44
Define function MipsMCInstLower::LowerOperand.
...
llvm-svn: 137707
2011-08-16 02:21:03 +00:00
6520b9857f
Add parameter Offset to MipsMCInstLower::LowerSymbolOperand.
...
llvm-svn: 137706
2011-08-16 02:15:03 +00:00
a917d4f9b4
Revert a bit of r137667; the logic in question can safely handle atomic load/store.
...
llvm-svn: 137702
2011-08-16 01:28:22 +00:00
bd39703456
After talking with Bill, it seems like the LandingPad handling here is likely
...
to be wrong (or at least somewhat suspect). Leave a FIXME for Bill.
llvm-svn: 137694
2011-08-16 00:41:37 +00:00
b8f30de527
Minor comment fixes.
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llvm-svn: 137693
2011-08-16 00:20:11 +00:00
0ffdf2ea0b
Update SimplifyCFG for atomic operations.
...
This commit includes a mention of the landingpad instruction, but it's not
changing the behavior around it. I think the current behavior is correct,
though. Bill, can you double-check that?
llvm-svn: 137691
2011-08-15 23:59:28 +00:00
01a67111d1
Add comments and test for atomic load/store and mem2reg.
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llvm-svn: 137690
2011-08-15 23:55:52 +00:00
07bb9eea33
Refactor.
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llvm-svn: 137689
2011-08-15 23:47:24 +00:00
a6201f0a72
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
...
llvm-svn: 137686
2011-08-15 23:38:54 +00:00
c1676e41c0
While I'm here, remove the "_alt" hacks to a series of INSERT_SUBREG and
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also add the AVX versions of the 128-bit patterns
llvm-svn: 137685
2011-08-15 23:36:51 +00:00
67005029bc
Reorder declarations of vmovmskp* and also put the necessary AVX
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predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.
llvm-svn: 137684
2011-08-15 23:36:45 +00:00
1f4f98d664
Continue to hoist uses of getCompileUnit() up. The goal is to get rid of uses of getCompileUnit().
...
llvm-svn: 137683
2011-08-15 23:36:40 +00:00
5a18b7c7c7
In places where it's using "getFirstNonPHI", skip the landingpad instruction if necessary.
...
llvm-svn: 137679
2011-08-15 23:19:54 +00:00
120a96a721
MCTargetAsmParser target match predicate support.
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Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.
llvm-svn: 137675
2011-08-15 23:03:29 +00:00
2b8acaf4f3
Add a finalize() hook, that'll let DIBuilder construct compile unit lazily.
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llvm-svn: 137673
2011-08-15 23:00:00 +00:00
91d4e9edec
Don't sink the instruction to before a landingpad instruction.
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llvm-svn: 137672
2011-08-15 22:53:05 +00:00
d2dfc5ec02
This is somewhat déjà-vu, but avoid using getCompileUnit() as much as possible.
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llvm-svn: 137668
2011-08-15 22:24:32 +00:00
211e348eaa
Update inter-procedural optimizations for atomic load/store.
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llvm-svn: 137667
2011-08-15 22:16:46 +00:00
8bc586e770
Update instcombine for atomic load/store.
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llvm-svn: 137664
2011-08-15 22:09:40 +00:00
3acc70e536
Refactor. Variables are part of compile unit so let CompileUnit create new variable.
...
llvm-svn: 137663
2011-08-15 22:04:40 +00:00
4419cd2464
Add some comments here because the lack of a check for volatile/atomic here is a bit unusual.
...
llvm-svn: 137662
2011-08-15 21:56:39 +00:00
cbe7feeab9
Fix PR10656. It's only profitable to use 128-bit inserts and extracts
...
when AVX mode is one. Otherwise is just more work for the type
legalizer.
llvm-svn: 137661
2011-08-15 21:45:54 +00:00
d899444347
There is no need to maintain a set to keep track of variables that use location expressions. In such cases, AT_location attribute's value will be a label.
...
llvm-svn: 137659
2011-08-15 21:43:21 +00:00
900d97719b
Fix warning.
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llvm-svn: 137658
2011-08-15 21:35:16 +00:00
3e4a965519
Simplify. Let DbgVariable keep track of variable's DBG_VALUE machine instruction.
...
llvm-svn: 137656
2011-08-15 21:24:36 +00:00
e86965ee19
Duncan pointed out that the LandingPadInst might read memory. (It might also
...
write to memory.) Marking it as such makes some checks for immobility go away.
llvm-svn: 137655
2011-08-15 21:14:31 +00:00
4d05198d1f
Fix llvm::CloneModule to correctly clone globals. Patch per bug report by Simon Moll on llvmdev.
...
llvm-svn: 137654
2011-08-15 21:05:06 +00:00
b9d5a63c86
Fix predicates methods on Instruction to handle atomic load/store correctly.
...
llvm-svn: 137652
2011-08-15 21:00:18 +00:00
5494adac67
Misc analysis passes that need to be aware of atomic load/store.
...
llvm-svn: 137650
2011-08-15 20:54:19 +00:00
91386c7be4
Atomic load/store support in LICM.
...
llvm-svn: 137648
2011-08-15 20:52:09 +00:00
1d5d2cac8c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
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Patch by James Molloy.
llvm-svn: 137647
2011-08-15 20:51:32 +00:00
de25f9aa8f
Remove dead classes.
...
llvm-svn: 137643
2011-08-15 20:11:11 +00:00
d9fb470758
The "landingpad" instruction will never be "trivially" dead.
...
llvm-svn: 137642
2011-08-15 20:10:51 +00:00
61a3ece665
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
...
llvm-svn: 137641
2011-08-15 20:08:25 +00:00
99819b527d
Simplify mapping to variable from its abstract variable info.
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When a variable is inlined multiple places, abstract variable keeps name, location, type etc.. info and all other concreate instances of the variable directly refers to abstract variable.
llvm-svn: 137637
2011-08-15 19:01:20 +00:00
3157f2eebe
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
...
llvm-svn: 137636
2011-08-15 19:00:06 +00:00
b9d82f411c
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
...
llvm-svn: 137635
2011-08-15 18:44:44 +00:00
d7d80aadd1
Refactor.
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llvm-svn: 137632
2011-08-15 18:40:16 +00:00
6e4d2c9fb7
Refactor.
...
llvm-svn: 137631
2011-08-15 18:35:42 +00:00
dd94d3426b
Don't try to sink the landingpad instruction. It's immobile.
...
llvm-svn: 137629
2011-08-15 18:23:40 +00:00
9af5b22b76
The landingpad instruction isn't loop-invariant.
...
llvm-svn: 137628
2011-08-15 18:22:49 +00:00
88294cdbe0
Mark the SCC as "might unwind" if we run into a 'resume' instruction.
...
llvm-svn: 137627
2011-08-15 18:22:00 +00:00
b9c0e0db53
Skip the insertion iterator past the landingpad instruction if there.
...
llvm-svn: 137626
2011-08-15 18:21:07 +00:00
dfd6ec3ce1
Refactor. Global variables are part of compile unit so let CompileUnit create new global variable.
...
llvm-svn: 137621
2011-08-15 17:57:41 +00:00
895437142a
Refactor. A subprogram is part of compile unit so let CompileUnit construct new subprogram.
...
llvm-svn: 137618
2011-08-15 17:24:54 +00:00
30694dcdeb
Update comment to reflect MC target machine refactor.
...
llvm-svn: 137615
2011-08-15 16:52:24 +00:00
55421f0c4d
Add inlining for the new EH scheme.
...
This builds off of the current scheme, but instead of llvm.eh.exception and
llvm.eh.selector, it uses the landingpad instruction. And instead of
llvm.eh.resume, it uses the resume instruction.
Because of the invariants in the landing pad instruction, a lot of code that's
currently needed to find the appropriate intrinsic calls for an invoke
instruction won't be needed once we go to the new EH scheme. The "FIXME"s tell
us what to remove after we switch.
llvm-svn: 137576
2011-08-14 08:01:36 +00:00
746e317953
This transform is not safe. Thanks to Eli for pointing that out!
...
llvm-svn: 137575
2011-08-14 04:51:49 +00:00
ae13df60a6
Don't attempt to add 'nsw' when intermediate instructions had no such guarantee.
...
llvm-svn: 137572
2011-08-14 03:41:33 +00:00
de49278c26
Teach instcombine to preserve the nsw bit by doing an after-the-fact analysis
...
when combining add and sub instructions. Patch by Pranav Bhandarkar!
llvm-svn: 137570
2011-08-14 01:45:19 +00:00
45620380b5
EE: Provide the symbol "lseek64" explicitly with <unistd.h> on Linux glibc.
...
With libcxx, it seems <unistd.h> would not be provided. Thanks to Ryuta Suzuki.
llvm-svn: 137567
2011-08-14 00:34:04 +00:00
6858b344ed
Fix PR 10635. When generating integer constants, the constant element type may
...
be illegal, even if the requested vector type is legal. Testcase is one of the
disabled ARM tests in the vector-select patch.
llvm-svn: 137562
2011-08-13 20:31:45 +00:00
d1de7764be
Expand VMOVQQQQ pseudo instructions.
...
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed. Our register allocator must be awesome!
llvm-svn: 137551
2011-08-13 05:14:55 +00:00
2be81acd77
Remove the last improper use of getGlobalContext() from LLVM.
...
This caused a race condition where a thread calls ~LLVMContextImpl which calls
Module::dropAllReferences which calls begin() on an empty ilist that would
create the sentinel, which racily accesses the global context.
This can not be fixed by locking inside createSentinel because the lock would
need to be shared with all users of the global context, including those that
reside outside LLVM's own code.
llvm-svn: 137546
2011-08-13 01:04:44 +00:00
02e737b08e
Move "atomic" and "volatile" designations on instructions after the opcode
...
of the instruction.
Note that this change affects the existing non-atomic load and store
instructions; the parser now accepts both forms, and the change is noted
in the release notes.
llvm-svn: 137527
2011-08-12 22:50:01 +00:00
2325474368
ARM STR_POST_IMM offset encoding fix in load/store optimizer.
...
Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.
rdar://9945172
llvm-svn: 137525
2011-08-12 22:20:41 +00:00
c53dd2ac01
Fix comment!
...
llvm-svn: 137521
2011-08-12 21:54:42 +00:00
f15dfe5818
The VPERM2F128 is a AVX instruction which permutes between two 256-bit
...
vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.
llvm-svn: 137519
2011-08-12 21:48:26 +00:00
960c8f71aa
Move code around and add comments
...
llvm-svn: 137518
2011-08-12 21:48:22 +00:00
2fcc1cfdce
Define unaligned load and store.
...
llvm-svn: 137515
2011-08-12 21:30:06 +00:00
f402f694e2
ARM expansion of pre-indexed store pseudos should maintain memoperands.
...
Partial fix for rdar://9945172.
llvm-svn: 137513
2011-08-12 21:02:34 +00:00
a52aa3c18f
Add checks for the landingpad instruction's clause values to make sure that
...
they're the correct type.
llvm-svn: 137511
2011-08-12 20:52:25 +00:00
2d1d7a11f8
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
...
llvm-svn: 137502
2011-08-12 20:36:11 +00:00
fae1475823
Initial commit of the 'landingpad' instruction.
...
This implements the 'landingpad' instruction. It's used to indicate that a basic
block is a landing pad. There are several restrictions on its use (see
LangRef.html for more detail). These restrictions allow the exception handling
code to gather the information it needs in a much more sane way.
This patch has the definition, implementation, C interface, parsing, and bitcode
support in it.
llvm-svn: 137501
2011-08-12 20:24:12 +00:00
60138eaf93
Fix decoding of ARM-mode STRH.
...
llvm-svn: 137499
2011-08-12 20:02:50 +00:00
1043e173bc
Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.
...
llvm-svn: 137494
2011-08-12 19:41:29 +00:00
3987a61c16
Fix decoding of pre-indexed stores.
...
llvm-svn: 137487
2011-08-12 18:12:39 +00:00
444034783e
Use ArrayRef.
...
llvm-svn: 137485
2011-08-12 18:10:19 +00:00
7bd6e6ebef
When constant double 0.0 is lowered, make sure 0 is copied directly from an
...
integer register to a floating point register. It is not valid to interpret
the value of a floating pointer register as part of a double precision
floating point value after a single precision floating point computational
or move instruction stores its result to the register.
- In the test case, the following code is generated before this patch is
applied:
mtc1 $zero, $f2 ; unformatted copy to $f2
mov.s $f0, $f2 ; $f0 is in single format
sdc1 $f12, 0($sp)
mov.s $f1, $f2 ; $f1 is in single format
c.eq.d $f12, $f0 ; $f0 cannot be interpreted as double
- The following code is generated after this patch is applied:
mtc1 $zero, $f0 ; unformatted copy to $f0
mtc1 $zero, $f1 ; unformatted copy to $f1
c.eq.d $f12, $f0 ; $f0 can be interpreted as double
Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and
provided the test case.
llvm-svn: 137484
2011-08-12 18:09:59 +00:00
a585102d3e
add ifdef's to let people easily remove these dead api for testing.
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llvm-svn: 137483
2011-08-12 18:08:19 +00:00
44f7ab4544
switch to the new struct api.
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llvm-svn: 137482
2011-08-12 18:07:26 +00:00
01becebef3
switch to the new struct apis.
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llvm-svn: 137481
2011-08-12 18:07:07 +00:00
335d399a0e
switch to use the new api for structtypes.
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llvm-svn: 137480
2011-08-12 18:06:37 +00:00
2f50231c10
forward to the correct constructor.
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llvm-svn: 137479
2011-08-12 18:03:30 +00:00
db4374a28a
Provide fast path as Jakob suggested.
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llvm-svn: 137478
2011-08-12 18:01:34 +00:00
c5798a3a59
Separate decoding for STREXD and LDREXD to make each work better.
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llvm-svn: 137476
2011-08-12 17:58:32 +00:00
8a2f747546
add two missing function impls
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llvm-svn: 137470
2011-08-12 17:43:05 +00:00
190552d3e0
add new accessors to reflect new terminology in struct types.
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llvm-svn: 137468
2011-08-12 17:31:02 +00:00
62da15a330
Revert r137310 because it does not optimize any code on ToT
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llvm-svn: 137466
2011-08-12 17:15:04 +00:00
75ec09c0e3
Whitespace and formatting. No functional change intended.
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llvm-svn: 137463
2011-08-12 16:45:18 +00:00
a41634e307
Silence a bunch (but not all) "variable written but not read" warnings
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when building with assertions disabled.
llvm-svn: 137460
2011-08-12 14:54:45 +00:00
91ea511436
MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does.
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llvm-svn: 137414
2011-08-12 01:51:29 +00:00
210bf8351d
findDeadCallerSavedReg fix: Missing NULL terminator in register arrays.
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Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it.
llvm-svn: 137404
2011-08-12 00:49:19 +00:00
10a18d55ce
Don't convert objc_autoreleaseReturnValue to objc_autorelease if the result
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is returned through a bitcast.
llvm-svn: 137402
2011-08-12 00:36:31 +00:00
121302772d
Don't let arbitrary calls disrupt nested retain+release pairs if
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the retains and releases all use the same SSA pointer value.
Also, don't let CFG hazards disrupt nested retain+release pair
optimizations.
llvm-svn: 137399
2011-08-12 00:26:31 +00:00
4767a1a117
Use an actual reverse-CFG reverse-postorder for the bottom-up traversal,
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rather than plain postorder, so that CFG constructs like single-exit loops
are reliably visited in a sensible order.
llvm-svn: 137398
2011-08-12 00:24:29 +00:00
1f582ba609
Simplify the interference checking code a bit.
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This is possible now that we now longer provide an interface to iterate
the interference overlaps.
llvm-svn: 137397
2011-08-12 00:22:04 +00:00
8cffa28af8
ARM vector compare to zero instruction assembly parsing support.
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llvm-svn: 137389
2011-08-11 23:51:13 +00:00
2b6860f0a1
Allow loop unrolling to get known trip counts from ScalarEvolution.
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SCEV unrolling can unroll loops with arbitrary induction variables. It
is a prerequisite for -disable-iv-rewrite performance. It is also
easily handles loops of arbitrary structure including multiple exits
and is generally more robust.
This is under a temporary option to avoid affecting default
behavior for the next couple of weeks. It is needed so that I can
checkin unit tests for updateUnloop.
llvm-svn: 137384
2011-08-11 23:36:16 +00:00
da0192d72b
Remove the InterferenceResult class.
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llvm-svn: 137381
2011-08-11 22:46:06 +00:00
cd14efaec2
Eliminate the last use of InterferenceResult.
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The Query class now holds two iterators instead of an InterferenceResult
instance. The iterators are used as bookmarks for repeated
collectInterferingVRegs calls.
llvm-svn: 137380
2011-08-11 22:46:04 +00:00
79d60d0e94
Enclose directive .cprestore with .set macro and nomacro to silence assembler
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warning.
llvm-svn: 137378
2011-08-11 22:42:31 +00:00
37f7e6b2f4
Remove no-longer-true comments. These are for the assembler, also.
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llvm-svn: 137375
2011-08-11 22:30:30 +00:00
e25942154c
ARM STRT assembly parsing and encoding.
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llvm-svn: 137372
2011-08-11 22:18:00 +00:00
eca346ee1a
Make the USAT16 operand decoder auto-generate-able.
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llvm-svn: 137371
2011-08-11 22:10:11 +00:00
ff0b442330
Add another accidentally omitted predicate operand.
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llvm-svn: 137370
2011-08-11 22:08:38 +00:00
2f7aa73312
Add missing predicate operand on SMLA and friends.
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llvm-svn: 137368
2011-08-11 22:05:38 +00:00
a2b8b60646
ARM load shifted register pre-index fix shift value asm parser encoding.
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llvm-svn: 137367
2011-08-11 22:05:09 +00:00
12d13efa21
Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
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llvm-svn: 137364
2011-08-11 21:52:38 +00:00
f05e744857
Making SEL decodings auto-generate-able.
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llvm-svn: 137363
2011-08-11 21:50:56 +00:00
8fbf023c9b
Add a dag combine to xform 256-bit shuffles into simple vector
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inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.
llvm-svn: 137362
2011-08-11 21:50:44 +00:00
88981ff168
Tidy up comment.
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llvm-svn: 137359
2011-08-11 21:41:59 +00:00
b685c9f011
Fix decoding support for STREXD and LDREXD.
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llvm-svn: 137356
2011-08-11 21:34:58 +00:00
da4f0eb12c
Remove more dead code.
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collectInterferingVRegs will be the primary function for interference
checks.
llvm-svn: 137354
2011-08-11 21:18:34 +00:00
d886f8cd8d
ARM STRH assembly parsing and encoding.
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llvm-svn: 137353
2011-08-11 21:17:22 +00:00
7e315fc37d
Fix typos in comments, and delete an unused function.
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llvm-svn: 137352
2011-08-11 21:06:32 +00:00
6d8c039ab1
Add isIndirectBranch flag.
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llvm-svn: 137351
2011-08-11 21:05:37 +00:00
7519336752
Privatize an unused part of the LiveIntervalUnion::Query interface.
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No clients are iterating over interference overlaps.
llvm-svn: 137350
2011-08-11 21:00:42 +00:00
3a850f28d0
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
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llvm-svn: 137347
2011-08-11 20:47:56 +00:00
05ff9d1f6d
Remove some dead code.
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The InterferenceResult iterator turned out to be less important than we
thought it would be. LiveIntervalUnion clients want higher level
information, like the list of interfering virtual registers.
llvm-svn: 137346
2011-08-11 20:41:41 +00:00
2ea19d1438
Tidy up. Remove unused template parameter.
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llvm-svn: 137345
2011-08-11 20:41:13 +00:00
887c0b1358
Improve operand validation for Thumb2 addressing modes.
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llvm-svn: 137344
2011-08-11 20:40:40 +00:00
Benjamin Kramer