Commit Graph

796 Commits

Author SHA1 Message Date
Matt Arsenault 2c33562cd6 R600/SI: Match not instruction.
llvm-svn: 205837
2014-04-09 07:16:16 +00:00
Tom Stellard 204e61bbdf R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies
llvm-svn: 205732
2014-04-07 19:45:45 +00:00
Tom Stellard 50122a5890 R600: Match 24-bit arithmetic patterns in a Target DAGCombine
Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.

This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched.  This occasionally
resulted in some instructions being incorrectly deleted from the
program.

v2:
  - Fix bug with 64-bit mul

llvm-svn: 205731
2014-04-07 19:45:41 +00:00
Tom Stellard 3cbe014027 R600: Replace dyn_cast + assert with cast
llvm-svn: 205730
2014-04-07 19:31:13 +00:00
Matt Arsenault 4be76e99fe Use std::swap
llvm-svn: 205723
2014-04-07 16:44:26 +00:00
Matt Arsenault 7939acd7fa Use .data() instead of &x[0]
llvm-svn: 205722
2014-04-07 16:44:24 +00:00
David Blaikie 2f7711242a MachineInstr: introduce explicit_operands and implicit_operands ranges
Makes iteration over implicit and explicit machine operands more
explicit (har har). Insipired by code review discussion for r205565.

llvm-svn: 205680
2014-04-05 22:42:04 +00:00
Matt Arsenault 5e1e4316c4 Fix tabs
llvm-svn: 205648
2014-04-04 20:13:08 +00:00
Craig Topper 840beec2d0 Make consistent use of MCPhysReg instead of uint16_t throughout the tree.
llvm-svn: 205610
2014-04-04 05:16:06 +00:00
Tom Stellard a0150cb6a9 R600: Correct opcode for BFE_INT
Acording to AMD documentation, the correct opcode for
BFE_INT is 0x5, not 0x4

Fixes Arithm/Absdiff.Mat/3 OpenCV test

Patch by: Bruno Jiménez

llvm-svn: 205562
2014-04-03 20:19:29 +00:00
Tom Stellard 7ed0b5235a R600/SI: Lower 64-bit immediates using REG_SEQUENCE
llvm-svn: 205561
2014-04-03 20:19:27 +00:00
Matt Arsenault d6c4326786 R600/SI: Remove leftover pattern splitting 64-bit ors.
It's now matched to the scalar 64-bit or and split later if
necessary.'

llvm-svn: 205252
2014-03-31 21:46:46 +00:00
Matt Arsenault f751d6272d Change shouldSplitVectorElementType to better match the description.
Pass the entire vector type, and not just the element.

llvm-svn: 205247
2014-03-31 20:54:58 +00:00
Matt Arsenault d7bdcc46a6 R600/SI: Implement shouldConvertConstantLoadToIntImm
llvm-svn: 205244
2014-03-31 19:54:27 +00:00
Matt Arsenault 378bf9c68b R600: Compute masked bits for min and max
llvm-svn: 205242
2014-03-31 19:35:33 +00:00
Matt Arsenault 4c53717787 R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.
llvm-svn: 205236
2014-03-31 18:21:18 +00:00
Matt Arsenault b34583661b R600: Add target nodes for BFM and BFI
llvm-svn: 205235
2014-03-31 18:21:13 +00:00
Tom Stellard 30f59417cf R600/SI: Implement SIInstrInfo::isTriviallyRematerializable()
llvm-svn: 205188
2014-03-31 14:01:56 +00:00
Tom Stellard 7ea3d6d420 R600/SI: Lower i64 SELECT by bitcasting to a vector type
This allows allows us to replace ISD::EXTRACT_ELEMENT, which is lowered
using shifts, with ISD::EXTRACT_VECTOR_ELT, which is a no-op.

llvm-svn: 205187
2014-03-31 14:01:55 +00:00
Tom Stellard 7277b008ee R600/SI: Return the correct index for VGPRs in getHWRegIndex()
The register index is stored in the low 8-bits of the encoding.

llvm-svn: 205186
2014-03-31 14:01:52 +00:00
Rafael Espindola 5904e12bfa Completely rewrite ELFObjectWriter::RecordRelocation.
I started trying to fix a small issue, but this code has seen a small fix too
many.

The old code was fairly convoluted. Some of the issues it had:

* It failed to check if a symbol difference was in the some section when
  converting a relocation to pcrel.
* It failed to check if the relocation was already pcrel.
* The pcrel value computation was wrong in some cases (relocation-pc.s)
* It was missing quiet a few cases where it should not convert symbol
  relocations to section relocations, leaving the backends to patch it up.
* It would not propagate the fact that it had changed a relocation to pcrel,
  requiring a quiet nasty work around in ARM.
* It was missing comments.

llvm-svn: 205076
2014-03-29 06:26:49 +00:00
Tim Northover 24f46618b2 R600: avoid calling std::next on an iterator that might be end()
This was causing my llc to go into an infinite loop on
CodeGen/R600/address-space.ll (just triggered recently by some allocator
changes).

llvm-svn: 205005
2014-03-28 13:52:56 +00:00
Rafael Espindola c03f44ca8a Remove another unused argument.
llvm-svn: 204961
2014-03-27 20:49:35 +00:00
Rafael Espindola 9ab380122a Remove unused argument.
llvm-svn: 204956
2014-03-27 20:41:17 +00:00
Matt Arsenault b517c8128e R600: Implement isZExtFree.
This allows 64-bit operations that are truncated to be reduced
to 32-bit ones.

llvm-svn: 204946
2014-03-27 17:23:31 +00:00
Matt Arsenault d125d74a73 R600/SI: Fix unreachable with a sext_in_reg to an illegal type.
llvm-svn: 204945
2014-03-27 17:23:24 +00:00
Matt Arsenault 90b733a3cf R600: Add a testcase for sext_in_reg I missed.
This sext_inreg i32 in i64 case was already handled, but not enabled.

llvm-svn: 204840
2014-03-26 18:31:06 +00:00
Matt Arsenault 0c274feedf R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp
Remove handling of select_cc, since it makes no sense to be there. This
now does nothing, but I'll be adding some handling of other target nodes
soon.

llvm-svn: 204743
2014-03-25 18:18:27 +00:00
Matt Arsenault db8b1d5b6c R600: Don't viewCFG() under DEBUG() except on failure.
Having these popping up every time you use -debug is really
irritating.

llvm-svn: 204664
2014-03-24 20:29:02 +00:00
Matt Arsenault 684dc80b6d R600/SI: Fix extra mov from legalizing 64-bit SALU ops.
Check the register class of each operand individually
to avoid an extra copy to a vgpr.

llvm-svn: 204662
2014-03-24 20:08:13 +00:00
Matt Arsenault 248b7b6ba1 R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.
No longer asserts, but now you get moves loading legal immediates
into the split 32-bit operations.

llvm-svn: 204661
2014-03-24 20:08:09 +00:00
Matt Arsenault f35182c783 R600/SI: Fix 64-bit bit ops that require the VALU.
Try to match scalar and first like the other instructions.
Expand 64-bit ands to a pair of 32-bit ands since that is not
available on the VALU.

llvm-svn: 204660
2014-03-24 20:08:05 +00:00
Matt Arsenault a7f1e0c44f R600: Implement isNarrowingProfitable.
llvm-svn: 204658
2014-03-24 19:43:31 +00:00
Matt Arsenault bd9958038c R600/SI: Move splitting 64-bit immediates to separate function.
llvm-svn: 204651
2014-03-24 18:26:52 +00:00
Matt Arsenault ad41d7b531 R600/SI: Fix 64-bit private loads.
llvm-svn: 204630
2014-03-24 17:50:46 +00:00
Tom Stellard 8c12fd9252 R600/SI: Fix warning with gcc 4.8.2
llvm-svn: 204618
2014-03-24 16:12:34 +00:00
Tom Stellard da99c6eff5 R600/SI: Promote fp64 SELECT to i64
This type promotion is replacing a Tablegen pattern and it is already
covered by existing tests.

llvm-svn: 204617
2014-03-24 16:07:30 +00:00
Tom Stellard 2c1c9de151 R600: Reorganize tablegen instruction definitions
Each GPU family now has its own file.

llvm-svn: 204615
2014-03-24 16:07:25 +00:00
Matt Arsenault 8e2581b11e R600/SI: Move instruction patterns to scalar versions.
Some of them also had the pattern on both, so this removes the
duplication.

llvm-svn: 204492
2014-03-21 18:01:18 +00:00
Tom Stellard 1583409e33 R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()
llvm-svn: 204476
2014-03-21 15:51:57 +00:00
Tom Stellard e038720702 R600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU()
llvm-svn: 204475
2014-03-21 15:51:54 +00:00
Tom Stellard def38c567d R600/SI: Use SGPR_(32|64) reg clases when lowering SI_ADDR64_RSRC
The SReg_(32|64) register classes contain special registers in addition
to the numbered SGPRs.  This can lead to machine verifier errors when
these register classes are used as sub-registers for SReg_128, since
SReg_128 only uses the numbered SGPRs.

Replacing SReg_(32|64) with SGPR_(32|64) fixes this problem, since
the SGPR_(32|64) register classes contain only numbered SGPRs.

Tests cases for this are comming in a later commit.

llvm-svn: 204474
2014-03-21 15:51:53 +00:00
Matt Arsenault 99395fa98f R600: Remove unused method declaration.
llvm-svn: 204357
2014-03-20 16:41:06 +00:00
Matt Arsenault dd78b8059b R600/SI: Add unused LDS 2 form instructions.
llvm-svn: 204275
2014-03-19 22:19:56 +00:00
Matt Arsenault d06ebd93e6 R600/SI: Add support for 64-bit LDS writes
llvm-svn: 204274
2014-03-19 22:19:54 +00:00
Matt Arsenault b943348cb9 R600/SI: Add support for 64-bit LDS loads.
v2:
  -Use correct opcode for DS_READ_64

llvm-svn: 204273
2014-03-19 22:19:52 +00:00
Matt Arsenault 99ed78926b R600/SI: Match i16 immediate offset of LDS instructions.
llvm-svn: 204272
2014-03-19 22:19:49 +00:00
Matt Arsenault 547aff20f5 R600/SI: Don't display the GDS bit.
It isn't actually used now, and probably never will be, plus it makes
tests less annoying. I also think SC prints GDS instructions as a
separate instruction name.

llvm-svn: 204270
2014-03-19 22:19:43 +00:00
Matt Arsenault 9cd8c38a32 R600/SI: Merge offset0 and offset1 fields for single address DS instructions v2
Also remove unused data fields from the DS_Load_Helper class.

v2:
  - Merge fields for DS_WRITE

llvm-svn: 204269
2014-03-19 22:19:39 +00:00
Matt Arsenault f45faaf30d Make methods static
llvm-svn: 204085
2014-03-17 22:23:09 +00:00