Commit Graph

289007 Commits

Author SHA1 Message Date
Adrian Prantl 3edc63a579 DwarfCompileUnit: Fix another assertion failure on malformed input
that is not rejected by the Verifier.

Thanks to Björn Pettersson for providing a reproducer!

llvm-svn: 331535
2018-05-04 16:10:43 +00:00
Zaara Syeda edc7a8c1e5 [PPC64] Remove support for ELF V1 ABI in LLD - buildbot fix
Fix buildbot error, failure to build with msvc due to error C2446
Use switch instead of ternary operator.

Differential Revision: https://reviews.llvm.org/D46316

llvm-svn: 331534
2018-05-04 16:04:04 +00:00
Erich Keane 425f48d480 [clang-cl] Print /showIncludes to stderr, if used in combination with /E, /EP or /P
This replicates 'cl.exe' behavior and allows for both preprocessor output and
dependency information to be extraced with a single compiler invocation.

This is especially useful for compiler caching with tools like Mozilla's sccache.

See: https://github.com/mozilla/sccache/issues/246

Patch By: fxb

Differential Revision: https://reviews.llvm.org/D46394

llvm-svn: 331533
2018-05-04 15:58:31 +00:00
Clement Courbet b18c34bc29 [llvm-exegesis] Fix pfm counter names for BDW.
Summary: They are not consistent with other microarchitectures.

Reviewers: gchatelet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D46434

llvm-svn: 331532
2018-05-04 15:26:12 +00:00
Simon Pilgrim 67cc246dca [X86] Cleanup SchedWriteFMA classes and use X86SchedWriteWidths directly.
Rename scalar and XMM versions, this is to match/simplify an upcoming change to split MUL/DIV/SQRT scalar/xmm/ymm/zmm classes.

llvm-svn: 331531
2018-05-04 15:20:18 +00:00
David Bolvansky 12e42f0f81 [bindings/go] Add Go bindings for volatile loads/stores
Reviewers: whitequark

Reviewed By: whitequark

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46235

llvm-svn: 331530
2018-05-04 15:14:00 +00:00
Zaara Syeda f61b0733a8 [PPC64] Remove support for ELF V1 ABI in LLD
The current support for V1 ABI in LLD is incomplete.
This patch removes V1 ABI support and changes the default behavior to V2 ABI,
issuing an error when using the V1 ABI. It also updates the testcases to V2
and removes any V1 specific tests.

Differential Revision: https://reviews.llvm.org/D46316

llvm-svn: 331529
2018-05-04 15:09:49 +00:00
Krzysztof Parzyszek 5291562acd [Hexagon] Remove leftover debugging code after r331527
llvm-svn: 331528
2018-05-04 15:07:30 +00:00
Krzysztof Parzyszek effcc2fb79 [Hexagon] Handle non-immediate constants in HexagonSplitDouble
llvm-svn: 331527
2018-05-04 15:04:48 +00:00
Simon Dardis 65b0492f0d [mips] Correct the predicates of sign extension instructions
And eliminatw the duplication of those instructions for microMIPS32r6.

Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D46117

llvm-svn: 331526
2018-05-04 15:00:54 +00:00
Simon Pilgrim bf4c8c0ff2 [X86] Add WriteVecMOVMSKY scheduler class
llvm-svn: 331525
2018-05-04 14:54:33 +00:00
David Major af79e30ad5 Comment fix.
Test commit!

llvm-svn: 331523
2018-05-04 14:41:49 +00:00
Adhemerval Zanella a57ef17ab6 [AArch64] Custom Lower MULLH{S,U} for v16i8, v8i16, and v4i32
This patch adds a custom lowering for ISD::MULH{S,U} used on divide by
constant optimization (DAGCombiner::BuildSDIV and DAGCombiner::BuildUDIV).

New patterns for smull and umull are added, so AArch64ISD::{S,U}MULL
can be correctly lowered to smull2 and umull2.

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D46009

llvm-svn: 331522
2018-05-04 14:33:55 +00:00
Peter Smith 2689d9f4f0 [ELF][AArch64] Add aarch64_elf64_le_vec emulation
Android AOSP has started specifying -m aarch64_elf64_le_vec as supported
by gold and BFD. This is a simple change to add the emulation so that LLD
doesn't immediately error when used as a linker in an AOSP build.

Differential Revision: https://reviews.llvm.org/D46429

llvm-svn: 331521
2018-05-04 14:28:29 +00:00
Alexander Kornienko a61d4c959a Remove explicit cfg-temporary-dtors=true
Summary:
Remove explicit -analyzer-config cfg-temporary-dtors=true in analyzer tests,
since this option defaults to true since r326461.

Reviewers: NoQ

Reviewed By: NoQ

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D46393

llvm-svn: 331520
2018-05-04 14:13:14 +00:00
Brian Gesiak ea9144e818 [Coroutines] Catch exceptions in await_resume
Summary:
http://wg21.link/P0664r2 section "Evolution/Core Issues 24" describes a
proposed change to Coroutines TS that would have any exceptions thrown
after the initial suspend point of a coroutine be caught by the handler
specified by the promise type's 'unhandled_exception' member function.
This commit provides a sample implementation of the specified behavior.

Test Plan: `check-clang`

Reviewers: GorNishanov, EricWF

Reviewed By: GorNishanov

Subscribers: cfe-commits, lewissbaker, eric_niebler

Differential Revision: https://reviews.llvm.org/D45860

llvm-svn: 331519
2018-05-04 14:02:37 +00:00
Krzysztof Parzyszek af73d2bdd9 [Hexagon] Skip reserved physical registers when updating liveness
llvm-svn: 331518
2018-05-04 13:59:05 +00:00
Andrea Di Biagio 24fb4fcb93 [llvm-mca] use colors for warnings and notes generated by InstrBuilder.
llvm-svn: 331517
2018-05-04 13:52:12 +00:00
Andrea Di Biagio 49c8591397 [llvm-mca] remove unused argument from method InstrBuilder::createInstrDescImpl.
We don't need to pass the instruction index to the method that constructs new
instruction descriptors.

No functional change intended.

llvm-svn: 331516
2018-05-04 13:10:10 +00:00
Simon Pilgrim be51b20127 [X86] Add SchedWriteFRnd fp rounding scheduler classes
Split off from SchedWriteFAdd for fp rounding/bit-manipulation instructions.

Fixes an issue on btver2 which only had the ymm version using the JSTC pipe instead of JFPA.

llvm-svn: 331515
2018-05-04 12:59:24 +00:00
Jeremy Morse 07e8daa66b [X86] Add test case for PR30290s failing behaviour
Following the advice in review D45022, this currently tests for the broken llc
output where an instruction is mis-scheduled. This test is committed in advance
to improve the eventual fixing patch in D45022, making the bad behaviour that
that patch fixes clearer.

llvm-svn: 331514
2018-05-04 10:05:10 +00:00
Peter Smith 9c116180a4 [ELF][AArch64] Add REQUIRES aarch64 to test [NFC]
Forgot to add REQUIRES aarch64 to the test I recently added for D46255.

llvm-svn: 331513
2018-05-04 09:10:18 +00:00
Jeremy Morse 71f17bf855 Word wrap a test-file comment to 80 columns
This is a test commit to check whether my account works.

llvm-svn: 331512
2018-05-04 08:58:06 +00:00
Peter Smith e72d3d32bb [ELF][AArch64] Implement the AArch64 TLSLD_LDST_LO12 family of relocs
Implement the following relocations for AArch64:
R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC

These are specified in ELF for the 64-bit Arm Architecture.

Fixes pr36727

Differential Revision: https://reviews.llvm.org/D46255

llvm-svn: 331511
2018-05-04 08:53:34 +00:00
Bjorn Pettersson 27a841fe83 [SelectionDAG] Refactor code by adding RegsForValue::getRegsAndSizes(). NFCI
Summary:
Added a helper method in RegsForValue to get a list with
all the <RegNumber, RegSize> pairs that we want to iterate
over in SelectionDAGBuilder::EmitFuncArgumentDbgValue and
in SelectionDAGBuilder::visitIntrinsicCall.

Reviewers: vsk

Reviewed By: vsk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46360

llvm-svn: 331510
2018-05-04 08:50:48 +00:00
Jonas Paulsson 72fe760592 [RegUsageInfoCollector] Bugfix for handling of register aliases.
Don't assume the alias of a defined reg is always already in the set.

As the test case in https://bugs.llvm.org/show_bug.cgi?id=36587 discovered,
it is wrong to assume that all the aliases of the defined register in the
*current function* is already present in the UsedPhysRegsMask.

This patch changes this so that any definition in the current function of a
phys-reg always results in all its aliases inserted into the set of defined
registers.

Review: Quentin Colombet
https://reviews.llvm.org/D45157

llvm-svn: 331509
2018-05-04 07:50:05 +00:00
Max Kazantsev 786032c1b7 [IRCE] Fix misuse of dyn_cast which leads to UB
llvm-svn: 331508
2018-05-04 07:34:35 +00:00
Dean Michael Berris 47e6b8c2c7 [XRay][compiler-rt] Support string-based config for Basic mode.
Summary:
This addresses http://llvm.org/PR36790.

This change allows the XRay Basic Mode implementation to use the
string-based initialization routine provided through
`__xray_log_init_mode(...)`. In the process, we've also deprecated some
flags defined for the `XRAY_OPTIONS` environment variable.

We then introduce another environment variable that can control the XRay
Basic Mode implementation through `XRAY_BASIC_OPTIONS`.

We also rename files from `xray_inmemory_log` to `xray_basic_logging` to
be more in line with the mode implementation.

Depends on D46174.

Reviewers: echristo, kpw, pelikan, eizan

Reviewed By: kpw

Subscribers: mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D46246

llvm-svn: 331507
2018-05-04 06:27:53 +00:00
Dean Michael Berris 5c389ace7d [XRay][compiler-rt] Support string-based config for FDR mode
Summary:
In this chage we add support for the string-based configuration
mechanism for configuring FDR mode.

We deprecate most of the `xray_fdr_log_*` flags that are set with the
`XRAY_OPTIONS` environment variable. Instead we make the FDR
implementation take defaults from the `XRAY_FDR_OPTIONS` environment
variable, and use the flags defined in `xray_fdr_flags.{h,cc,inc}` for
the options we support.

This change addresses http://llvm.org/PR36790.

Depends on D46173.

Reviewers: eizan, pelikan, kpw, echristo

Subscribers: llvm-commits, mgorny

Differential Revision: https://reviews.llvm.org/D46174

llvm-svn: 331506
2018-05-04 06:13:35 +00:00
Martin Storsjo cc80776eff [COFF] Implement the remaining ARM64 relocations
Now only IMAGE_REL_ARM64_ABSOLUTE and IMAGE_REL_ARM64_TOKEN
are unhandled.

Also add range checks for the existing BRANCH26 relocation.

Differential Revision: https://reviews.llvm.org/D46354

llvm-svn: 331505
2018-05-04 06:06:27 +00:00
Martin Storsjo 665c7a4479 [Driver] Don't warn about unused inputs in config files
This avoids warnings about unused linker parameters, just like
other flags are ignored if they're from config files.

Differential Revision: https://reviews.llvm.org/D46286

llvm-svn: 331504
2018-05-04 06:05:58 +00:00
Dean Michael Berris f0a6927932 [XRay][compiler-rt+docs] Introduce __xray_log_init_mode(...).
Summary:
This addresses http://llvm.org/PR36790.

The change Deprecates a number of functions and types in
`include/xray/xray_log_interface.h` to recommend using string-based
configuration of XRay through the __xray_log_init_mode(...) function. In
particular, this deprecates the following:

- `__xray_set_log_impl(...)` -- users should instead use the
`__xray_log_register_mode(...)` and `__xray_log_select_mode(...)` APIs.

- `__xray_log_init(...)` -- users should instead use the
`__xray_log_init_mode(...)` function, which also requires using the
`__xray_log_register_mode(...)` and `__xray_log_select_mode(...)`
functionality.

- `__xray::FDRLoggingOptions` -- in following patches, we'll be
migrating the FDR logging implementations (and tests) to use the
string-based configuration. In later stages we'll remove the
`__xray::FDRLoggingOptions` type, and ask users to migrate to using the
string-based configuration mechanism instead.

- `__xray::BasicLoggingOptions` -- same as `__xray::FDRLoggingOptions`,
we'll be removing this type later and instead rely exclusively on the
string-based configuration API.

We also update the documentation to reflect the new advice and remove
some of the deprecated notes.

Reviewers: eizan, kpw, echristo, pelikan

Reviewed By: kpw

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46173

llvm-svn: 331503
2018-05-04 06:01:12 +00:00
Michael Zolotukhin 131e74910c [MachineCSE] Rewrite a loop checking if a block is in a set of blocks without using a set. NFC.
Summary:
Using a set is unnecessary here an in some cases (see e.g. PR37277)
takes significant amount of time to just insert values into it. In this
particular case all we need is just to check if we find the block we are
looking for or not.

Reviewers: davide

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D46411

llvm-svn: 331502
2018-05-04 01:40:05 +00:00
Jim Ingham 0fd685353d Add children and child[N] properties to SBValue.i.
Also fixed some bad formatting in SBValue.i.

llvm-svn: 331501
2018-05-04 01:31:47 +00:00
Craig Topper 9510f70636 [LoopIdiomRecognize] Replace more unchecked dyn_casts with cast.
Two of these are immediately dereferenced on the next line. The other two are passed immediately to the IRBuilder constructor which can't handle a nullptr.

llvm-svn: 331500
2018-05-04 01:04:28 +00:00
Craig Topper cafae62ec9 [LoopIdiomRecognize] Use a regular array instead of a SmallVector and explicit ArrayRef.
llvm-svn: 331499
2018-05-04 01:04:26 +00:00
Craig Topper 8304231508 [LoopIdiomRecognize] Turn two uncheck dyn_casts into regular casts.
These are casts on users of a PHINode to Instruction. I think since PHINode is an Instruction any users would also be Instructions. At least a cast will give us an assertion if its wrong.

llvm-svn: 331498
2018-05-04 01:04:24 +00:00
Jason Molenda 07580ffe47 The on-ios-device command line lldb has an optimization where
when it and the inferior process both have the same shared cache
(a conglomeration of all libraries at the same fixed address for
all processes), lldb will read data out of its own memory to speed
things up.  The shared cache has a UUID, so lldb currently checks
that the UUID of its own shared cache matches that of the inferior.

This change adds one refinement to that -- it checks that the UUID
is the same and that the base address of the shared cache is the
same.  And only uses its local shared cache if they are both identical.

This involved using a different style of SPI with dyld to get lldb's
shared cache load address, but it's not especially difficult.

One unattractive part of the change is that I'm using the real
underlying types of task_t and kern_return_t instead of picking
them up from mach/mach.h.  The defines that get picked up there (a
lot from machine.h but others too) conflict with llvm/Support/MachO.h
even when I have mach.h included before our SafeMachO.h which
undefines most of the defines before including llvm/Support/MachO.h.
I'll need to augment the #undefs in SafeMachO.h to get this to
compile cleanly, but that'll be another day.

<rdar://problem/39868238> 

llvm-svn: 331497
2018-05-04 00:59:37 +00:00
Artem Dergachev 4cc0d4e823 [analyzer] NFC: Remove unused parameteer of StoreManager::CastRetrievedVal().
llvm-svn: 331496
2018-05-04 00:53:41 +00:00
Craig Topper a3f39ee33d [LoopIdiomRecognize] Add a test case to show incorrect transformation of an infinite loop with side effets into a countable loop using ctlz.
We currently recognize this idiom where x is signed and thus the shift in an ashr.

int cnt = 0;
while (x) {
  x >>= 1; // arithmetic shift right
  ++cnt;
}

and turn it into (bitwidth - ctlz(x)). And if there is anything else in the loop we will create a new loop that runs that many times.

If x is initially negative, the shift result will never be 0 and thus the loop is infinite. If you put something with side effects in the loop, that side effect will now only happen bitwidth times instead of an infinite number of times.

So this transform is only safe for logical shift right (which we don't currently recognize) or if we can prove that x cannot be negative before the loop.

llvm-svn: 331493
2018-05-03 23:50:29 +00:00
Adrian Prantl b51804e0d8 DWARFExpression: Convert file addresses to load addresses early on.
This is a change that only affects Swift and is NFC for the language
plugins on llvm.org. In Swift, we can have global variables with a
location such as DW_OP_addr <addr> DW_OP_deref. The DWARF expression
evaluator doesn't know how to apply a DW_OP_deref to a file address,
but at the very end we convert the file address into a load address.

This patch moves the file->load address conversion to right after the
result of the DW_OP_addr is pushed onto the stack so that a subsequent
DW_OP_deref (and potentially other operations) can be interpreted.

rdar://problem/39767528

Differential revision: https://reviews.llvm.org/D46362

llvm-svn: 331492
2018-05-03 23:32:47 +00:00
Volodymyr Sapsai 3835320617 Revert "Follow-up to r331378. Update tests to allow to use C atomics in C++."
It reverts commit r331484 because it caused test failures

    ThreadSanitizer-x86_64 :: Darwin/gcd-groups-destructor.mm
    ThreadSanitizer-x86_64 :: Darwin/libcxx-shared-ptr-stress.mm
    ThreadSanitizer-x86_64 :: Darwin/xpc-race.mm

Foundation.h transitively includes <atomic>, so we have a case of benign mixing
<stdatomic.h> and <atomic>.

llvm-svn: 331491
2018-05-03 23:06:37 +00:00
Tom Stellard b03c98d1a3 AMDGPU: Make getSubRegFromChannel a static member of AMDGPURegisterInfo
Summary:
This makes is possible to have R600RegisterInfo and SIRegisterInfo
not inherit from AMDGPURegisterInfo.

Reviewers: arsenm, nhaehnle

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D46280

llvm-svn: 331490
2018-05-03 22:38:06 +00:00
Simon Pilgrim 542b20d656 [X86] Add WriteDPPD/WriteDPPS dot product scheduler classes
llvm-svn: 331489
2018-05-03 22:31:19 +00:00
Simon Pilgrim 0aed731516 [X86][Znver1] Use SchedAlias to tag microcoded scheduler classes
Avoids extra entries in the class tables.

Found a typo that missed the MMX_PHSUBSW instruction.

llvm-svn: 331488
2018-05-03 22:12:23 +00:00
Justin Bogner 33e0ae0d8f Fix include of config.h that was incorrectly changed in r331184
The RWMutex implementation depends on config.h macros (specifically
HAVE_PTHREAD_H and HAVE_PTHREAD_RWLOCK_INIT), so we need to be
including it and not just llvm-config.h here or we fall back to a much
slower implementation.

llvm-svn: 331487
2018-05-03 21:59:13 +00:00
Sanjay Patel e7b6654711 [InstCombine] refine select-of-constants to bitwise ops
Add logic for the special case when a cmp+select can clearly be
reduced to just a bitwise logic instruction, and remove an 
over-reaching chunk of general purpose bit magic. The primary goal 
is to remove cases where we are not improving the IR instruction 
count when doing these select transforms, and in all cases here that 
is true.

In the motivating 3-way compare tests, there are further improvements
because we can combine/propagate select values (not sure if that
belongs in instcombine, but it's there for now).

DAGCombiner has folds to turn some of these selects into bit magic,
so there should be no difference in the end result in those cases.
Not all constant combinations are handled there yet, however, so it
is possible that some targets will see more cmov/csel codegen with
this change in IR canonicalization. 

Ideally, we'll go further to *not* turn selects into multiple 
logic/math ops in instcombine, and we'll canonicalize to selects.
But we should make sure that this step does not result in regressions
first (and if it does, we should fix those in the backend).

The general direction for this change was discussed here:
http://lists.llvm.org/pipermail/llvm-dev/2016-September/105373.html
http://lists.llvm.org/pipermail/llvm-dev/2017-July/114885.html

Alive proofs for the new bit magic:
https://rise4fun.com/Alive/XG7

Differential Revision: https://reviews.llvm.org/D46086

llvm-svn: 331486
2018-05-03 21:58:44 +00:00
Tom Stellard abc9871d60 GlobalISel: Use a callback to compute constrained reg class for unallocatble registers
Summary:
constrainOperandRegClass() currently fails if it tries to constrain the
register class of an operand that is defeined with an unallocatable register
class.  This patch resolves this by adding a target callback to compute
register constriants in this case.

This is required by the AMDGPU because many of its instructions have source opreands
defined with the unallocatable register classe VS_32 which is a union of two allocatable
register classes VGPR_32 and SReg_32.

Reviewers: dsanders, aditya_nandakumar

Reviewed By: aditya_nandakumar

Subscribers: rovka, kristof.beyls, tpr, llvm-commits

Differential Revision: https://reviews.llvm.org/D45991

llvm-svn: 331485
2018-05-03 21:44:16 +00:00
Volodymyr Sapsai 6e713d9866 Follow-up to r331378. Update tests to allow to use C atomics in C++.
Reviewers: kubamracek

Reviewed By: kubamracek

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D46363

llvm-svn: 331484
2018-05-03 21:30:47 +00:00
Craig Topper ce716347af [X86] Make __builtin_ia32_directstore_u32 and __builtin_ia32_movdir64b 'nothrow'
These builtins snuck in while I was in the middle of adding nothrow to the other builtins in my local clone and I guess I missed them.

llvm-svn: 331483
2018-05-03 21:01:35 +00:00