Commit Graph

193268 Commits

Author SHA1 Message Date
Florian Hahn 0c5b6e2ea5 Recommit "[SCCP] Use ValueLatticeElement instead of LatticeVal (NFCI)"
This patch should fix the cause of the stage2 failures and
PR45185.

This reverts the revert commit c52f839e72.
2020-03-13 17:03:22 +00:00
Simon Pilgrim a2db388dce [CostModel][X86] Improve ISD::CTTZ costs accounting for BSF/TZCNT implementations 2020-03-13 16:51:13 +00:00
Simon Pilgrim ec3218dbee [X86] Add cttz/ctlz tests for i686 with CMOV target 2020-03-13 16:51:13 +00:00
Ehud Katz 18eae33122 [SCEV] Fix usage of invalid IP with FoldingSet
Fix the use of invalid Insertion Point pointer with the UniqueSCEVs FoldingSet,
which caused memory corruption.
2020-03-13 18:36:58 +02:00
Tyker 2543567c41 [AssumeBundles] filter usefull attriutes to preserve
Summary:
This patch will filter attributes to only preserve those that are usefull.
In the case of NoAlias it is filtered out not because it isn't usefull
but because it is incorrect to preserve it as it is only valdi for the
duration of the function.

Reviewers: jdoerfert

Reviewed By: jdoerfert

Subscribers: jdoerfert, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75828
2020-03-13 17:35:47 +01:00
Tyker 69375fd0a3 [AssumeBundles] Preserve Information in the inliner
Summary:
during inling Create and insert an llvm.assume with attributes to preserve them.
to prevent any changes for now generation of llvm.assume is under a flag disabled by default.

Reviewers: jdoerfert

Reviewed By: jdoerfert

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75825
2020-03-13 17:35:47 +01:00
Alexandre Ganea a7325298e1 [CodeView] Align type records on 4-bytes when emitting PDBs
When emitting PDBs, the TypeStreamMerger class is used to merge .debug$T records from the input .OBJ files into the output .PDB stream.
Records in .OBJs are not required to be aligned on 4-bytes, and "The Netwide Assembler 2.14" generates non-aligned records.

When compiling with -DLLVM_ENABLE_ASSERTIONS=ON, an assert was triggered in MergingTypeTableBuilder when non-ghash merging was used.
With ghash merging there was no assert.
As a result, LLD could potentially generate a non-aligned TPI stream.

We now align records on 4-bytes when record indices are remapped, in TypeStreamMerger::remapIndices().

Differential Revision: https://reviews.llvm.org/D75081
2020-03-13 12:22:19 -04:00
omarahmed1111 b285b333dc [Attributor] Detect possibly unbounded cycles in functions
This patch add mayContainUnboundedCycle helper function which checks whether a function has any cycle which we don't know if it is bounded or not.
Loops with maximum trip count are considered bounded, any other cycle not.
It also contains some fixed tests and some added tests contain bounded and
unbounded loops and non-loop cycles.

Reviewed By: jdoerfert, uenoku, baziotis

Differential Revision: https://reviews.llvm.org/D74691
2020-03-13 11:17:33 -05:00
Pankaj Gode bf990530ae [Attributor] Improve noalias preservation using reachability
Resolution for below fixme:
(ii) Check whether the value is captured in the scope using AANoCapture.
FIXME: This is conservative though, it is better to look at CFG and
             check only uses possibly executed before this callsite.

Propagates caller argument's noalias attribute to callee.

Reviewed by: jdoerfert, uenoku

Reviewers: jdoerfert, sstefan1, uenoku

Subscribers: uenoku, sstefan1, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D71617
2020-03-13 21:09:08 +05:30
Simon Pilgrim 846c614f54 [X86] combineExtractWithShuffle - pull out repeated getSizeInBits() call. NFC. 2020-03-13 15:36:04 +00:00
Simon Pilgrim fe047fbccc [X86] LowerEXTRACT_VECTOR_ELT - pull out repeated getOperand() calls. NFC.
Also, cleanup LowerEXTRACT_VECTOR_ELT_SSE4 comments which had references to non-constant extraction indices.
2020-03-13 15:36:02 +00:00
Fangrui Song 7b74b0d4e5 [llvm-objdump] --syms: print 'u' for STB_GNU_UNIQUE
GCC when configured with --enable-gnu-unique (default on glibc>=2.11)
emits STB_GNU_UNIQUE for certain objects which are otherwise emitted as
STT_OBJECT, such as an inline function's static local variable or its
guard variable, and a static data member of a template.

Clang does not implement -fgnu-unique.

Implementing it as a binding is strange and the feature itself is
considered by some as a misfeature.

Reviewed By: grimar, jhenderson

Differential Revision: https://reviews.llvm.org/D75797
2020-03-13 08:04:09 -07:00
Fangrui Song e799405e53 [llvm-objdump] --syms: print 'i' for STT_GNU_IFUNC
Reviewed By: grimar, Higuoxing, jhenderson

Differential Revision: https://reviews.llvm.org/D75793
2020-03-13 08:02:36 -07:00
Fangrui Song 0bd3da5bfa [llvm-objdump][test] Reorganize ELF --syms tests
Merge symbol-table-elf.test and common-symbol-elf.test, and add some
more tests (invalid st_type, STT_COMMON, STT_GNU_IFUNC, STT_HIOS, STT_LOPROC, SHN_UNDEF, SHN_ABS, SHN_COMMON, STB_GNU_UNIQUE, invalid binding, etc) to test/llvm-objdump/ELF/symbol-table.test

The naming follows test/llvm-{readobj,objcopy}/ELF .

Some discrepancy from GNU objdump:

* STT_COMMON: can be produced with `ld.bfd -r -z common`, but it almost never exists in practice
* STT_GNU_IFUNC: will be fixed by D75793
* STB_GNU_UNIQUE: will be fixed by D75797
* STT_TLS: GNU objdump does not print 'O'
* unknown binding: GNU objdump does not print 'g'. This probably does not matter.
* A reserved symbol index is displayed as *ABS* in GNU objdump. It is not clear what we should print.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D75796
2020-03-13 08:00:59 -07:00
Matt Arsenault 6bbc1737e0 TableGen: Fix typo 2020-03-13 10:45:28 -04:00
Sanjay Patel cbeffa3f6c [SimplifyCFG] convert if-else chain to switch; NFC
Fix formatting of related function names while changing the code.
2020-03-13 10:28:41 -04:00
Nico Weber 86eb2c3991 Revert "[ObjC][ARC] Don't remove autoreleaseRV/retainRV pairs if the call isn't"
This reverts commit 1f5b471b8b.
Causes asserts when building code with arc. See
https://bugs.chromium.org/p/chromium/issues/detail?id=1061289#c2
for a full repro. Will post a creduced repro once creduce is done
running.
2020-03-13 10:16:02 -04:00
LLVM GN Syncbot 73d8a324ec [gn build] Port 512767eb3f 2020-03-13 14:09:37 +00:00
Clement Courbet ffe3515aa7 [ExpandMemCmp][NFC] Add more tests. 2020-03-13 15:06:52 +01:00
Ehud Katz fcc2238b8b [SCEV] Add missing cache queries
Calculating SCEVs can be cumbersome, and may take very long time (even
hours, for very long expressions). To prevent recalculating expressions
over and over again, we cache them.
This change add cache queries to key positions, to prevent recalculation
of the expressions.

Fix PR43571.

Differential Revision: https://reviews.llvm.org/D70097
2020-03-13 15:32:43 +02:00
Andrzej Warzynski a0c15ed460 [AArch64][SVE] Add the @llvm.aarch64.sve.dup.x intrinsic
Summary:
This intrinsic implements the unpredicated duplication of scalar values
and is mapped to (through ISD::SPLAT_VECTOR):
  * DUP <Zd>.<T>, #<imm>
  * DUP <Zd>.<T>, <R><n|SP>

Reviewed by: sdesmalen

Differential Revision: https://reviews.llvm.org/D75900
2020-03-13 12:40:22 +00:00
Alexandre Ganea 28ad9fc208 [Clang][Driver] In -fintegrated-cc1 mode, avoid crashing on exit after a compiler crash
After a crash catched by the CrashRecoveryContext, this patch prevents from accessing dangling pointers in TimerGroup structures before the clang tool exits. Previously, the default TimerGroup had internal linked lists which were still pointing to old Timer or TimerGroup instances, which lived in stack frames released by the CrashRecoveryContext.

Fixes PR45164.

Differential Revision: https://reviews.llvm.org/D76099
2020-03-13 08:15:35 -04:00
David Green 2c6c169dbd [ARM] Optimise ASRL/LSRL to smaller shifts using demand bits.
The ASRL/LSRL long shifts are generated from 64bit shifts. Once we have
them, it might turn out that enough of the 64bit result was not required
that we can use a smaller shift to perform the same result. As the
smaller shift can in general be folded in more way, such as into add
instructions in one of the test cases here, we can use the demand bit
analysis to prefer the smaller shifts where we can.

Differential Revision: https://reviews.llvm.org/D75371
2020-03-13 10:09:03 +00:00
Nico Weber 5c68043b9f [gn build] (manually) port ce79c4246 2020-03-13 06:08:28 -04:00
Georgii Rymar 6f3de2e53d [yaml2obj][obj2yaml][test] - Add base tests for relocation addends.
We had no test for `Addend` field of a relocation. Though the
current behavior is not ideal and might need to be fixed.

This patch adds 2 test cases to document the current
behavior and add a few FIXMEs. These FIXME are fixed in the
follow-up: https://reviews.llvm.org/D75527

Differential revision: https://reviews.llvm.org/D75528
2020-03-13 13:07:46 +03:00
David Green f67d93dc23 [ARM] Constant long shift combines
This changes the way that asrl and lsrl intrinsics are lowered, going
via a the ISEL ASRL and LSLL nodes instead of straight to machine nodes.
On top of that, it adds some constant folds for long shifts, in case it
turns out that the shift amount was either constant or 0.

Differential Revision: https://reviews.llvm.org/D75553
2020-03-13 08:54:59 +00:00
Juneyoung Lee c39cb1c0dd [CodeGenPrepare] Expand freeze conversion to support fcmp and icmp with null
Summary:
This is a simple patch that expands https://reviews.llvm.org/D75859 to pointer comparison and fcmp

Checked with Alive2

Reviewers: reames, jdoerfert

Reviewed By: jdoerfert

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76048
2020-03-13 17:21:33 +09:00
Juneyoung Lee 48b901b0e1 Add tests to Transforms/CodeGenPrepare/X86/freeze-cmp.ll before commiting D76048 2020-03-13 17:18:42 +09:00
QingShan Zhang d0fb34dc09 [PowerPC] Replace the PPCISD:: SExtVElems with ISD::SIGN_EXTEND_INREG to leverage the combine rules
The PPCISD::SExtVElems was added by commit https://reviews.llvm.org/D34009. However,
we have another ISD node ISD::SIGN_EXTEND_INREG that perfectly match the semantics
of SExtVElems. And the DAGCombiner has some combine rules for SIGN_EXTEND_INREG
that produce better code.

Differential Revision: https://reviews.llvm.org/D70771
2020-03-13 07:28:28 +00:00
Craig Topper 09c8f38924 [X86] Add isel patterns for X86VBroadcast with i16 truncates from i16->i64 zextload/extload.
We can form vpbroadcastw with a folded load.

We had patterns for i16->i32 zextload/extload, but nothing prevents
i64 from occuring.

I'd like to move this all to DAG combine to fix more cases, but
this is trivial fix to minimize test diffs when moving to a combine.
2020-03-13 00:10:48 -07:00
Craig Topper 51a4c6125c [X86] Add test cases for failures to form vbroadcastw due to isTypeDesirableForOp preventing load shrinking to i16.
These are based on existing test cases but use i64 instead of i32.
Some of these end up with i64 zextload/extloads from i16 that we
don't have isel patterns for.

Some of the other cases fail because isTypeDesirableForOp prevents
shrinking the (trunc (i64 (srl (load)))) directly. So we try
to shrink based on the (i64 (srl (load))) but we need 64 - shift_amount
to be a power of 2 to do that shrink.
2020-03-12 23:20:05 -07:00
Johannes Doerfert a198adb490 [Attributor] IPO across definition boundary of a function marked alwaysinline
Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D75590
2020-03-13 01:06:12 -05:00
Johannes Doerfert 40815a4957 Revert "[Attributor] Enable test with update check lines"
This reverts commit 13def55b3f.

This broke a buildbot, will investigate.
2020-03-13 00:59:47 -05:00
Amy Kwan 1ba3d2639d [PowerPC][NFC] Rename instruction formats in PPCInstrPrefix.td
This patch renames some of the instruction formats within PPCInstrPrefix.td to
adopt a more uniform naming convention. It also adds the naming convention
extension, `_MEM` to indicate instruction formats for memory ops.

Differential Revision: https://reviews.llvm.org/D75819
2020-03-13 00:50:08 -05:00
Johannes Doerfert 1c9c23d60e [OpenMP][Opt][NFC] Add test case for known runtime function attributes
This test somehow did not make it in before.
2020-03-13 00:28:14 -05:00
rathod-sahaab 263c4a3c75 Fix compiler warning when compiling without asserts
This patch aims to prevent warning-as-error failures in release build.
As suggested in this comment
https://reviews.llvm.org/D69930#1910922

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D75970
2020-03-13 00:26:49 -05:00
Dylan McKay c480c584a0 [AVR] Include AVR by default in LLVM builds
This was initially committed and promptly reverted in 9059056e27
after a MSan failure was found by the sanitizer bots.

These have since been fixed.

Summary:
This patch makes the AVR backend an official target of LLVM, serving
as a request for comments for moving the AVR backend out of
experimental.

A future patch will move the LLVM AVR buildbot (llvm-avr-linux) from the
staging buildmaster to the production buildmaster, so error emails will
start to go out.

Summary of the backend
----------------------

  - 16-bit little endian
  - AsmParser based assembly parser
  - uses the MC library for generating AVR ELFs
  - most logic driven from standard TableGen-erated tables like other
    backends
  - passes all of the test suite under `check-all`, including generic
    CodeGen and DebugInfo tests
  - Used in two frontends
  - Limited, but functional support for DebugInfo and LLVM DWARF dumping
  - Binary compatible with AVR-GCC and avr-{libc,libgcc} for the most part
  - Cannot lower 32-bit shifts due to a bug, can lower shifts larger or
    smaller
  - Supports assembly/MC for all the entire AVR ISA, generally generates poorly
    optimized machine instructions, with most focus thus far on correctness

I've added reviewers and subscribers from previous patches where backends were made official,
and those who participated in the recent thread on llvm-dev, please add anybody I've missed.

The most recent discussion on this topic can be found in the llvm-dev thread [Moving the AVR backend out of experimental](https://lists.llvm.org/pipermail/llvm-dev/2020-February/139158.html)

Reviewers: chandlerc, lattner, rengolin, tstellar, arsenm, thakis, simoll, asb

Reviewed By: rengolin, thakis

Subscribers: CryZe, wdng, mgorny, aprantl, Jim, hans, aykevl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75099
2020-03-13 17:40:30 +13:00
Johannes Doerfert 13def55b3f [Attributor] Enable test with update check lines
The test disabled in 528a6a1d4c is enabled
again with the check lines for 9708279c72.
2020-03-12 23:24:15 -05:00
QingShan Zhang e601196833 [NFC][DAGCombine] Move the fold of a*b-c and a-b*c into lambda function
This will help the review of https://reviews.llvm.org/D75982. It is
a simple code refactor.
2020-03-13 02:35:46 +00:00
Arlo Siemsen 1478ed69d3 Add support for SHA256 source file checksums in debug info
LLVM currently supports CSK_MD5 and CSK_SHA1 source file checksums in
debug info. This change adds support for CSK_SHA256 checksums.

The SHA256 checksums are supported by the CodeView debug format.

Reviewed By: aprantl

Differential Revision: https://reviews.llvm.org/D75785
2020-03-12 16:32:05 -07:00
Nico Weber 03f5f6bebd [gn build] (manually) port eb41cc6198 2020-03-12 19:29:09 -04:00
David Blaikie dcaf13a404 CFGDiff: Fix one place where I'd left BasicBlock* hardcoded 2020-03-12 16:18:21 -07:00
Huihui Zhang f4f2706572 [ConstantFold][SVE] Fix constant folding for scalable vector compare instruction.
Summary:
Do not iterate on scalable vector. Also do not return constant scalable vector
from ConstantInt::get().
Fix result type by using getElementCount() instead of getNumElements().

Reviewers: sdesmalen, efriedma, apazos, huntergr, willlovett

Reviewed By: efriedma

Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73753
2020-03-12 16:15:38 -07:00
Matt Arsenault ccc6e780c8 AMDGPU: Directly annotate functions if they have calls
Currently we infer whether the flat-scratch-init kernel input should
be enabled based on calls. Move this handling, so we can decide if the
full set of ABI inputs is needed in kernels. Ideally we would have an
analysis of some sort, rather than the function attributes.
2020-03-12 19:10:59 -04:00
Matt Arsenault 1fdb03808b CodeGen: Add constexpr to Register constructors 2020-03-12 19:10:59 -04:00
Lang Hames 7266a8bfeb [ORC] Enable exception handling in JIT'd code when using LLJIT on Darwin.
This patch enables exception handling in code added to LLJIT on Darwin by
adding an orc::EHFrameRegistrationPlugin instance to the ObjectLinkingLayer
(which is currently used on Darwin only).
2020-03-12 15:33:56 -07:00
Lang Hames 214a9f0dd4 [ORC] Add a mutex to guard EHFrameRegistrationPlugin data structures.
These may be accessed from multiple threads if concurrent materialization is
enabled in ORC.

Testcase coming in a follow-up patch that enables eh-frame registration for
LLJIT.
2020-03-12 15:33:56 -07:00
Stanislav Mekhanoshin a73528649c [AMDGPU] Simplify exec copies
The patch removes late endcf handling and only leaves the
related portion with redundant exec mask copy elimination.

Differential Revision: https://reviews.llvm.org/D76095
2020-03-12 14:54:19 -07:00
Huihui Zhang 118abf2017 [SVE] Update API ConstantVector::getSplat() to use ElementCount.
Summary:
Support ConstantInt::get() and Constant::getAllOnesValue() for scalable
vector type, this requires ConstantVector::getSplat() to take in 'ElementCount',
instead of 'unsigned' number of element count.

This change is needed for D73753.

Reviewers: sdesmalen, efriedma, apazos, spatel, huntergr, willlovett

Reviewed By: efriedma

Subscribers: tschuett, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74386
2020-03-12 13:22:41 -07:00
Simon Pilgrim e91feeed21 [AMDGPU] Add ISD::FSHR -> ALIGNBIT support
This patch allows ISD::FSHR(i32) patterns to lower to ALIGNBIT instructions.

This improves test coverage of ISD::FSHR matching - x86 has both FSHL/FSHR instructions and we prefer FSHL by default.

Differential Revision: https://reviews.llvm.org/D76070
2020-03-12 20:16:57 +00:00